UltraScale Architecture Memory Resources User Guide

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UltraScale ArchitectureMemory ResourcesUser GuideUG573 (v1.12) March 17, 2021

Revision HistoryThe following table shows the revision history for this document.DateVersionRevision03/17/20211.12Added additional bullet to list before Table 1-3. Revised values, default, and typefor IS XX INVERTED attributes in Table 2-5.08/18/20201.11Revised important notes in Block RAM Summary, Common-Clock/Single-ClockFIFO, and Block RAM and UltraRAM Differences.02/04/20191.10Added information on common and independent clocks in Address Collision.Revised port A to write port and port B to read port in Simple Dual-Port Block RAM.Removed content clear from UltraRAM Key Features.02/09/20181.9Revised description for EN A and EN B ports in Table 2-2. Revised Figure 2-16.11/14/20171.8Revised important note in Common-Clock/Single-Clock FIFO and added note to SetEnable Auto Sleep Mode – EN AUTO SLEEP MODE. Revised UltraRAM Summary.Removed Figure 2-28 and associated verbiage.08/10/20171.7Added important note to Common-Clock/Single-Clock FIFO. Revised ECCEncode-Only Read.05/04/20171.6Updated Table 2-5.03/15/20171.5Revised important note in Block RAM Summary. Added note 2 to Table 1-16.Revised Reset – RST A, RST B. Added UltraRAM Timing Diagrams.07/20/20161.4Revised Differences from Previous Generations, Synchronous Dual-Port andSingle-Port RAMs, Power Saving – RDADDRCHANGE[A B], Power Gating EnableInput – SLEEP, Data-Out Buses – DOUT A, DOUT B, Read Status Output –RDACCESS A, RDACCESS B, Optional Cascade Register Stage – REG CAS [A B],Cascading UltraRAM and Matrix Configurations, and Cascade User Attributes.Added note to Table 1-16 and Table 1-32. Updated Table 2-5. AddedAVG CONS INACTIVE CYCLES, MATRIX ID, NUM URAM IN MATRIX, andNUM UNIQUE SELF ADDR A B Attributes. Updated Figure 2-1 and Figure 2-5.11/24/20151.3Added UltraScale device information. Updated Introduction to the UltraScaleArchitecture to include UltraScale information. Updated important note inBlock RAM Summary. Added introductory paragraph to RAMB18/36 Unused Inputs.Reorganized user guide by incorporating previous Chapter 2 (Built-in FIFO) andChapter 3 (Built-in Error Correction) into Chapter 1, Block RAM Resources, andadding a new Chapter 2, UltraRAM Resources.02/24/20151.2Updated Content Initialization – INIT xx.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback2

DateVersionRevision08/14/20141.1Updated bullet 11 in Block RAM Summary. Changed description of CASDINPA[3:0]and CASDINB[31:0] in Table 1-8. Updated description of DOB REG in Table 1-16.Updated WDADDREN input in Figure 1-6. Added Table 1-14. Updated CascadableBlock RAM. Minor changes in SLEEP and Power Saving – SLEEP ASYNC. Minorchanges to descriptions in Common-Clock/Single-Clock FIFO. Added SLEEP inputto Figure 1-21 and Figure 1-22. Added SLEEP port and changed descriptions ofCASOREGIMUX, CASOREGIMUXEN, CASDOMUX, and CASDOMUXEN in Table 1-25.Updated Table 1-26. Added Table 1-27. Updated PROG EMPTY THRESH,PROG FULL THRESH, and REGISTER MODE in Chapter 1. RemovedPROG EMPTY THRESH Range for FIFO18E2/FIFO36E2 and PROG FULL THRESHRange for FIFO18E2/FIFO36E2 tables in Chapter 2. Updated CASOUTSBITERR,CASINDBITERR, and CASOUTSBITERR in Table 1-8.12/10/20131.0Initial Xilinx release.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback3

Table of ContentsRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Chapter 1: Block RAM ResourcesIntroduction to the UltraScale Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Block RAM Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Differences from Previous Generations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Block RAM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Synchronous Dual-Port and Single-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Additional Block RAM Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Block RAM Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Block RAM Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Block RAM Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39Block RAM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Block RAM and FIFO Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Block RAM Initialization in VHDL or Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Additional RAMB18E2 and RAMB36E2 Primitive Design Considerations . . . . . . . . . . . . . . . . . . . . 49Block RAM Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Built-in FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Built-in Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Chapter 2: UltraRAM ResourcesUltraRAM Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92UltraRAM Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93UltraRAM Cascade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94UltraRAM Error Correction Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Block RAM and UltraRAM Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95UltraRAM Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97UltraRAM Port Names and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100UltraRAM Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Dual Port SRAM Array Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Built-in Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124UltraRAM Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback4

Appendix A: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Solution Centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback1371371371381385

Chapter 1Block RAM ResourcesIntroduction to the UltraScale ArchitectureThe Xilinx UltraScale architecture is the first ASIC-class architecture to enablemulti-hundred gigabit-per-second levels of system performance with smart processing,while efficiently routing and processing data on-chip. UltraScale architecture-based devicesaddress a vast spectrum of high-bandwidth, high-utilization system requirements by usingindustry-leading technical innovations, including next-generation routing, ASIC-likeclocking, 3D-on-3D ICs, multiprocessor SoC (MPSoC) technologies, and new powerreduction features. The devices share many building blocks, providing scalability acrossprocess nodes and product families to leverage system-level investment across platforms.Virtex UltraScale devices provide the highest performance and integration capabilitiesin a FinFET node, including both the highest serial I/O and signal processing bandwidth, aswell as the highest on-chip memory density. As the industry's most capable FPGA family,the Virtex UltraScale devices are ideal for applications including 1 Tb/s networking anddata center and fully integrated radar/early-warning systems.Virtex UltraScale devices provide the greatest performance and integration at 20 nm,including serial I/O bandwidth and logic capacity. As the industry's only high-end FPGA atthe 20 nm process node, this family is ideal for applications including 400G networking,large scale ASIC prototyping, and emulation.Kintex UltraScale devices provide the best price/performance/watt balance in a FinFETnode, delivering the most cost-effective solution for high-end capabilities, includingtransceiver and memory interface line rates as well as 100G connectivity cores. Our newestmid-range family is ideal for both packet processing and DSP-intensive functions and is wellsuited for applications including wireless MIMO technology, Nx100G networking, and datacenter.Kintex UltraScale devices provide the best price/performance/watt at 20 nm and includethe highest signal processing bandwidth in a mid-range device, next-generationtransceivers, and low-cost packaging for an optimum blend of capability andcost-effectiveness. The family is ideal for packet processing in 100G networking and datacenters applications as well as DSP-intensive processing needed in next-generation medicalimaging, 8k4k video, and heterogeneous wireless infrastructure.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback6

Chapter 1: Block RAM ResourcesZynq UltraScale MPSoC devices provide 64-bit processor scalability while combiningreal-time control with soft and hard engines for graphics, video, waveform, and packetprocessing. Integrating an Arm -based system for advanced analytics and on-chipprogrammable logic for task acceleration creates unlimited possibilities for applicationsincluding 5G Wireless, next generation ADAS, and Industrial Internet-of-Things.This user guide describes the UltraScale architecture memory resources and is part of theUltraScale architecture documentation suite available at: www.xilinx.com/documentation.Block RAM SummaryThe block RAM in UltraScale architecture-based devices stores up to 36 Kbits of data andcan be configured as either two independent 18 Kb RAMs, or one 36 Kb RAM. Eachblock RAM has two write and two read ports. A 36 Kb block RAM can be configured withindependent port widths for each of those ports as 32K x 1, 16K x 2, 8K x 4, 4K x 9, 2K x 18or 1K x 36 (when used as true dual-port (TDP) memory). If only one write and one read portare used, a 36 Kb block RAM can additionally be configured with a port width of 512 x 72bits (when used as simple dual-port (SDP) memory). An 18 Kb block RAM can be configuredwith independent port widths for each of those ports as 16K x 1, 8K x 2, 4K x 4, 2K x 9 or1K x 18 (when used as TDP memory). If only one write and one read port are used, an 18 Kbblock RAM can additionally be configured with a port width of 512 x 36 bits (when used asSDP memory).Similar to the 7 series FPGA block RAMs, write and read are synchronous operations. Thetwo ports are symmetrical and totally independent, sharing only the stored data. Each portcan be configured in one of the available widths, independent of the other port. In addition,the read port width can be different from the write port width for each port. The memorycontent can be initialized or cleared by the configuration bitstream. During a writeoperation, the memory can be set to have the data output remain unchanged, reflect thenew data being written or the previous data now being overwritten.The block RAM features include: Per-block memory storage capability where each block RAM can store up to 36 Kbits ofdata. Support of two independent 18 Kb blocks, or a single 36 Kb block RAM. Each 36 Kb block RAM can be used with a single read and write port (SDP), doublingdata width of the block RAM to 72 bits. The 18 Kb block RAM can also be used with asingle read and write port, doubling data width to 36 bits. When used as RAMB36 SDP memory, one port width is fixed (i.e., 512 x 64 or 512 x 72).The other port width can then be 32K x 1 through 512 x 72. When used as RAMB18 SDPmemory, one port width is fixed (i.e., 512 x 36). The other port width can then be16K x 1 through 512 x 36.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback7

Chapter 1: Block RAM Resources The data outputs of the lower to upper adjacent block RAMs can be cascaded to buildlarge block RAM blocks. Optional pipeline registers are available to support maximumperformance. One 64-bit error correction coding (ECC) block is provided per 36 Kb block RAM or36 Kb FIFO. Independent encode/decode functionality is available. ECC mode has thecapability of injecting errors. Synchronous set/reset of the outputs to an initial value is available for both the latchand register modes of the block RAM output. Separate synchronous set/reset pins independently control the set/reset of theoptional output registers and output latch stages in the block RAM. An attribute to configure the block RAM as a common-clock/single-clock FIFO toeliminate flag latency uncertainty. 18, 36, or 72-bit wide block RAM ports can have an individual write enable per byte.This feature is popular for interfacing to a microprocessor. Each block RAM contains optional address sequencing and control circuitry to operateas a built-in independent-clock FIFO memory. The block RAM can be configured as an18 Kb or 36 Kb FIFO. All inputs are registered with the port clock and have a setup-to-clock timingspecification. All outputs have a read function or a read-during-write function, depending on thestate of the write enable (WE) pin. The outputs are available after the clock-to-outtiming interval. The read-during-write outputs have one of three operating modes:WRITE FIRST, READ FIRST, and NO CHANGE. A write operation requires one clock edge. A read operation requires one clock edge. All output ports are latched or registered (optional). The state of the output port doesnot change until the port executes another read or write operation. The defaultblock RAM output is register mode.RECOMMENDED: The output datapath has an optional internal pipeline register. Using the registermode is strongly recommended. This allows a higher clock rate. However, it adds a clock cycle latencyof one.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback8

Chapter 1: Block RAM ResourcesThe block RAM usage rules include: The block RAM synchronous output registers (optional) are set or reset (SRVAL) withRSTREG when DO REG 1. The RSTREG PRIORITY attribute determines if RSTREG haspriority over REGCE. The synchronous output latches are set or reset (SRVAL) withRSTRAM when DO REG is 0 or 1.IMPORTANT: The clock minimum pulse width and setup/hold time of the block RAM address, and writeenable pins must not be violated. Violating the clock minimum pulse width or these setup/hold times(even if write enable is Low) can corrupt the data contents of the block RAM. This most commonlyoccurs during an unstable clock or when flip-flops driving block RAM control pins are asynchronouslyreset, such as a system wide reset. To avoid this issue, ensure stable clocks and design with synchronousresets for both assertion and deassertion. When the clock is not stable, disable the clock buffer ordisable logic driving the block RAM control pins or deassert the block RAM EN input. The block RAM register mode RSTREG requires REGCE 1 to reset the output DOregister value if the RSTREG PRIORITY is set to REGCE. The block RAM array dataoutput latch does not get reset in this mode. The block RAM latch mode RSTRAMrequires the block RAM enable, EN 1, to reset the output DO latch value. There are two block RAM primitives: RAMB36E2 and RAMB18E2. Different read and write port width choices are available when using specificblock RAM primitives. The parity bits are only available for the x9, x18, and x36 portwidths. The parity bits should not be used when the read width is x1, x2, or x4. If theread width is x1, x2, or x4, the effective write width is x1, x2, x4, x8, x16, or x32. Similarly,when a write width is x1, x2, or x4, the actual available read width is x1, x2, x4, x8, x16,or x32 even though the primitive attribute is set to 1, 2, 4, 9, 18, or 36, respectively.Table 1-1 shows some possible scenarios.Table 1‐1:PrimitiveParity Use ScenariosSettingsEffective Read WidthEffective Write Width9 or 18Same as setting8 or 169 or 181, 2, or 48 or 16Same as settingRAMB18E21, 2, or 41, 2, or 4Same as settingSame as settingRAMB18E29 or 189 or 18Same as settingSame as settingRAMB36E21, 2, or 49, 18, or 36Same as setting8, 16, or 32RAMB36E29, 18, or 361, 2, or 48, 16, or 32Same as settingRAMB36E21, 2, or 41, 2, or 4Same as settingSame as settingRAMB36E29, 18, or 369, 18, or 36Same as settingSame as settingRead WidthWrite WidthRAMB18E21, 2, or 4RAMB18E2Notes:1. Do not use parity bits DINP/DOUTP when one port width is less than 9 and another port width is 9 or greater.UltraScale Architecture Memory ResourcesUG573 (v1.12) March 17, 2021www.xilinx.comSend Feedback9

Chapter 1: Block RAM ResourcesDifferences from Previous GenerationsChanges from 7 Series FPGAs When used as SDP memory, all write modes are supported (READ FIRST, WRITE FIRST,NO CHANGE). UltraScale architecture-based devices have a new data cascading scheme. Largeblock RAMs can now be built in a bottom-up fashion directly in the block RAM columnwithout additional use of logic resources. An address enable feature has been added to the block RAM. If disabled, the newaddress is not latched in the block. A dynamic power gating capability has been added. The block RAM can be put intosleep mode while preserving the data content. The RAM MODE attribute has been removed. The Vivado tools automaticallydetermine if a block RAM is used in TDP or SDP mode. The built-in FIFOs and IP FIFOs have been harmonized as much as possible. This makesit easier to switch between soft and hard FIFO implementations. FIFOs allow cascading of multiple FIFO36s and FIFO18s for building deeper FIFOs inhardware. A synchronous FIFO reset replacing the asynchronous reset in previous generations hasbeen added. FIFO latencies of the deassertion of the EMPTY/PROGEMPTY flag for a write operationand the FULL/PROGFULL flag for a read operation have changed. The behavior of WRERR and RDERR during reset has changed. FIFO asymmetric ports are now supported. The write port and read port can each beconfigured independently as x4, x9, x18, x36, or x72 for

UltraScale Architecture Memory Resources 7 UG573 (v1.12) March 17, 2021 www.xilinx.com Chapter 1: Block RAM Resources Zynq UltraScale MPSoC devices provide 64-bit processor scalability while combining real-

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