OS And Libraries Document Collection(UG643)

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Xilinx Standalone LibraryDocumentationOS and Libraries Document CollectionUG643 (v2020.2) November 24, 2020

Table of ContentsChapter 1: Xilinx OS and Libraries Overview. 5Chapter 2: Xilinx Standard C Libraries.7Arithmetic Operations. 8Input/Output Functions. 9Chapter 3: Standalone Library v7.3. 12Xilinx Hardware Abstraction Layer API. 12Microblaze Processor API.40ARM Processor Common API.73Cortex R5 Processor API. 79Cortex A9 Processor API. 102Cortex A53 32-bit Processor API. 132Cortex A53 64-bit Processor API. 144Chapter 4: LwIP 2.1.1 Library.155Introduction. 155Using lwIP.156LwIP Library APIs.166Chapter 5: XilIsf Library v5.15. 173Overview.173XilIsf Library API. 174Library Parameters in MSS File.190Chapter 6: XilFFS Library v4.4.192XilFFS Library API Reference. 192Library Parameters in MSS File.194Chapter 7: XilSecure Library v4.3. 197Overview.197AES-GCM.198UG643 (v2020.2) November 24, 2020OS and Libraries Document CollectionSend Feedbackwww.xilinx.com2

AES-GCM Error Codes. 206AES-GCM API Example Usage. 207AES-GCM Usage to decrypt Boot Image. 208RSA. 209RSA API Example Usage. 214SHA-3. 215SHA-3 API Example Usage.222Chapter 8: XilSkey Library v7.0.224Overview.224BBRAM PL API. 229Zynq UltraScale MPSoC BBRAM PS API. 231Zynq eFUSE PS API. 233Zynq UltraScale MPSoC eFUSE PS API. 235eFUSE PL API. 252CRC Calculation API.258User-Configurable Parameters.259Data Structure Index.308Chapter 9: XilPM Library v3.2. 313XilPM Zynq UltraScale MPSoC APIs. 313XilPM Versal ACAP APIs.372Chapter 10: XilFPGA Library v5.3. 513Overview.513Supported Features. 513Zynq UltraScale MPSoC XilFPGA Library.514Versal ACAP XilFPGA Library. 531Chapter 11: XilMailbox v1.2. 538XilMailbox Library API Reference. 538Data Structure Index.546Chapter 12: XilSEM. 548XilSEM Library API Reference.548Appendix A: Additional Resources and Legal Notices. 551Xilinx Resources.551Documentation Navigator and Design Hubs. 551UG643 (v2020.2) November 24, 2020OS and Libraries Document CollectionSend Feedbackwww.xilinx.com3

Please Read: Important Legal Notices. 552UG643 (v2020.2) November 24, 2020OS and Libraries Document CollectionSend Feedbackwww.xilinx.com4

Chapter 1: Xilinx OS and Libraries OverviewChapter 1Xilinx OS and Libraries OverviewThe Vitis Unified Software Development Environment provides a variety of Xilinx softwarepackages, including drivers, libraries, board support packages, and complete operating systems tohelp you develop a software platform. This document collection provides information on these.Complete documentation for other operating systems can be found in the their respectivereference guides. Device drivers are documented along with the corresponding peripheraldocumentation. The documentation is listed in the following table; click the name to open thedocument.Library NameSummaryChapter 2: XilinxStandard C LibrariesDescribes the software libraries available for the embedded processors.Chapter 3: StandaloneLibrary v7.3Describes the Standalone platform, a single-threaded, simple operating system (OS) platformthat provides the lowest layer of software modules used to access processor-specific functions.Some typical functions offered by the Standalone platform include setting up the interrupts andexceptions systems, configuring caches, and other hardware specific functions.The Hardware Abstraction Layer (HAL) is described in this document.Chapter 4: LwIP 2.1.1LibraryDescribes the SDK port of the third party networking library, Light Weight IP (lwIP) for embeddedprocessors.Chapter 5: XilIsfLibrary v5.15Describes the In System Flash hardware library, which enables higher-layer software (such as anapplication) to communicate with the Isf. XilIsf supports the Xilinx In-System Flash and externalSerial Flash memories from Atmel (AT45XXXD), Spansion(S25FLXX), Winbond W25QXX, and MicronN25QXX.Chapter 6: XilFFSLibrary v4.4Xilffs is a generic FAT file system that is primarily added for use with SD/eMMC driver. The filesystem is open source and a glue layer is implemented to link it to the SD/eMMC driver.Chapter 7: XilSecureLibrary v4.3The XilSecure library provides APIs to access secure hardware on the Zynq UltraScale MPSoCdevices.Chapter 8: XilSkeyLibrary v7.0The XilSKey library provides a programming mechanism for user-defined eFUSE bits and forprogramming the KEY into battery-backed RAM (BBRAM) of Zynq SoC, provides programmingmechanisms for eFUSE bits of UltraScale devices.The library also provides programming mechanisms for eFUSE bits and BBRAM key of the ZynqUltraScale MPSoC devices.Chapter 9: XilPMLibrary v3.2The Zynq UltraScale MPSoC and Versal ACAP power management framework is a set of powermanagement options, based upon an implementation of the extensible energy managementinterface (EEMI).The power management framework allows software components running across differentprocessing units (PUs) on a chip or device to issue or respond to requests for powermanagement.Chapter 10: XilFPGALibrary v5.3The XilFPGA library provides an interface to the Linux or bare-metal users for configuring theprogrammable logic (PL) over PCAP from PS. The library is designed for Zynq UltraScale MPSoCand Versal ACAP to run on top of Xilinx standalone BSPs.Chapter 11: XilMailboxv1.2The XilMailbox library provides the top-level hooks for sending or receiving an inter-processorinterrupt (IPI) message using the Zynq UltraScale MPSoC and Versal ACAP IPI hardware.UG643 (v2020.2) November 24, 2020OS and Libraries Document CollectionSend Feedbackwww.xilinx.com5

Chapter 1: Xilinx OS and Libraries OverviewLibrary NameChapter 12: XilSEMSummaryThe Xilinx Soft Error Mitigation (XilSEM) library is a pre-configured, pre-verified solution to detectand optionally correct soft errors in Configuration Memory of Versal ACAPs.About the LibrariesThe Standard C support library consists of the newlib, libc, which contains the standard Cfunctions such as stdio, stdlib, and string routines. The math library is an enhancementover the newlib math library, libm, and provides the standard math routines. The LibXillibraries consist of the following: LibXil Driver (Xilinx device drivers) XilMFS (Xilinx memory file system) XilFlash (a parallel flash programming library) XilIsf (a serial flash programming library)The Hardware Abstraction Layer (HAL) provides common functions related to register I/O,exception, and cache. These common functions are uniform across MicroBlaze and Cortex A9processors. The Standalone platform document provides some processor specific functions andmacros for accessing the processor-specific features. Most routines in the library are written in Cand can be ported to any platform. User applications must include appropriate headers and linkwith required libraries for proper compilation and inclusion of required functionality. Theselibraries and their corresponding include files are created in the processor \lib and \includedirectories, under the current project, respectively. The -I and -L options of the compiler beingused should be leveraged to add these directories to the search paths.Library OrganizationYour application can interface with the components in a variety of ways. The libraries areindependent of each other, with the exception of some interactions. The LibXil drivers and theStandalone form the lowermost hardware abstraction layer. The library and OS components relyon standard C library components. The math library, libm.a is also available for linking with theuser applications.Note: “LibXil Drivers” are the device drivers included in the software platform to provide an interface to theperipherals in the system. These drivers are provided along with the Vitis Unified Software DevelopmentEnvironment and are configured by Libgen. This document collection contains a section that brieflydiscusses the concept of device drivers and the way they integrate with the board support package in Vitis.Taking into account some restrictions and implications, which are described in the referenceguides for each component, you can mix and match the component libraries.UG643 (v2020.2) November 24, 2020OS and Libraries Document Colle

The XilMailbox library provides the top-level hooks for sending or receiving an inter-processor interrupt (IPI) message using the Zynq UltraScale MPSoC and Versal ACAP IPI hardware. Chapter 1: Xilinx OS and Libraries Overview

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