Emulation And Trace Headers - TI
Emulation and Trace HeadersTechnical Reference ManualLiterature Number: SPRU655IFebruary 2003 – Revised August 2012
ContentsPreface . 51Introduction . 72Adapters . 93Fundamental Information . 94Alternate Target Impedance Configurations . 95Header Information . 106Header Footprint Comparisons . 107Target Mating Caution . 128Header Pin Assignment . 129Electrical Requirements . 2110Single-Processor Termination . 2311Buffering . 2412General Specifications . 2413Acceptable Signal Qualifications . 2514Connecting Alternate Headers . 26.15Layout and Routing Requirements .15.1 Maximum Recommended Distances .16Advanced Emulation - Layout and Route Distance Deviations .16.1 Signal-to-Signal Clearance .16.2 PWB Routing Lengths .17Traditional JTAG Emulation Layout and Route Distance Deviations .17.1 Layout and Routing - Mechanical Considerations .18Multi-Function Trace Pins .19Multiple Device Considerations .19.1 Multiple-Processor Termination .Appendix A Alternate Target Impedance Configurations .Appendix B Buffering - Methods, Techniques and Terminations .Appendix C TI 14-Pin and 60-Pin Headers in Parallel .Appendix D Layout and Routing Requirements .D.1Layout and Route Deviations [Advanced Emulation] .Appendix E XDS560T Spice Model .Appendix F XDS560 v2 System Trace Modeling .Appendix G XDS Pro Trace Modeling .Appendix H Finding a Buffer's Output Impedance .Appendix I Variable Board Impedance .Revision History .14.12TI 14-Pin and 60-Pin Headers in ParallelTable of 64SPRU655I – February 2003 – Revised August 2012Submit Documentation FeedbackCopyright 2003–2012, Texas Instruments Incorporated
www.ti.comList of Figures.1TI 60-Pin Emulation Header2MIPI 60-Pin Header . 113TI 20-Pin CTI Header . 114TI 14-Pin Traditional Through-Hole Emulation Interface . 115TI 14-Pin Traditional SMT Emulation Interface Header . 11660-Pin Header Orientation7Emulator Cable Connector Superimposed Over 60-Pin Header . 198MIPI 60-Pin Header Pin Location209TI 20-Pin CTI Header Pin 303132333435363738394041424344454647.Target Connection for Unbuffered JTAG and EMU Signals .Acceptable Wave Form Criteria .Multi-Header EMU0, EMU1, TDO Termination .Symmetrical Nets .TI 60-Pin Connector Maximum Trace Length .MIPI 60-Pin Connector Maximum Trace Length .XDS560T TI 60-Pin Target Cable Connector Minimum Clearance - Height.XDS560 v2 System Trace MIPI 60-Pin Target Cable Connector Minimum Clearance - Height .XDS560T TI 60-Pin Target Cable Header Dimensions .XDS560 v2 System Trace MIPI 60-Pin Target Cable Header Dimensions .XDS560T TI 60-Pin Target Cable Board Keep-Out Area .XDS560 v2 System Trace MIPI 60-Pin Target Cable Board Keep-Out Area .Multi-Function Trace .Multiple Device - Single Trace Configuration .Multiple Device - Parallel Trace Configuration.Device-Independent Trace Configuration .Parallel Termination .Recommended TCK Buffered Configuration .Recommended TCK Unbuffered Configuration .Recommended RTCK Configuration .Recommended EMU Output Configuration .TCK, Multiple Header Configuration .Preferred Configuration for EMU0 and EMU1 Terminations.EMU0 Simulation Model (TI's XDS560T Pod Assembly - 50-Ω and 75-Ω Target and Pod Model) .EMU0 Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) .EMU0 Wave Form (Host Side, TI's XDS560T - 75 Ω).EMU2 Type Signals Simulation Model (TI's XDS560T Pod Assembly - 50-Ω Target and Pod Model) .EMU2 Type Signals Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) .EMU18 Type Signals Simulation Model (TI's XDS560T Pod Assembly - 50-Ω Target and Pod Model) .EMU18 Type Signals - Acceptable Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) .EMU0 Dual-Header Simulation Model (TI's XDS560T Pod Assembly - 50-Ω Target and Pod Model) .EMU0 Dual-Header - Wave Form (Host Side, TI's XDS560T Pod - 50 Ω) .TRCLK[0] Model Schematic.TRC CLK0 Model Schematic .TRC CLK1 Model Schematic .TRC DATA[n] Signal Schematic .Various PCB Impedance Calculations .Example of 10-Layer PCB Construction .SPRU655I – February 2003 – Revised August 2012Submit Documentation FeedbackCopyright 2003–2012, Texas Instruments IncorporatedList of 83940414446484951525455575859596063633
www.ti.comList of Tables1TXDS Trace Support Platforms . 72Emulation Header Use . 83Adapters . 94Summary: Alternate Target Impedance Configurations . 95Summary: TI 60-Pin Header Information . 106Summary: MIPI 60-Pin Header Information . 107Summary: TI 20-Pin CTI Header Information . 108Summary: Header Footprint Comparisons . 129Summary: Header Changes1210TI 60-Pin Header Signal Naming 304.Summary: TI 60-Pin Header Pinout .MIPI 60-Pin Header Signal Naming Convention .TI 20-Pin CTI Header Signal Naming Convention .Summary: Header Pin Assignments .JTAG Signal Directions .Summary: Electrical Requirements .Termination Values and Use Cases .Summary: Single-Processor Terminations .Summary: Buffering .General Specifications .Summary: Acceptable Signals .Summary: TI 14-Pin and 60-Pin Headers in Parallel .Summary: Advanced Emulation Layout and Routing .Summary: Layout and Routing - Mechanical Considerations (TI 60-Pin) .Summary: Layout and Routing - Mechanical Considerations (MIPI 60-Pin) .Sizing Common Termination Resistor Values .EMU Pins Modeled as EMU2 or EMU18 .Buffer Name Decode and Output Impedance .Recommended Series Termination Resistor Value .Model name Example .List of 655I – February 2003 – Revised August 2012Submit Documentation FeedbackCopyright 2003–2012, Texas Instruments Incorporated
PrefaceSPRU655I – February 2003 – Revised August 2012Read This FirstAbout This ManualThis technical reference describes how to incorporate Texas Instruments' next-generation emulationheader on a board with a trace-enabled DSP.Notational ConventionsThis document uses the following conventions. Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h. Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion. Measurements are in English standard units (inches, pounds, etc.).Related DocumentationThe following documents describe the TMS320C6000 DSP platform and related support tools. Copies ofthese documents are available on the Internet at www.ti.com. Tip: Enter the literature number in thesearch box provided at www.ti.com.SPRA439 — Emulation Fundamentals for TI's DSP Solutions. This paper explains the fundamentals ofhow the emulation logic and emulation tools work together with the TI digital signal processors. Byunderstanding the fundamentals of emulation, you will be able to accelerate the process of settingup and performing software debug, as well as aid in troubleshooting potential problems in thedebugging setup. A detailed explanation of the setup of the emulator hardware systems for singleand multi-processor applications, along with a discussion of how the system components interactduring debug will be discussed in the sections to follow. Also included is a troubleshooting guide toassist in common setup problems.SPRU641 — TMS320C6000 DSP Designing for JTAG Emulation Reference Guide. This documentassists you in meeting the design requirements of the XDS510 emulator with respect to JTAGdesigns and discusses the XDS510 cable. This cable supports both standard 3-volt and 5-volttarget system power inputs.SPRU589 — XDS560 Emulator Reference Guide. This technical reference describes the fundamentalsof the XDS560 PCI Emulator and Pod and how to interface it to a target system.SPDU079 — JTAG/MPSD Emulation Technical Reference. A reference guide that provides detailedinformation to be used when designing for JTAG emulation.SPRAAK6 — Common Trace Transmission Problems and Solutions. This document providesguidelines for identifying and solving common problems associated with the collecting of high speeddata. On a trace-capable device, the trace interface is one of the highest performance interfaces.Although only used during design, development, and debug, the trace interface must beimplemented correctly for full functionality and performance.SPRU655I – February 2003 – Revised August 2012Submit Documentation FeedbackCopyright 2003–2012, Texas Instruments IncorporatedPreface5
Related Documentationwww.ti.comIEEE Std 1149.1-1990 — IEEE Std 1149.1-1990 IEEE Standard Test Access Port and Boundary-ScanArchitecture -Description. Circuitry that may be built into an integrated circuit to assist in the test,maintenance, and support of assembled printed circuit boards is defined. The circuitry includes astandard interface through which instructions and test data are communicated. A set of testfeatures is defined, including a boundary-scan register, such that the component is able to respondto a minimum set of instructions designed to assist with testing of assembled printed circuit boards.TMS320C6000, XDS510, XDS560 are trademarks of Texas Instruments.ARM is a registered trademark of ARM Ltd or its subsidiaries.6Read This FirstSPRU655I – February 2003 – Revised August 2012Submit Documentation FeedbackCopyright 2003–2012, Texas Instruments Incorporated
Technical Reference ManualSPRU655I – February 2003 – Revised August 2012Emulation and Trace Headers1IntroductionThis technical reference describes the requirements necessary to incorporate an emulation header on aboard that includes devices that support trace export through the device's EMU pins to an emulator withtrace capture support. Texas Instruments device's support various combinations of DSP and ARM coretrace and system trace. Table 1 shows the TI XDS platforms that support trace capture. In all cases, thetrace data rates require that the EMU pins be treated as high-speed clocks within your design. Thisspecifically means that the EMU pins must be terminated properly and the correct header chosen for thenumber of EMU pins required. In the case of core trace or if core trace and system trace export are bothsupported, this requires utilizing a 60-pin header in place of the traditional TI 14-pin or TI 20-pin CTIemulation header. In the case where a device only supports export of system trace data, a TI 20-pin CTIheader may be used.Table 1. TXDS Trace Support PlatformsXDSDSP Core TraceARM Core TraceSystem TraceXDS560v2 System TraceNoNoYesXDS Pro TraceYesYesYesXDS560T (1)YesNoNo(1)Note that the XDS560T has been discontinued, and the TI-60 pin header required by the XDS560T isno longer recommended for new designs.Core trace typically provides at least processor PC trace, and depending on the silicon implementationmay also provide processor data trace and event trace. System trace is a message-based technologythat, in enabled silicon, can export application instrumentation and hardware generated messages fromsystem-level monitors. Many device
target system power inputs. SPRU589 — XDS560 Emulator Reference Guide. This technical reference describes the fundamentals of the XDS560 PCI Emulator and Pod and how to interface it to a target
PCL 6 (XL3.0) emulation, PCL 5c emulation, Epson FX Emulation, PostScript 3 emulation, PDF 2.0 emulation, IBM Tray 1: 250 sheets of 80gsm,MP tray: 100 sheets of 80gsm Hi Speed USB 2.0, 10/100/1000Base-Tx Standard 19,900 OKI C834NW (OKI-OKI-47074215) 36 ppm Color, 20 ppm Mono 1200
STM is a trace element which allows for several types of trace messages to be added to a trace stream. This trace stream may or may not also contain instruction flow trace streams. Adding STM messaging has several effects. STM trace messages can be a way of tracing the high-level state of the SoC-based system.
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3.2. tips from our trace experience 28 3.3. evaluating your trace campaigns and use of tools 31 Using TAToo to analyse your data 35 Stories from the TRACE pilot sites 39 5.1. Traffic Snake Game 40 5.2. positive drive 44 5.3. biklio 50 TRACE recommendations 53 6.1. General recommendations 54 6.2.
APB200 - Advanced Debugging using the Ashling MPC5500 Tools Page 4 of 16 2. The e200 Code tab can be left at default settings i.e.: Figure 5. e200 Code Dialog 3. The e200 Data tab should be set as shown below. Set Start Emitting Data Trace to On Program Execution and Stop Emitting Data Trace to On Program Halt. Set Data Trace Region 0 Trace Type to Write Trace and the Start Address and End .
For each open trace, the session man- formation. ager saves the name of the file containing 1 Trace fik. Traceview processes event 67 trace file input session configuration saving and restoring Session manager Trace manager ]*[Disploy Luger 1 U Figure 2. Tmcevim a &temwe. traces. An event is a recorded instance of
2.5 Installing Oracle Trace File Analyzer on Microsoft Windows in Non-Daemon Mode 2-4 2.6 Oracle Trace File Analyzer Key Directories 2-4 2.7 Oracle Trace File Analyzer Command Interfaces 2-5 2.8 Masking Sensitive Data 2-5 2.9 Securing Access to Oracle Trace File Analyzer 2-6 2.10 Uninstalling Oracle Trace File Analyzer 2-7iii
