Quad H-Bridge Micro Step Motor Driver With I C Interface
Quad H-Bridge Micro StepMotor Driver with I2C InterfaceBi-CMOS LSILV8414CSOverviewThe LV8414CS is a motor driver that is available for the PWMconstant current control micro step drive of dual stepper motor.Miniaturization using the wafer level package (WLCSP) makes the ICideally suited for driving the stepping motors used to control the lensesin digital still cameras, cell phone camera modules and other suchdevices.www.onsemi.comFeatureWLCSP32, 2.47x2.47CASE 567GT Built in 256 division Micro Step Drive Circuit for Dual Stepper MotorExcitation Step Proceeds Only by Step Signal InputPeak Excitation Current Switchable to One of 16 LevelsSerial Data Control using I2C InterfaceBuilt in Thermal Protection CircuitLow Supply Voltage Protection Circuit IncorporatedOn chip Photo Sensor Drive TransistorsOn chip Schmitt BufferMARKING DIAGRAMA1LV8414YMAZZ(Top View)Typical Applications LV8414YMAZZTabletDigital Still CameraFeature PhoneSmartphone Specific Device Code Production Date Code Assembly Lot CodeORDERING INFORMATIONSee detailed ordering and shipping information on page 39 ofthis data sheet. Semiconductor Components Industries, LLC, 2015May, 2020 Rev. 41Publication Order Number:LV8414CS/D
LV8414CSSPECIFICATIONSABSOLUTE MAXIMUM RATINGS at TA 25 CParameterSymbolMaximum supply voltage 1ConditionsRatingsUnitVM max6.0VMaximum supply voltage 2VCC max6.0VOutput peak currentIOpeakch1 to 4t 10ms, ON duty 20%600mAContinuous output current 1IO max1ch1 to 4400mAContinuous output current 2IO max2PI30mAAllowable power dissipationPd max*Mounted on a specified board1.0WOperating temperatureTopr 30 to 85 CStorage temperatureTstg 55 to 150 CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.*Specified circuit board: 40 mm 50 mm 0.8 mm, glass epoxy four layer board.RECOMMENDED OPERATING CONDITIONS at TA 25 CParameterSymbolConditionsRatingsUnitOperating supply voltage range1VM op2.5 to 5.5VOperating supply voltage range2VCC op2.5 to 5.5VLogic input voltageVIN0 to VCC 0.3VCLK input frequencyFIN0 to 100kHzCLK1 to 2Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.ELECTRICAL CHARACTERISTICS at TA 25 C, VM 5.0 V, VCC 3.3 VRatingsParameterStandby mode current drainSymbolIstnConditionsMinTypENA “L”VM current drainIMENA “H”, IM1 IM2, with no loadVCC current drainICCENA “H”MaxUnit1.0mA50100200mA0.751.53.0mAVCC low voltage cutoff voltageVthVCC2.02.252.5VLow voltage hysteresis voltageVthHYS100150200mVThermal shutdown temperatureTSDDesign guarantee value *160180200 CDTSDDesign guarantee value *103050 CLogic pin internal pull down resistanceRinENA, CLK1 to 2, FR1 to 250100200kWLogic pin input currentIinLVIN 0, ENA, CLK1 to 2, FR1 to 21.0mAIinHVIN 3.3 V, ENA, CLK1 to 2, FR1 to 216.566mALogic high level voltageVinHENA, SCL, SDA, CLK1 to 2, FR1 to 20.6 VCCLogic low level voltageVinLENA, SCL, SDA, CLK1 to 2, FR1 to 2Thermal hysteresis widthMICRO STEP DRIVERwww.onsemi.com233V0.2 VCCV
LV8414CSELECTRICAL CHARACTERISTICS (continued) at TA 25 C, VM 5.0 V, VCC 3.3 O STEP DRIVEROutput on-resistanceRonuIO 100 mA, upper ON resistance0.38WRondIO 100 mA, lower ON resistance0.22WRonIO 100 mA, sum of upper andlower side on resistance0.6Output leakage currentIOleakDiode forward voltageVDChopping frequencyCurrent setting reference voltagesID 100 V1.52.5W1.0mAPI (Photo sensor driving transistor)Output on resistanceOutput leakage currentRonIO 10 mAIOleakSCHMITT BUFFERLogic input high level voltageVinHBI1, BI2Logic input low level voltageVinLBI1, BI20.5 VCCV0.25 VCCVProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.*Design target value, not to be measured at production test.www.onsemi.com3
LV8414CSPIN ASSIGNMENTFigure 1. Pin AssignmentFigure 2.www.onsemi.com4
LV8414CSBLOCK DIAGRAMFigure 3.www.onsemi.com5
LV8414CSPIN FUNCTIONSPIN FUNCTIONSPin No.Pin NameFunctionA1A6BI1BI2Schmitt buffer input pinB3SCLI2C InterfaceB4SDAI2C InterfaceE2ENAChip enable pinC2C5CLK1CLK2Step signal input UT2AOUT4AOUT2BOUT4BB1B6E1E6RF1RF3RF2RF4Equivalent CircuitForward/reverse rotation setting signal input pinH bridge output pinCurrent sense resistor connection pinswww.onsemi.com6
LV8414CSPIN FUNCTIONS (continued)Pin No.Pin NameFunctionE5MOMonitor output pinF1F6BO1BO2Schmitt buffer output uivalent CircuitPhoto sensor drive transistor output pinLogic power supply connection pinSignal groundMotor power supply connection pinPower groundUnused pinwww.onsemi.com7
LV8414CSSerial Bus Communication SpecificationsI 2C Serial Transfer Timing ConditionsFigure 4.STANDARD MODEParameterSymbolConditionsMinMaxUnit100kHzSCL clock frequencyfsclSCL clock frequencyData setup timets1Setup time of SCL with respect to the falling edge of SDA4.7msts2Setup time of SDA with respect to the rising edge of SCL250nsts3Setup time of SCL with respect to the rising edge of SDA4.0msth1Hold time of SCL with respect to the rising edge of SDA4.0msth2Hold time of SDA with respect to the falling edge of SCL0.08mstwLSCL low period pulse width4.7mstwHSCL high period pulse width4.0tonSCL, SDA (input) rising time1000mstofSCL, SDA (input) falling time300mstbufInterval between stop condition and start conditionSCL clock frequencyfsclSCL clock frequencyData setup timets1Setup time of SCL with respect to the falling edge of SDA0.6msts2Setup time of SDA with respect to the rising edge of SCL100nsData hold timePulse widthInput waveform conditionsBus free time0Typms4.7msHIGH SPEED MODE0400kHzts3Setup time of SCL with respect to the rising edge of SDA0.6msth1Hold time of SCL with respect to the rising edge of SDA0.6msth2Hold time of SDA with respect to the falling edge of SCL0.08mstwLSCL low period pulse width1.3mstwHSCL high period pulse width0.6msInput waveform conditionstonSCL, SDA (input) rising timetofSCL, SDA (input) falling timeBus free timetbufInterval between stop condition and start conditionData hold timePulse widthwww.onsemi.com81.3300ms300msms
LV8414CSI2C Bus Transmission MethodStart and Stop ConditionsThe I2C bus requires that the state of SDA be preservedwhile SCL is high as shown in the timing diagram belowduring a data transfer operation.SCLSDAts2th2Figure 5.When data is not being transferred, both SCL and SDA arein the high state. The start condition is generated and accessis started when SDA is changed from high to low while SCLand SDA are high.Conversely, the stop condition is generated and access isended when SDA is changed from low to high while SCL ishigh.Start ConditionStop Conditionth1ts3SCLSDAFigure 6.www.onsemi.com9
LV8414CSData Transfer and Acknowledgement ResponseThere are no CE signals in the I2C bus; instead, a 7 bitslave address is assigned to each device, and the first byte ofthe transfer data is allocated to the 7 bit slave address andto the command (R/W) which specifies the direction ofsubsequent data transfer.The LV8414CS is a drive IC with a dedicated writefunction and it does not have a read function.The 7 bit address is transferred in sequence starting withMSB, and the eighth bit is set to low. The second andsubsequent bytes are transferred in write mode.In the LV8414CS, the slave address is stipulated to be“1110010.”.After the start condition is generated, data is transferredone byte (8 bits) at a time. Any number of data bytes can betransferred consecutively.An ACK signal is sent to the sending side from thereceiving side every time 8 bits of data are transferred. Thetransmission of an ACK signal is performed by setting thereceiving side SDA to low after SDA at the sending side isreleased immediately after the clock pulse of SCL bit 8 in thedata transferred has fallen low.After the receiving side has sent the ACK signal, if thenext byte transfer operation is to receive only the byte, thereceiving side releases SDA on the falling edge of the 9thclock of SCL.Figure 7.Data Transfer Write FormatThus, continuous data transfer starting at the designatedaddress is made possible.When the register address is set to “00000011,” theaddress to which the next byte is transferred wraps aroundto “00000000.”The slave address and Write command must be allocatedto the first byte (8 bits) and the register address in the “Serialdata truth table” must be designated in the second byte.For the third byte, data transfer is carried out to the addressdesignated by the register address which is written in thesecond byte. Subsequently, if data continues, the registeraddress value is automatically incremented for the fourthand subsequent bytes.1. Data Write ExampleFigure 8.www.onsemi.com10
LV8414CS2. Actual Example of Continuous Data Transfer3/4 channelOutput onReset releaseForward rotationCurrent referencevoltage 0.2V 2 channel CLK1 frequencydivision Half step setting3/4-channel CLK2 frequencydivision Half step setting 400kHz chopping photo sensor OFF MO outputchannels set to 1/2channels MO output Initialposition1/2 channelOutput onReset releaseReverse rotationCurrent referencevoltage 0.2V Figure 9.Based on the “Serial data truth table” on the next page, thefollowing settings are used for the actual example of thecontinuous data transfer shown in the above figure.(Data transfer is set at the SCL rising edge of “D0” of eachdata.)3/4 channel Settings:Output ON, reset release, forward (CW) rotation, currentreference voltage setting of 0.2 V, no CLK2 frequencydivision, Half step setting.Other Settings:400 kHz chopping frequency, photo sensor OFF, MOoutput channels set to 1/2 channels, MO output initialposition.1/2 channel Settings:Output ON, reset release, reverse (CCW) rotation, currentreference voltage setting of 0.2 V, no CLK1 frequencydivision, Half step setting.www.onsemi.com11
LV8414CSSERIAL DATA TRUTH TABLERegister AddressA5 A4 A3 ********************01****DataD4 w.onsemi.com12D0Setting ModeSet Contents00.200 V10.190 V00.180 V10.170 V00.160 V10.150 V00.140 V1/2ch10.130 V0 Current reference voltage0.120 Vsetting10.110 V00.100 V10.090 V00.080 V10.070 V00.060 V10.050 V*CW (forward rotation)1/2ch*CCW (reverse rotation)Excitation rCounter Reset*Output OFF1/2chOutput Enable*Output ON00.200 V10.190 V00.180 V10.170 V00.160 V10.150 V00.140 V3/4ch10.130 V0 Current reference voltage0.120 Vsetting10.110 V00.100 V10.090 V00.080 V10.070 V00.060 V10.050 V*CW (forward rotation)3/4ch*CCW (reverse rotation)Excitation rCounter Reset*Output OFF3/4ch*Output ONOutput Enable
LV8414CSSERIAL DATA TRUTH TABLE (continued)A700A600Register AddressA5 A4 A3 *****DataD4 ***0011*******D00101************0101*******Setting Mode1/2chCLK1 division setting3/4chCLK2 division setting1/2chExcitation mode setting3/4chExcitation mode settingChopping frequencysettingPhoto sensor drivingMO outputChannel settingMO output positionDummy dataSet Contents1 (frequency division)1/21/41/81 (frequency division)1/21/41/8Micro stepHalf stepHalf step (full torque)Full stepMicro stepHalf stepHalf step (full torque)Full step400 kHz200 kHz600 kHz300 kHzOFFON1/2ch3/4chInitial positionHalf step position Precautions for IC OperationsThe supply voltage VCC, ENA pin and I2C output ONsetting stand in the following relationship. VCC, ENA pin, I2C output settings, and outputs1. No output operations are performed unless the ENA pin is set to high and the I2C output setting is set to ON.2. The I2C setting is accepted even if the ENA pin is in low state.(Other I2C settings are also accepted.)3. When the supply voltage VCC is set to low, the internal data is reset.(The I2C output setting in the above figure is initialized to OFF state by the fall in the supply voltage VCC.)Figure 10.www.onsemi.com13
LV8414CSTable 1.ENA PinI2C Output Enable SettingOutputLOFF settingHigh impedance stateHOFF settingHigh impedance stateLON settingHigh impedance stateHON settingOutput ON stateDescription of Stepping Motor Drive Operations The following state settings related to the control of thestepping motor are established using an I2C serial datacommunication. Excitation mode: Micro step (256 divisions), Half step,Half step (full torque), or Full step Excitation direction: CW (clockwise) or CCW(counterclockwise) Step/Hold: Clear or HoldCounter reset: Clear or ResetOutput enable: Output Off or Output OnCurrent setting reference voltages: Selects one of 16valuesChopping frequency: Selects one of 4 valuesCLK Pin FunctionCLK PIN FUNCTIONNOTE:ENACLKOperating modeLow*Standby modeHighExcitation step proceedsHighExcitation step is keptThe excitation steps are advanced by setting the CLK1 (2) from low to high when the ENA is in high state.Initial PositionThe excitation mode is set to the initial position when theIC is set to the initial state at power on or when the counteris reset.INITIAL POSITIONInitial PositionExcitation Mode1ch (3ch)2ch (4ch)256 divisions (1/64) Micro step100%0%Half step100%0%Half step (full torque)100%0%Full step100% 100%www.onsemi.com14
LV8414CSMO Pin FunctionMO is set to low at the initial position and remainsunchanged after it is initialized.* Since the period during which MO is set to low extendsfrom the rising edge of the CLK which is the setting position,to the rising edge of the CLK which moves to the nextposition, care must be taken when a frequency divisionsetting has been established.By setting the MO output channel and MO output positionusing the I2C serial data, the MO pin is set to low at the initialposition in each excitation mode or at the Half step positionin the micro step drive mode.* It is assumed that the Half step setting for the MO outputis used in the micro step drive mode. Even if the MO outputposition is set to Half step in the Half step or Full step mode,Figure 11.www.onsemi.com15
LV8414CSExcitation Mode SettingGiven below and in the following pages are the timingcharts and monitor output pin MO signal in each excitationmode.[Half step Timing Chart]Figure 12.www.onsemi.com16
LV8414CS[Half Step (Full Torque) Timing Chart]Figure 13.www.onsemi.com17
LV8414CS[Full Step Timing Chart]Figure 14.www.onsemi.com18
LV8414CS[Micro step (1/64 Step) Timing Chart]Figure 15.www.onsemi.com19
LV8414CSSwitching the Excitation Mode During OperationThe timing at which the results of switching the excitationmode during operation are reflected and the positionestablished after each excitation mode has been switched areas shown below.[Timing at which the results of switching the excitationmode setting are reflected (from Half step to Full step)]The excitation mode switching is set at the rising edge ofSCLK (8th bit of SCLK) of “D0” and the setting is reflectedstarting with the next CLK.Figure 16.www.onsemi.com20
LV8414CS[Positions When Switching the Excitation Mode Setting]1. Switching to the micro step modeWhen operation has been switched from eachexcitation mode to the micro step mode,excitation position proceeds to the next micro stepposition by the first pulse generated after theswitchingFigure 17.Table 2.Before Switching the Excitation ModeExcitation ModePositionMicro stepq64Step Position after the Excitation Mode is Switched256 Divisions Micro stepq63 to θ33q32q31 to θ1q0Half stepHalf step full torqueFull stepq64q63q32q31q0 q1q64q63q32’q31q0 q1q32’q31www.onsemi.com21
LV8414CS2. Switching to the Half step (Half step full torque)modeWhen operation has been switched from excitationmode to the Half step (Half step full torque) mode,excitation position proceeds to position q32 (q32’)by the first pulse generated after the switching, andthen operation transfers to the Half step (Half stepfull torque) mode.However, if the position established before theexcitation mode switching is q32 (q32’),excitation position proceeds to the next position inthe Half step (Half step full torque) mode by thefirst pulse generated after the switching.3. Switching to the Full step modeIf, in the case of channel 1 to channel 4, operationhas been switched from each excitation mode tothe Full step mode, excitation position proceeds toposition q32’ by the first pulse generated after theswitching, and then to the next position in the Fullstep mode.Figure 18.www.onsemi.com22
LV8414CSTable 3.Before Switching the Excitation ModeStep Position after the Excitation Mode is SwitchedExcitation ModePositionHalf StepHalf Step Full TorqueFull StepMicro stepθ64θ32θ32’θ32’θ63 to θ33θ32θ32’θ32’θ32θ0θ0θ32’θ31 to θ1θ32θ32’θ32’θ0 θ32’Half stepHalf step full torqueFull step θ32’ θ32’θ64θ32’θ32’θ32θ0θ32’θ0 θ32’ θ32’θ64θ32θ32’θ32’θ0θ32’θ0 θ32 θ32’θ32’θ0θ0ENA Pin Function and I2C Serial Data Output Enable Settinglogic circuit is set to the initial excitation position (initialposition).By setting the ENA pin to high, the output becomes ONstate, and the circuit operates from the initial excitationposition.[ENA Pin]VCC consumption current during standby can be reducedto virtually zero by setting the ENA input pin to low.Furthermore, when this pin is set to low, the output becomesOFF state (high impedance), and the state of the internal*The output does not operate unless “output enable” is set to the “output ON” state using an I2C serial data communication.Figure 19.[I 2C Serial Data Output Enable Setting]When “output enable” is set to the “output OFF” state, theoutput is placed in the high impedance state at the risingedge of the 8th SCL bit in the data transmission.However, since the internal logic circuit is activated, theposition number advances if CLK has been input. Thismeans that when “output enable” is set to the “output ON”state after this, the output is set to ON at the rising edge ofthe 8th SCL bit in the data transmission, and that the outputlevel at this time will be the level at the number to which theposition has advanced by the CLK input.www.onsemi.com23
LV8414CS[Timing at which the Output Enable Setting is Reflected (Output OFF)]The output enable setting is reflected at the rising edge ofSCLK (8th bit of SCLK) of “D0”.Figure 20.www.onsemi.com24
LV8414CS[Timing at which the Output Enable Setting is Reflected (Output ON)]Figure 21.www.onsemi.com25
LV8414CSFR Pin Function and I2C Serial Data Excitation Direction Setting[FR Pin]Using the FR1 (FR2) forward/reverse rotation settingsignal input pin, it is possible to switch the excitationdirection between forward and reverse rotation.When FR is set to low, the cl
Logic pin internal pull down resistance Rin ENA, CLK1 to 2, FR1 to 2 50 100 200 k Logic pin input current IinL VIN 0, ENA, CLK1 to 2, FR1 to 2 1.0 A IinH VIN 3.3 V, ENA, CLK1 to 2, FR1 to 2 16.5 33 66 A Logic high level
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grade step 1 step 11 step 2 step 12 step 3 step 13 step 4 step 14 step 5 step 15 step 6 step 16 step 7 step 17 step 8 step 18 step 9 step 19 step 10 step 20 /muimn 17,635 18,737 19,840 20,942 22,014 22,926 23,808 24,689 325,57! 26,453 /2qsohrs steps 11-20 8.48 9.0! 9.54 10.07 10.60 11.02 11.45 11.87 12.29 12.72-
Special Rates 562-600 Station Number 564 Duty Sta Occupation 0083-00 City: FAYETTEVILL State: AR Grade Suppl Rate Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9 Step 10 Min OPM Tab Eff Date Duty Sta Occupation 0601-13 City: FAYETTEVILL State: AR Grade Suppl Rate Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Step 8 Step 9 Step 10 Min OPM Tab Eff Date
Grade Minimum Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Mid-Point Step 8 Step 9 Step 10 Step 11 Step 12 Step 13 Step 14 Maximum Step 15 12/31/2022 Accounting Services Coordinator O-19 45.20 55.15 65.10 Hourly 94,016 114,712 135,408 Appx Annual 12/31/2022 Accounting Services Manager O-20 47.45 57.90 68.34 Hourly
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the quad. William (Bill) Orr, W6SAI (SK) in his book "All About Cubical Quad Antennas" said a group of radio engineers installed a "gigantic" four element quad in Ecuador in 1939 (All About Cubical Quad Antennas, 2nd Ed., Radio Publications, Inc., 1977). Now I see various quad related designs (e.g. "Hexbeam", "Spiderbeam") that
