Computer Organization Tri-State Buffers
Computer Organization! Computer design as an application of digital logic designprocedures! Computer processing unit memory system! Processing unit control datapath! Control finite state machine" Inputs machine instruction, datapath conditions" Outputs register transfer control signals, ALU operation codes" Instruction interpretation instruction fetch, decode, execute! Datapath functional units registers" Functional units ALU, multipliers, dividers, etc." Registers program counter, shifters, storage registersCS 150 – Spring 2007 – Lec #12: Computer Org I - 1Tri-State Buffers! 0, 1, Z (high impedance state)Basic Inverter ininoutOEout OEif OE then Out Inelse “disconnected”outinInverting BufferCS 150 – Spring 2007 – Lec #12: Computer Org I - 2
Tri-States vs. MuxASelBASel0D0E1CSel1B01Sel2:1 MuxBuffer circuits simple!Scales nicely for high fan-inand wide bit widths!Scales poorly for high fan-inor wide bit widthsCS 150 – Spring 2007 – Lec #12: Computer Org I - 3Register TransferASelBSel0D0E1CSel1C!ASel ! 0; Ld ! 1C!BSel ! 1; Ld ! 1BusLdCClkClkSelLdA on BusLd Cfrom BusCS 150 – Spring 2007 – Lec #12: Computer Org I - 4B on Bus?
Open Collector ConceptResistivePull-up “1”Default is highMust activelydrive it low“1”“0”“0”Bad! Short circuit!Low resistance path fromVdd to GndWired AND Configuration:If any attached device wantswire to be “0”, it winsIf all attached devices wantwire to be “1”, it isCS 150 – Spring 2007 – Lec #12: Computer Org I - 5Structure of a Computer! Block diagram viewaddressProcessorread/writecentral processingunit (CPU)dataControlcontrol signalsMemorySystemData Pathdata conditionsinstruction unit– instruction fetch andinterpretation FSMCS 150 – Spring 2007 – Lec #12: Computer Org I - 6execution unit– functional unitsand registers
Registers! Selectively loaded – EN or LD input! Output enable – OE input! Multiple registers –!group 4 or 8 in parallelLDOED7D6D5D4D3D2D1D0Q7Q6Q5Q4Q3Q2Q1Q0CLKOE asserted causes FF state to beconnected to output pins; otherwise theyare left unconnected (high impedance)LD asserted during a lo-to-hi clocktransition loads new data into FFsCS 150 – Spring 2007 – Lec #12: Computer Org I - 7Register Transfer! Point-to-point connection" Dedicated wires" Muxes on inputs ofeach registerMUXMUXMUXMUXrsrtrdR4rsrtrdR4rdR4! Common input from multiplexer" Load enablesfor each register" Control signalsfor multiplexer! Common bus with output enablesMUX" Output enables and loadenables for each registerrsrtBUSCS 150 – Spring 2007 – Lec #12: Computer Org I - 8
Register Files! Collections of registers in one package" Two-dimensional array of FFs" Address used as index to a particular word" Separate read and write addresses so can do both at same time! 4 by 4 register file""""16 D-FFsOrganized as four words of four bits eachWrite-enable (load)Read-enable (output enable)RERBRAWEWBWAD3D2D1D0Q3Q2Q1Q0CS 150 – Spring 2007 – Lec #12: Computer Org I - 9Memories! Larger Collections of Storage Elements" Implemented not as FFs but as much more efficient latches" High-density memories use 1-5 switches (transitors) per bit! Static RAM – 1024 words each 4 bits wide" Once written, memory holds forever (not true for denser dynamicRAM)" Address lines to select word (10 lines for 1024 words)" Read enable# Same as output enable# Often called chip select# Permits connection of manychips into larger array" Write enable (same as load enable)" Bi-directional data lines# output when reading, input when writingCS 150 – Spring 2007 – Lec #12: Computer Org I - 10RDWRA9A8A7A6A5A4A3A2A2A1A0IO3IO2IO1IO0
Instruction Sequencing! Example – an instruction to add the contents of two registers(Rx and Ry) and place result in a third register (Rz)! Step 1: Get the ADD instruction from memory into an instructionregister! Step 2: Decode instruction" Instruction in IR has the code of an ADD instruction" Register indices used to generate output enables for registers Rxand Ry" Register index used to generate load signal for register Rz! Step 3: Execute instruction" Enable Rx and Ry output and direct to ALU" Setup ALU to perform ADD operation" Direct result to Rz so that it can be loaded into registerCS 150 – Spring 2007 – Lec #12: Computer Org I - 11Instruction Types! Data Manipulation" Add, subtract" Increment, decrement" Multiply" Shift, rotate" Immediate operands! Data Staging" Load/store data to/from memory" Register-to-register move! Control" Conditional/unconditional branches in program flow" Subroutine call and returnCS 150 – Spring 2007 – Lec #12: Computer Org I - 12
Elements of the Control Unit (akaInstruction Unit)! Standard FSM Elements""""State registerNext-state logicOutput logic (datapath/control signaling)Moore or synchronous Mealy machine to avoid loops unbroken by FF! Plus Additional ”Control" Registers" Instruction register (IR)" Program counter (PC)! Inputs/Outputs" Outputs control elements of data path" Inputs from data path used to alter flow of program (test if zero)CS 150 – Spring 2007 – Lec #12: Computer Org I - 13Instruction Execution! Control State Diagram (for each diagram)ResetResetFetch instructionDecodeExecuteInit! Instructions partitionedinto three classesFetchInstr.""""" Branch" Load/store" Register-to-register! Different sequencethrough diagram foreach instruction typeBranchBranchTakenBranchNot TakenLoad/StoreIncr.PCCS 150 – Spring 2007 – Lec #12: Computer Org I - 14InitializeMachineXEQInstr.Registerto-Register
Data Path (Hierarchy)! Arithmetic circuits constructed in hierarchical anditerative fashionCin" Each bit in datapath isfunctionally identical" 4-bit, 8-bit, 16-bit,32-bit datapathsAinBinFASumCoutAinHABinHACinCS 150 – Spring 2007 – Lec #12: Computer Org I - 15Data Path (ALU)! ALU Block Diagram" Input: data and operation to perform" Output: result of operation and status informationAB1616Operation16NSZCS 150 – Spring 2007 – Lec #12: Computer Org I - 16SumCout
Data Path (ALU Registers)! Accumulator" Special register" One of the inputs to ALU" Output of ALU stored back in accumulator! One-address instructions" Operation and address of one operand" Other operand and destinationis accumulator register" AC – AC op Mem[addr]" ”Single address instructions”(AC implicit operand)! Multiple registers16REGAC1616OP" Part of instruction usedto choose register operandsN16ZCS 150 – Spring 2007 – Lec #12: Computer Org I - 17Data Path (Bit-slice)! Bit-slice concept: iterate to build n-bit wide rdfrommemory1 bit wideCIfrommemoryfrommemory2 bits wideCS 150 – Spring 2007 – Lec #12: Computer Org I - 18CI
Announcements! Additional readings on-line: CLD 1ed Chapters 11, 12! Lab Checkpoints and Project" Project is a marathon, not a sprint" Not as completely specified or as straightforward as thelabs: creativity, team work as well as technical skill required" Do NOT fall behind schedule may appear to look slack, butit probably won’t be possible to catch up if you fall behind" Partner problems: Keep us informed! Don’t let it fester!" Keep up with your TA design reviews. This is really important!Take them seriously!CS 150 – Spring 2007 – Lec #12: Computer Org I - 19Instruction Path! Program Counter" Keeps track of program execution" Address of next instruction to read from memory" May have auto-increment feature or use ALU! Instruction Register""""Current instructionIncludes ALU operation and address of operandAlso holds target of jump instructionImmediate operands! Relationship to Data Path" PC may be incremented through ALU" Contents of IR may also be required as input to ALUCS 150 – Spring 2007 – Lec #12: Computer Org I - 20
Data Path (Memory Interface)!Memory"Separate data and instruction memory (Harvard architecture)#"Single combined memory (Princeton architecture)#!Single address bus, single data busSeparate memory"""""!Two address busses, two data bussesALU output goes to data memory inputRegister input from data memory outputData memory address from instruction registerInstruction register from instruction memory outputInstruction memory address from program counterSingle memory"""Address from PC or IRMemory output to instruction and data registersMemory input from ALU outputCS 150 – Spring 2007 – Lec #12: Computer Org I - 21Block Diagram of Processor! Register Transfer View of Princeton Architecture" Which register outputs are connected to which register inputs" Arrows represent data-flow, other are control signals fromcontrol FSMloadpath16" MAR may be a simple multiplexerREGACrather than separate registerrd wr16 store16datapath" MBR is split in twoData MemoryOP(16-bit words)(REG and IR)addrN8" Load controlZControlMARfor each registerFSM16IRPC1616OP16CS 150 – Spring 2007 – Lec #12: Computer Org I - 22
Block Diagram of Processor! Register transfer view of Harvard architecture" Which register outputs are connected to which register inputs" Arrows represent data-flow, other are control signals fromcontrol FSMloadpath16" Two MARs (PC and IR)REGAC" Two MBRs (REG and IR)rd wr16 store16data" Load control for each registerpathData Memory(16-bit words)OPNZaddr16ControlFSM16IRPC1616OPaddr16CS 150 – Spring 2007 – Lec #12: Computer Org I - 23A Simplified Processor Data-path andMemory! Princeton architecture! Register filedataInst Memory(8-bit words)memory has only 255 wordswith a display on the last one! Instruction register! PC incrementedthrough ALU! Modeled afterMIPS rt000(used in 61Ctextbook byPatterson &Hennessy)" Really a 32 bitmachine" We’ll do a 16 bitversionCS 150 – Spring 2007 – Lec #12: Computer Org I - 24
Processor Control! Synchronous Mealy machine! Multiple cycles per instructionCS 150 – Spring 2007 – Lec #12: Computer Org I - 25Processor Instructions! Three principal types (16 bits in each instruction)typeopR(egister) 3I(mmediate) 3J(ump)3rs3313rt33! Some of the rsrtoffsetrsrtoffsetrsrtoffsettarget address-funct401234rd rs rtrd rs - rtrd rs & rtrd rs rtrd (rs rt)rt mem[rs offset]mem[rs offset] rtpc pc offset, if (rs rt)rt rs offsetpc target addressstop execution until resetCS 150 – Spring 2007 – Lec #12: Computer Org I - 26
Tracing an Instruction's Execution! Instruction:Rr3 r1 r20rs r1rt r2rd r3funct 0! 1. Instruction fetch" Move instruction address from PC to memory address bus" Assert memory read" Move data from memory data bus into IR" Configure ALU to add 1 to PC" Configure PC to store new value from ALUout! 2. Instruction decode" Op-code bits of IR are input to control FSM" Rest of IR bits encode the operand addresses (rs and rt)# These go to register fileCS 150 – Spring 2007 – Lec #12: Computer Org I - 27Tracing an Instruction's Execution(cont’d)! Instruction:R0r3 r1 r2rs r1rt r2rd r3 funct 0! 3. Instruction execute" Set up ALU inputs" Configure ALU to perform ADD operation" Configure register file to store ALU result (rd)CS 150 – Spring 2007 – Lec #12: Computer Org I - 28
Tracing an Instruction's Execution(cont’d)! Step 1CS 150 – Spring 2007 – Lec #12: Computer Org I - 29Tracing an Instruction's Execution(cont’d)! Step 2CS 150 – Spring 2007 – Lec #12: Computer Org I - 30to controller
Tracing an Instruction's Execution(cont’d)! Step 3CS 150 – Spring 2007 – Lec #12: Computer Org I - 31Register-Transfer-Level Description! Control" Transfer data btwn registers by asserting appropriate control signals! Register transfer notation: work from register to register" Instruction fetch:mabus ! PC;memory read;IR ! memory;op ! add– move PC to memory address bus (PCmaEN, ALUmaEN)– assert memory read signal (mr, RegBmdEN)– load IR from memory data bus (IRld)– send PC into A input, 1 into B input, add(srcA, srcB0, scrB1, op)PC ! ALUout– load result of incrementing in ALU into PC (PCld, PCsel)" Instruction decode:IR to controllervalues of A and B read from register file (rs, rt)" Instruction execution:op ! add– send regA into A input, regB into B input, add(srcA, srcB0, scrB1, op)rd ! ALUout – store result of add into destination register(regWrite, wrDataSel, wrRegSel)CS 150 – Spring 2007 – Lec #12: Computer Org I - 32
Register-Transfer-Level Description(cont’d)! How many states are needed to accomplish thesetransfers?" Data dependencies (where do values that are needed come from?)" Resource conflicts (ALU, busses, etc.)! In our case, it takes three cycles" One for each step" All operation within a cycle occur between rising edges of the clock! How do we set all of the control signals to be output bythe state machine?" Depends on the type of machine (Mealy, Moore, synchronous Mealy)CS 150 – Spring 2007 – Lec #12: Computer Org I - 33Review of FSM Timingdecodefetchstep 1step 2IR ! mem[PC];PC ! PC 1;A ! rsB ! rtexecutestep 3rd ! A Bto configure the data-path to do this here,when do we set the control signals?CS 150 – Spring 2007 – Lec #12: Computer Org I - 34
FSM Controller for CPU (skeletal MooreFSM)! First pass at deriving the state diagram (MooreMachine)" These will be further refined into SW ADDJinstructionexecutionCS 150 – Spring 2007 – Lec #12: Computer Org I - 35FSM Controller for CPU (reset andinstruction fetch)! Assume Moore Machine" Outputs associated with states rather than arcs! Reset state and instruction fetch sequence! On reset (go to Fetch state)" Start fetching instructions" PC will set itself to zeromabus ! PC;memory read;IR ! memory data bus;PC ! PC 1;resetFetchCS 150 – Spring 2007 – Lec #12: Computer Org I - 36instructionfetch
FSM Controller for CPU (decode)! Operation Decode State" Next state branch based on operation code in instruction" Read two operands out of register file# What if the instruction doesn’t have two operands?Decode instructiondecodebranch based on value ofInst[15:13] and Inst[3:0]addCS 150 – Spring 2007 – Lec #12: Computer Org I - 37FSM Controller for CPU (InstructionExecution)! For add instruction" Configure ALU and store result in registerrd ! A B" Other instructions may require multiple cyclesaddCS 150 – Spring 2007 – Lec #12: Computer Org I - 38instructionexecution
FSM Controller for CPU (AddInstruction)! Putting it all togetherand closing the loop" the instructionfetchDecode instructiondecodeaddinstructionexecutionCS 150 – Spring 2007 – Lec #12: Computer Org I - 39FSM Controller for CPU! Now we need to repeat this for all the instructions ofour processor" Fetch and decode states stay the same" Different execution states for each instruction# Some may require multiple states if available register transferpaths require sequencing of stepsCS 150 – Spring 2007 – Lec #12: Computer Org I - 40
CS 150 Ð Spring 2007 Ð Lec #12: Computer Org I - 1 Computer Organization!Computer design as an application of digital logic design procedures!Computer processing unit memory system!Processing unit control datapath!Control finite state m
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