Accumulator V12.0 LogiCORE IP Product Guide (PG119)

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Accumulator v12.0LogiCORE IP Product GuideVivado Design SuitePG119 February 4, 2021

Table of ContentsIP FactsChapter 1: OverviewNavigating Content by Design Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Feature Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Licensing and Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5556Chapter 2: Product SpecificationResource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Chapter 3: Designing with the CoreGeneral Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Chapter 4: Design Flow StepsCustomizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11141415Chapter 5: Example DesignChapter 6: Test BenchAppendix A: UpgradingMigrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback2

Appendix B: DebuggingFinding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Appendix C: Additional Resources and Legal NoticesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Documentation Navigator and Design Hubs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback22222223233

IP FactsIntroductionLogiCORE IP Facts TableThe Xilinx LogiCORE IP Accumulator coreprovides LUT and single DSP slice accumulationimplementations. The Accumulator module cangenerate adder-based, subtracter-based andadder/subtracter-based accumulatorsoperating on signed or unsigned data. Thefunction can be implemented in a single DSPslice or LUTs (but currently not a hybrid ofboth). Pipelining is available for bothimplementations.Core SpecificsSupportedDevice Family(1)UltraScale FamiliesUltraScale ArchitectureVersal ACAPZynq -7000 SoC7 SeriesSupported UserInterfacesN/AResourcesPerformance and Resource Utilization webpageProvided with CoreDesign FilesEncrypted RTLExample DesignNot ProvidedFeaturesTest BenchNot Provided SimulationModelEncrypted VHDLSupportedS/W DriverN/AConstraints FileGenerates add, subtract, and add/subtract-based accumulators Supports two’s complement signed andunsigned operations Supports fabric implementation outputs upto 256 bits wide Supports DSP slice implementation outputsup to 58 bits wide (max width varies withdevice family) Supports pipelining (automatic andmanual) User-programmable feedback scaling forfabric implementations Optional carry output Optional clock enable and sclr Optional Bypass (Load) capabilityAccumulator v12.0PG119 February 4, 2021N/ATested Design Flows(2)Vivado Design SuiteSystem Generator for DSPVivadoDesign EntrySimulationFor supported simulators, see theXilinx Design Tools: Release Notes Guide.SynthesisVivado SynthesisSupportRelease Notesand KnownIssuesAll Vivado IPChange LogsMaster Answer Record: 54492Master Vivado IP Change Logs: 72775Xilinx Support web pageNotes:1. For a complete listing of supported devices, see the Vivado IPcatalog.2. For the supported versions of third-party tools, see theXilinx Design Tools: Release Notes Guide.4Product SpecificationSend Feedbackwww.xilinx.com

Chapter 1OverviewNavigating Content by Design ProcessXilinx documentation is organized around a set of standard design processes to help youfind relevant content for your current development task. This document covers thefollowing design processes: Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardwareplatform, creating PL kernels, subsystem functional simulation, and evaluating theVivado timing, resource and power closure. Also involves developing the hardwareplatform for system integration. Topics in this document that apply to this designprocess include: Port Descriptions Clocking Resets Customizing and Generating the CoreFeature SummaryThe Accumulator core implements area-efficient, high-performance add, subtract andadd-subtract accumulators. The core can be customized to use either fabric logic or a DSPslice to construct the accumulator.ApplicationsThe Accumulator core can be used to implement fixed-point accumulators in a wide rangeof applications, such as phase accumulation for a Numerically Controlled Oscillator (NCO).Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback5

Chapter 1: OverviewLicensing and OrderingThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado Design Suite under the terms of the Xilinx End User License. Information aboutother Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page. Forinformation on pricing and availability of other Xilinx LogiCORE IP modules and tools,contact your local Xilinx sales representative.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback6

Chapter 2Product SpecificationResource UtilizationFor details about resource utilization, visit the Performance and Resource Utilization webpage.PerformanceFor details about performance, visit the Performance and Resource Utilization web page.Port DescriptionsSignal names for the schematic symbol are shown in Figure 2-1 and described in Table 2-1.Table 2-1 shows the SSET and SINIT pins which appear only on fabric implementations.The DSP slice implementations do not support SSET and SINIT.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback7

Chapter 2: Product SpecificationX-Ref Target - Figure 2-1BQADDBYPASSSCLRCLKCESSET*SINIT*C lyDS213 01 111810Figure 2-1:Table 2-1:NameCore SymbolCore Signal PinoutI/ODescriptionB[M:0]IInput busADDIControls operation performed by Adder/Subtractor-based accumulator (High Addition, Low Subtraction)Q[P:0]OOutput busBYPASSIEnables the value on port B to bypass the accumulator logic and appeardirectly on the output register (optionally active-Low)CEIActive-High Clock EnableCLKIClock signal: rising edgeSCLRISynchronous Clear: forces the output to a Low state when driven HighSINIT(1)ISynchronous Initialize: forces outputs to user-defined state when driven HighISynchronous Set: forces the output to a High state when driven HighICarry InputSSET(1)C INNotes:1. Available only for fabric implementations.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback8

Chapter 3Designing with the CoreThis chapter includes guidelines and additional information to facilitate designing with thecore.General Design GuidelinesPipelined OperationThe Accumulator module can be optionally pipelined to improve speed. The pipelinedoperation is controlled by the latency parameters. Set Latency Configuration to Automatic to achieve optimal pipelining for maximumspeed. Set Latency Configuration to Manual to allow a valid number of pipeline stages to beentered in the Latency parameter. For Latency 1, only output registers are present. For Latency 2, output and input registers are present.After power-up or reset, the pipelined module takes many clock cycles, specified by thelatency control, for the outputs to become valid.If Bypass is requested on a pipelined module, the BYPASS input appears on the outputafter the number of clock cycles, specified by the latency control.ClockingThe core requires a single clock, CLK, and is active-High triggered.If selected, the active-High clock enable, CE, stalls all core processes when deasserted.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback9

Chapter 3: Designing with the CoreResetsThe core has a single, active-High synchronous reset, SCLR. Asserting SCLR for a singlecycle resets all registers in the core.The priority of SCLR and CE pins can be selected when customizing the core.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback10

Chapter 4Design Flow StepsThis chapter describes customizing and generating the core, constraining the core, and thesimulation, synthesis and implementation steps that are specific to this IP core. Moredetailed information about the standard Vivado design flows and the IP integrator can befound in the following Vivado Design Suite user guides: Vivado Design Suite User Guide: Designing IP Subsystems using IP integrator (UG994)[Ref 1] Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] Vivado Design Suite User Guide: Getting Started (UG910) [Ref 3] Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 5]Customizing and Generating the CoreThis section includes information about using Xilinx tools to customize and generate thecore in the Vivado Design Suite.If you are customizing and generating the core in the Vivado IP integrator, see the VivadoDesign Suite User Guide: Designing IP Subsystems using IP integrator (UG994) [Ref 1] fordetailed information. IP integrator might auto-compute certain configuration values whenvalidating or generating the design. To check whether the values do change, see thedescription of the parameter in this chapter. To view the parameter value, you can run thevalidate bd design command in the Tcl Console.You can customize the IP for use in your design by specifying values for the variousparameters associated with the IP core using the following steps:1. Select the IP from the IP catalog.2. Double-click the selected IP or select the Customize IP command from the toolbar orright-click menu.For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2] andthe Vivado Design Suite User Guide: Getting Started (UG910) [Ref 3].Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback11

Chapter 4: Design Flow StepsCore ParametersThe Accumulator core Vivado IDE provides fields to set the parameter values for therequired instantiation. This section provides a description of each field. Implement using: Sets the implementation type: Fabric or DSP Slice. Input Width: Sets the width of the input port. In IP integrator, this parameter isauto-updated. Input Type: Sets the type of the Port B data: Signed or Unsigned. In IP integrator, thisparameter is auto-updated. Output Width: Sets the output width. Accumulation Mode: Sets the mode of operation of the module. If an adder/subtracteris specified, the ADD pin sets the mode of operation. Carry In: When set to TRUE, this generic creates the C IN port, which is thesynchronous carry-in to the accumulator. Bypass: When set to TRUE, creates a BYPASS pin. Activating the BYPASS pin sets theoutput as the value given on Port B. This functionality is used for creating loadableaccumulators. Bypass Sense: When set to active-Low, the BYPASS pin is active-Low. BYPASS is theonly pin that has a parameter to control its active sense. This is because an historicalimplementation made significant speed gains with an active-Low BYPASS, instead ofactive-High BYPASS. This is no longer necessarily the case, because sometimesactive-High is as or more efficient. The details depend on the exact set of parameters. Accumulator Scaling: Sets the scaling factor used for the feedback path to Port B onfabric implementations. The value represents the number of low-order bits that arediscarded in the feedback process. Clock Enable: When set to TRUE, the module is generated with a clock enable input. Power-on Reset Init value: Specifies in binary the value the output initializes to duringpower-up reset. Synchronous Clear: Specifies if an SCLR pin is to be included. Synchronous Set: Specifies if an SSET pin is to be included. SSET pin is not valid inDSP slice implementations. See Sync Set and Clear (Reset) Priority for SCLR/SSETpriorities. Synchronous Init: Specifies if an SINIT pin is to be included which, when asserted,synchronously sets the output value to the value defined by Init Value.Note: If SINIT is present, then neither SSET nor SCLR can be present. The SINIT pin is notvalid in DSP slice implementations. Init Value: Specifies, in hex, the value that the output initializes to when SINIT isasserted. Ignored if Synchronous Init 0.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback12

Chapter 4: Design Flow Steps Synchronous Controls and Clock Enable (CE) Priority: This parameter controlswhether or not the SCLR (and if fabric: SSET and SINIT) inputs are qualified by CE.When set to Sync Overrides CE, the synchronous controls override the CE signal. Whenset to CE Overrides Sync, the control signals have an effect only when CE is High.Note: On the fabric primitives, the SCLR and SSET controls override CE, so choosingCE Overrides Sync generally results in extra logic. Sync Set and Clear (Reset) Priority: Controls the relative priority of SCLR and SSET.When set to Reset Overrides Set, SCLR overrides SSET. The default isReset Overrides Set, as this is the way the primitives are arranged. Making SSET takepriority requires extra logic. Latency Configuration: Automatic sets optimal latency for maximum speed; Manualallows you to set Latency to one of the allowed values. Latency: Value used for latency when Latency Configuration is set to Manual. See thesection, Pipelined Operation, for more information.User ParametersTable 4-1 shows the relationship between the fields in the Vivado IDE and the UserParameters (which can be viewed in the Tcl console).Table 4-1:Vivado IDE Parameter to User Parameter RelationshipVivado IDE ParameterUser ParameterDefault ValueImplement usingimplementationFabricInput Typeinput typeSignedInput Widthinput width16Output Widthoutput width16Accumulation Modeaccum modeAddLatency Configurationlatency configurationManualLatencylatency1Accumulator Scalingscale0Clock Enable(CE)ceFalseCarry In(C IN)c inFalseSynchronous Clear(SCLR)sclrFalseSynchronous Set (SSET)ssetFalseSynchronous Init (SINIT)sinitFalseInit Value (Hex)sinit valueFalseBypassbypassTrueBypass Sensebypass senseActive HighAccumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback13

Chapter 4: Design Flow StepsTable 4-1:Vivado IDE Parameter to User Parameter Relationship (Cont’d)Vivado IDE ParameterUser ParameterDefault ValueSynchronous Set and Clear(Reset)PrioritysyncctrlpriorityReset Overrides SetSynchronous Controls and ClockEnable (CE) Prioritysync ce prioritySync Overrides CECore Use through the Vivado Design SuiteThe Vivado IDE performs error-checking on all input parameters. Resource estimation andlatency information is also available.Several files are produced when a core is generated, and customized instantiationtemplates for Verilog and VHDL design flows are provided in the .veo and .vho files,respectively. For detailed instructions, see the Vivado Design Suite User Guide: Designingwith IP (UG896) [Ref 2].Core Use through System GeneratorThe Accumulator core is available through Xilinx System Generator for DSP, a DSP designtool that enables the use of the model-based design environment Simulink software forFPGA design. The Accumulator core is one of the DSP building blocks provided in the XilinxDSP blockset for the Simulink software. The core can be found in the Xilinx Blockset in theMath section. The block is called “Accumulator”. See the System Generator for DSP UserGuide (UG640) [Ref 4] for more information.Output GenerationFor details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 2].Constraining the CoreThere are no constraints associated with this core.SimulationFor comprehensive information about Vivado simulation components, as well asinformation about using supported third-party tools, see the Vivado Design Suite UserGuide: Logic Simulation (UG900) [Ref 5].Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback14

Chapter 4: Design Flow StepsIMPORTANT: For cores targeting 7 series or Zynq-7000 devices, UNIFAST libraries are not supported.Xilinx IP is tested and qualified with UNISIM libraries only.Synthesis and ImplementationFor details about synthesis and implementation, see the Vivado Design Suite User Guide:Designing with IP (UG896) [Ref 2].Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback15

Chapter 5Example DesignNo example design is provided for this core.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback16

Chapter 6Test BenchNo demonstration test bench is provided for this core.Accumulator v12.0PG119 February 4, 2021www.xilinx.comSend Feedback17

Appendix AUpgradingThis appendix contains information about migrating a design from ISE to the Vivado Design Suite, and for upgrading to a more recent version of the IP core. For customersupgrading in the Vivado Design Suite, important details (where applicable) about any portchanges and other impact to user logic are included.Migrating to the Vivado Design SuiteUpdating from Accumulator v9.0 and LaterThe Vivado Design Suite IP update feature can be used to update an existing Accumulatorto v12.0 of the core. The core can then be regenerated to create a new netlist. See the ISEto Vivado Design Suite Migration Guide (UG911) [Ref 6] for more information on this feature.Updating from Versions Prior to Accumulator v9.0It is not currently possible to automatically update versions of the Accumulator core prior tov9.0. Some features and configurations might be unavailable in Accumulator v12.0, andsome port names might differ between versions.RECOMMENDED: Use the Accumulator v12.0 Vivado IDE in the Vivado Design Suite to customize a newcore.Upgrading in the Vivado Design SuiteThis section provides information about any changes to the user logic or port designatio

DS213_01_111810 Q *fabric implementation only B ADD BYPASS SCLR CLK CE SSET* SINIT* C_IN *fabric implementation only Send Feed back. Accumulator v12.0 9 PG119 February 4, 2021 www.xilinx.com Chapter 3 Designing with the Core This chapter includes guidelines an

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