CMOS Image Sensors: Recent Innovations In Imaging
Special Issue - 2019International Journal of Engineering Research & Technology (IJERT)ISSN: 2278-0181NCRIETS – 2019 Conference ProceedingsCMOS Image Sensors: Recent Innovations inImaging TechnologyDr. Gagan KhanduriAssociate Professor,Dev Bhoomi Institute of Technology, DehradunAbstract:- Recent advances in CMOS imager technology hasshown the potential to be applicable in the field of spacetechnology, apart from its use in consumer digital camcorders,PC and cellphone cameras, machine vision, surveillance, toys,ID checks, etc. to name a few. The rapid progress has enabledthe CMOS Imaging devices to compete with the well-establishedCCD devices. CMOS imagers has a definite edge over CCDdevices vis-à-vis integration with standard CMOS operation,compact size, low cost, low power, on-chip support circuitry,random access, radiation tolerance, etc. The heart of presentday CMOS digital camera is its pixel array. The Active PixelSensor (APS) comprises of multi-transistors (NMOS or PMOS)pixel, along with the photodiode or photogate to capture thelight. The incident photons are converted into respective chargeand/or voltage values. The Column Amplifier further moves thisvoltage to Double Correlated Sampling circuit and the resultantvoltage value is converted into Digital Domain by the Analog-toDigital converter (ADC). After this, Storing and Processing ofthe digital data is done by the digital block of the camera, whichis considered as a relatively noise-proof operation. The majorissue of various Temporal and Fixed pattern Noise, dark currentetc. are inherited from the basic pixel block. Therefore, one ofthe most important parts of noise reduction in digital camera isto improve the noise performance of the pixel structurecomprising of Photodiode/photogate and various NMOSTransistors. The present paper gives a brief insight into thedevelopment, design and working of a typical 4-Transistor (4T)APS. Various other pixel designs are also discussed briefly tobring out the 4T pixels abode in the CMOS APS device scene. Adiscussion on various Characterization factors to evaluate 4TAPS functioning as a digital image sensing device and its Noiseissues are also presented.Keywords: CMOS imaging, Active Pixel Sensors, 4T pixels, pixelnoise, pixel characterizationI.INTRODUCTION:The first ever metal oxide semiconductor (MOS)image sensorwas suggested by Morrison in 1963 [1]. However, the firstMOS image sensorin photon flux integration mode wasproposed in 1967 by Weckler [2], which was a passive pixelsensor (PPS) [3]. In a typical PPS, the photons are convertedinto electrical charge by the photosite (photodiode), and thischarge is controlled using a single pass transistor (MOSswitch) to taken out of the pixel, and the signal is readout incharge sensing mode.This use of photosite for charge sensingand charge integration is the central theme in even presentday complementary metal oxide semiconductor (CMOS)image sensors. Incidentally, the first MOS active pixel sensor(APS) was soon realizedin 1968 by Noble [4], whichproposed the voltage sensing mode for photodiode(PD)charge by using an in-pixel buffer amplifier in Sourcefollower mode. However, the MOS fabrication technology ofVolume 7, Issue 12that era was still under-developed for a mature image sensorstechnology, using a photodiode and MOS. The commercialviability and research interest took a back step for MOSimage sensors, due to the excessive spatial noise (fixedpattern noise, FPN) in pixel arrays.In 1970, Boyle and Smith invented theCharge Coupled Devices (CCDs), which originally were tobe used as memory devices [5]. However, the light sensitiveproperties of CCDs were quickly recognized and owing totheir simpler structure and much lower FPN, they almostfinished any remaining interest in MOS imagers barring few[6, 7].Although, from 1970 to 1990, the commercial viabilityof CCD was firmly established and almost all digital imagingwas done using CCDs, nevertheless the improvement inCMOS fabrication process, lead researchers to consider theCMOS image sensors as an alternative to the CCDtechnology in early 1990’s.The main motivation to look for CMOSimage sensors came from the fact that CCDs are made usinga dedicated fabrication process for photosensing elements,and it is difficult to co-integrate the functional blockscomprising of CMOS transistors with the CCD chip. On theother hand, CMOS imager showed the ability to provide theon-chip timing, control, correlated double sampling (CDS),and FPN suppressing circuitry along with the CMOS imagesensor, by using the same fabrication process as standardCMOS processing [8]. Other motivations for using theCMOS APS imagers over CCDs are: low powerconsumption, lower cost, compactness, high speed, randomaccess, integration with other devices, antiblooming,smearless operation etc. [9]. Nonetheless, CMOS imagersstill has to compete with CCDs vis-à-vis pixel sensitivity tophoton flux, dynamic range (DR), and noise issues etc [10].II.DEVELOPMENT, DESIGN AND WORKING OFCMOS APS:The CMOS pixel sensors use a photogate or photodiode tocapture the photon flux and convert it into correspondingelectrical charge. The main photodiode type MOS pixelsensors which use the photon flux integration mode can bedivided into 2 basic approaches, i.e. of passivepixels (PPS)and active pixels (APS) [11]. A brief description of thephotodiode type Pixel sensors is given as:A.Passive Pixel Sensor (PPS) with photodiodeAs shown in figure 1, Weckler [3] proposed the first PPSconsisting of a photodiode and just one MOS transistor,which act as a switch to move the pixel signal charge on to aload resistor RL. The integrated charge on photodiode wasPublished by, www.ijert.org1
Special Issue - 2019International Journal of Engineering Research & Technology (IJERT)ISSN: 2278-0181NCRIETS – 2019 Conference Proceedingsread out by measuring the voltage across the load resistor,which was needed to reset the pixel. To integrate this pixelinto array, he proposed the column wise load resistances, atthe bottom of pixel columns.Although, this device still suffers from FPN (difference inCIAs), sensitivity and speed issues and used only for lowerend consumer electronics, it boasts of highest design fillfactor for a given pixel size. This leads to a very highQuantum efficiency (electrons collected per photon incident).B.Active Pixel Sensor (APS) with photodiodeNoble [4] in 1968 showed the use of a MOS buffer amplifieralong with a photodiode in the pixel to use the voltagesensing mode for signal readout. The buffer amplifier is usedas a source follower to output the photodiode voltage asshown in figure 3.Fig. 1. Passive pixel sensor (PPS) array schematic, as proposed by Dyck andWeckler [3].But this readout technique had limited use for large arraysdue to large reset timing issues. Noble [4] proposed a onecharge integration amplifier (CIA) per array for readout. Butthis technique suffers from large parasitic capacitance (due toall the data lines) and output signal voltage can besignificantly reduced. To overcome the parasitic capacitanceproblem, more modern PPS use a column wise CIA at thebottom of each column bus, and uses one addressing (access)transistor, as shown in figure 2.At the start of a frame capture,the access transistor is activated such that the photodiode isconnected to the vertical column bus. This resets thephotodiode to a reverse bias of Vref. The access transistor isthen opened for the integration time (T int) and photodiode isallowed to discharge at a rate approximately proportional tothe incident illumination to the final value V diode. Now, whenthe address transistor is again activated, the current flows viathe resistance and capacitance of the column bus because ofpotential difference of Vref-Vdiode. This total charge requiredto reset the diode is integrated by the capacitor Cint, andoutput as a Vout. Eventually, the final bus and diode voltagesare returned to Vref by CIA. The address MOS is turned offand the voltage across Cint is removed by the reset MOS, andthe next cycle ensues.Fig. 3.First active pixel sensor (APS) with a photodiode and buffer amplifier(T3) for voltage sensing mode,as proposed by Noble [4].The use of the buffer amplifier enables the lower noise leveland higher readout speed. The power dissipation is minimalin this configuration as each amplifier is only activatedduring readout. In Noble’s MOS APS, due to the immaturefabrication technology, variations in diode dark currents,MOSFET threshold voltages and variations in leakages,capacitances etc. in circuitry lead to large FPN and very lowsignal to noise ratio (SNR). However, modern APS withimproved CMOS fabrication process have managed to reducethe device variations and hence the FPN [12].(a)Three Transistor (3T) APS: The most basic form ofpresent day CMOS APS employs the photodiode and areadout circuit of three MOS transistors and called as 3Tpixel.The three nMOS transistors are RESET transistor (M rst),Source Follower (Msf) and row–select (Msel) transistor, asshown in figure 4.Fig. 2. Modern PPS array with column wise Charge Integration amplifier(CIA).Figure 4. A Three-transistor (3T) active pixel sensor (APS)Volume 7, Issue 12Published by, www.ijert.org2
Special Issue - 2019International Journal of Engineering Research & Technology (IJERT)ISSN: 2278-0181NCRIETS – 2019 Conference ProceedingsHere, the PD capacitance is independent of the column buscapacitance and comprises only of the diode capacitance, M rstsource capacitance and Msf gate capacitance. The p-njunction of the photodiode is used as the photon sensingnode. The MrstnMOS is used to reset the PD to a value equalto [reset voltage (VRST) – threshold voltage (Vt)], before theintegration time starts and then the Mrst is switched OFFduring Tint. This sets the base voltage for the integratedsignal. The integrated charge is then accumulated in the PDduring Tint and the photodiode voltage decreases from the(VRST-Vt) value due to the electron accumulation in PD. Thereduced PD voltage is then sensed by the Msf. The nMOSsource follower transistor Msf is acting as a voltage buffer todrive the output independently of the diode. The sourcevoltage of Msf is then output using the Msel transistor which isacting as a switch and select transistor. There is a singleactive-current-source-load for each column (to keep fill factorhigh and FPN low) and readout timing is set such that onlyone row is activated at any time. The signal voltage is thussampled. Now, the Mrst is switched ON to re-create the basevoltage for PD. The double sampling circuitry in the columnthen subtracts the signal voltage from reset voltage and thelight intensity is determined. The double sampling operationis supposed to negate the threshold mismatch of the M sftransistors so that the pixel FPN is reduced. However, thetemporal noise in the 3T pixel is rather high owing to thedifferent reset voltages used in the signal base voltage and recreated reset level. Thus the two sampled signals in factcontain the reset noise from different reset operations. Sincethe Reset noise (also called as kTC noise, which originatesfrom thermal noise of nMOS Mrst transistor) here is noncorrelated, this double sampling operation actually increasesthe resulting noise power. Nonetheless, the typical fill factorfor 3T APS is still reasonable (20-35%) and a major reasonfor its large scale commercialization in CMOS imagers.(b)Four Transistor (4T) APS: In the 4T pixel, anadditional nMOS transistor is used as transfer gate (TG),which separates the photodiode (PD) from the reset transistor(RG) source and floating diffusion (FD) region and hence thesource follower (SF) gate, as shown in figure 5.Fig. 5.A four-transistor (4T) active pixel sensor (APS)schematic during resetoperation.Volume 7, Issue 12Row select nMOS transistor (SG) is used as switchto sample the signal voltage and reset voltage. This enablesthe 4T pixels to have an electronic global shutter and makeuse of correlated double sampling (CDS). In principle, thisshould remove the offset and noise due to reset signal afterdouble sampling operation. The operation starts with a resetpulse to PD while RG and TG are switched ON. This resetsthe PD to a voltage of (VDD-Vt(RG)). Next, the TG is switchedoff and PD is allowed to integrate the charge. A second resetpulse is then sampled at the end of the T int, which also clearsthe FD off dark current charge and leakage current throughTG. The TG is then switched ON and the signal voltage issampled and subtracted from reset voltage through CDS [13].A further improvement in 4T APS is proposed by using thepinned photodiode principle [14]. A pinned photodiodemeans 2 things: a diode that is fully depleted of mobilecharges and one where silicon surface states are pinned to avoltage. The device uses additional implantation steps to thestandard CMOS process, which implants an additional P surface implant on the surface of PD, as shown in figure 6.Fig. 6. A 2-D depiction of pinned photodiode (PPD) active pixel sensor(APS)The P implant acts like a self-biased internal photogate.Here, the doping levels and implant depths are carefullycontrolled to deplete the n-region completely. The P implantpins the potential at the PD surface to that of the substrate,andso do not contribute to generation/recombination currents,leading to lower dark current. Moreover, a buried PD well isformed which encourages the blue electrons to move awayfrom the surface towards the buried PD well. However, atradeoff is there to consider a heavy doping to reduce the darkcurrent generation at surface or to have a shallower implant tobring the electric field closer to the surface and collect moreblue electrons.III.NOISE ISSUES IN CMOS APS:The CMOS APS are designed to maximize the sensitivity toillumination; however the overall performance of the sensoris ultimately limited by the noise that is added by the systemto the signal. One of the most important figures of merit ofCMOS APS is its dynamic range (DR), which is given as theratio of saturation signal to rms noise level. The minimumresolvable signal is determined by the noise in the system,and would require a very low noise floor (also called readnoise, comprising of amplifier noise, reset noise and ADCnoise) to collect reasonable data at low light levels. Asmentioned earlier, reset noise is thermal noise of RSTPublished by, www.ijert.org3
Special Issue - 2019International Journal of Engineering Research & Technology (IJERT)ISSN: 2278-0181NCRIETS – 2019 Conference Proceedingstransistor and occurs due to charging of PD capacitancethrough the resistance of RGnMOS channel. Flicker Noise(1/f noise) is due to the conductivity fluctuations at junctionsand arises mainly in amplifier circuits. At low frequency, 1/fnoise can be a dominant factor. Apart from the read noise, theother two system noise components are the shot noise (due tostatistical arrival of photo-generated electrons and thermalgenerated electrons in depletion region) and pattern noise.Typically, the noise in CMOS APS can be categorized as:Random Noise[15] and Pattern Noise [13]. The random noise(temporal noise) is not constant from frame to frame and socan be reduced by averaging the frames. However, the patternnoise is effectively a spatial noise and does not change fromframe to frame, so cannot be removed by frame averaging.The pattern noise can be subdivided into 2 components;fixedpattern noise (FPN) and photo response non uniformity(PRNU). FPN is measured in the absence of illumination, andis mainly due to the variations in MOS characteristics (Vt,gain, W, L etc.), doping variations, dimension variations, orcontamination during fabrication between pixels. Morespecifically, the main cause of FPN in CMOS imagers is thevariation in nMOS Vt of RST and SF transistors betweenpixels and Vt variations between MOSFETs in columncircuits.FPN can also occur due to faulty array clocking. Inthe late 1960’s, FPN was the main reason for rejection ofCMOS imagers.However, FPN is independent of theillumination level. PRNU on the other hand is illuminationdependent and is caused due to variations in PD dimension,doping, topography and spectral response between pixels.Ageneral depiction of various noise components in CMOS APSis given in figure 7.Fig. 7.Various components of CMOS APS noise and their introductionregime.To apply the noise reduction technique,there are essentially three classes of noise; noise whichcannot be reduced (shot noise), noise which can be reducedby better design of circuit components (thermal noise) andnoise which can be reduced by circuit design (FPN).However, adding extra circuit to reduce FPN would increase1/f noise and KTC noise. Photon shot noise is dependent onthe illumination level and we cannot reduce it withoutreducing the quantum efficiency (QE) of the PD. Shot noisealso arises from the pixel dark current. This again can bereduced by increasing the doping level and reducing thedepletion region of PD, but will again adversely affect the QEof the diode. Fortunately, shot noise is not the usual limitingfactor in CMOS APS. In general, smaller MOS channellength and an optimized channel width would reduce thethermal noise. Flicker noise arises mainly due to the trappingdetrapping of electrons at the Si-SiO2 interface. So, reducingVolume 7, Issue 12the channel length is a viable option to reduce the devicearea, as channel width cannot be reduced due to adverseeffect on amplifier gain. Flicker noise in CCD was reducedby using the buried channel device (BCD), however,implementing BCD in CMOS APS is a challenging task.Reset noise is difficult to design out of the CMOS APSsystem unless we go for lower FD node capacitance, whichalso increases the conversion gain. The most commonsolution to remove reset noise is to measure the reset noiseand then subtract it from the signal as is done in correlateddouble sampling (CDS). In CMOS APS, we need one CDScircuit per column of the pixel array and sample and hold iscarried out for all columns in parallel. However, Columnwise CDS circuitry could further add the KTC noise from thesample and hold capacitors and thermal and flicker noisefrom its MOSFETs.Moreover, column wise FPN could alsobe added by the CDS circuits themselves which appears asvertical streaks in the image. But this column FPN could beremoved by storing and subtracting the column referencesignals off chip.Apart from the random and pattern noisesources mentioned, there could be design issues which lead toadditional noise and therefore careful layout needs to be donefor CMOS APS.IV.CHARACTERIZATION FACTORS FOR CMOSAPS:The most common pixel array performance criteria are readnoise (Nr), PD full well capacity (FWC), conversion gain(CG) and responsivity (Rp). FD node capacitance, maximumoutput voltage swing (MOVS), dynamic range (DR) andsignal to noise ratio (SNR) can be calculated using thisinformation [16, 17]. Other important pixel performance isrelated with dark current (DC) measurements and noise dueto dark current. All the noise components related toTemporal, FPN and pixel noise are also obtained racterization. A brief description of variouscharacterization parameters are given as:A.Pixel Characteristics: The pixel characteristics are ameasure of the pixels performance and can be classified as:(a)Dark Current (DC): Dark current is measured asPD signal response when it is allowed to integrate thethermally generated charges under complete absence ofillumination. This parameter is always reported at a particulartemperature. The dark FPN becomes an important parameterunder low light conditions. It is advantageous to have lowerDC and DC related noise components for improved pixelperformance.(b)Fill Factor (FF): It is defined as the ratio of lightcapturing area of pixel to that of the total pixel area. CCDshas almost 100% FF [18.19], whereas, CMOS APS has 30%FF, typically. The lower FF in CMOS APS is due to
CMOS APS: The CMOS pixel sensors use a photogate or photodiode to capture the photon flux and convert it into corresponding electrical charge. The main photodiode type MOS pixel sensors which use the photon flux integration mode can be divided into 2 basic approaches, i.e. of passivepixels (PPS) and active pi
Full-frame vs. APS-C, some other considerations 10 IV. THE ECONOMICS OF IMAGE SENSORS 11 Wafers and sensors 11 V. WHY CMOS? 13 CCD 13 CMOS 14 Power consumption issues 15 Speed issues 16 Noise issues 17 VI. CANON’S UNIQUE R&D SYNERGY 20 Other differences between CMOS and CCD image sensors
CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0
8. n-CH Pass Transistors vs. CMOS X-Gates 9. n-CH Pass Transistors vs. CMOS X-Gates 10. Full Swing n-CH X-Gate Logic 11. Leakage Currents 12. Static CMOS Digital Latches 13. Static CMOS Digital Latches 14. Static CMOS Digital Latches 15. Static CMOS Digital Latches . Joseph A. Elias, PhD 2
SOI CMOS technology has been used to integrate analog circuits. In this section, SOI CMOS op amp is discussed. Then, the performance comparison of op amps using bulk and SOI CMOS technologies is presented. 3.1 Analysis on SOI CMOS Op amp Figure 5 shows an SOI CMOS single stage op amp with a symmetrical topology. This circuit has a good .
CMOS Setup Procedure for Dispense System CPU Board PN 2025-0121 CMOS Setup Procedure Use this procedure to set computer CMOS parameters for dispense system CPU board (PN 2025-0121) with CPU, memory, and fan. 1. Activate BIOS/CMOS Setup Utility (pg 1) 2. Preset CPU board (pg 2) 3. Computer CMOS Parameters (pg 2) 4. Save Changes (pg 5) Revision .
image sensors first appeared in the late 1960s,'3 most of todays CMOS image sensors are based on work done starting around the early 1980's. Until the early 1990s PPS was the CMOS image sensor technology of choice.'4'8 The feature sizes of the available CMOS technologies were too large to accomodate more than a
When using either CCD or CMOS APS technology, electronic image sensors are based on analog pixels. With CCD sensors, data conversion is done at board level, and with CMOS APS ones, data conversion is done at either chip or column level. Because digital data is more
Reading Comprehension GRADE 10. Student Name School Name. District Name. ELEMENTELEMENTARY & SECONDARYTARAARRY & SECONDAR&RY. Massachusetts Department of. This is a practice test. Your responses to practice test questions must be recorded on your Practice Test Answer Document. Mark only one answer for each multiple-choice question. If you are not sure of the answer, choose the answer you think .
