AN 684: Design Guidelines For 100 Gbps - CFP2 Interface

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Design Guidelines for 100 Gbps - CFP2 Interface2013.03.29AN-684SubscribeFeedbackThis document shows an example layout design that implements a 4 x 25/28 Gbps CFP2 module interfacethat meets the insertion and return loss mask requirements proposed in the working clause draft version8.0 for CEI-28G-VSR.The common electrical interface CEI-28G-VSR implementation architecture (IA) for short reach channelsis intended for next generation 100 Gbps chip - to - optical module applications. CFP2 is a pluggable opticalmodule that uses CEI-28G-VSR as its electrical interface (as defined by the CFP Multi-Source Agreement(MSA) member companies). CFP2 also defines the mechanical form factor for a 100 Gbps optical transceivermodule targeted for Ethernet and OTN (Optical Transport Network) applications.CFP2 provides an industry standard to develop next generation 100 G interfaces with lower power andgreater port density compared to previous generation CFP optical modules.Note: For more information, refer to the CEI-28G-VSR working clause specification. Document numberOIF2010.404.08.Figure 1: Stratix V GT Device to a CFP2 Pluggable Module Interface on a PCBModuleCageStratix V GT DeviceTX and Transceiver Serial LinkIngressPCB dViasThe channel layout on the PCB is optimized in order to meet the strict insertion and return loss masksdefined by CEI-28G-VSR.Refer to the following documents for more information on optimizing your board designs for high speedserial links.Related LinksAN529: Via Optimization Techniques for High-Speed Channel DesignsAN530: Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIXwords and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other wordsand logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves theright to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the applicationor use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised toobtain the latest version of device specifications before relying on any published information and before placing orders for products or services.www.altera.com101 Innovation Drive, San Jose, CA 95134ISO9001:2008Registered

2AN-6842013.03.29Stratix V GT Transceiver ChannelsStratix V GT Transceiver ChannelsStratix V GT FPGAs offer four transceiver channels (ATT TXR[3:0] P/N and ATT RXR[3:0] P/N) thatcan operate up to 28 Gbps for interfacing with CFP2 or other optical modules.Figure 2: Top View of 28 Gbps Transmitter and Receiver Channel Locations in Stratix V GT NMLKJHGFEDCBA393530252015105ATT TXRN 0ATT TXRP 0ATT RXRN 0ATT RXRP 0ATT TXRN 1ATT TXRP 1ATT RXRN 1ATT RXRP 1ATT TXRN 2ATT TXRP 2ATT RXRN 2ATT RXRP 2ATT TXRN 3ATT TXRP 3ATT RXRN 3ATT RXRP 31CFP2 Host Connector Assembly and PinoutThe CFP2 specification defines the mechanical connector requirements for the 104-pin CFP2 connector.The host connector assembly is composed of a female host connector, and a metal connector cover and cagefor retention and electromagnetic shielding of the inserted CFP2 optical module.Altera CorporationDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedback

AN-6842013.03.29CFP2 Host Connector Assembly and Pinout3Figure 3: CFP2 Host Connector Assembly for a 4x25G/28G Module Interface as Defined by the CFP2Mechanical SpecificationCageConnector CoverConnectorNote: This figure is courtesy of Yamaichi Electronics.Design Guidelines for 100 Gbps - CFP2 InterfaceFeedbackAltera Corporation

4CFP2 Host Connector Assembly and PinoutAN-6842013.03.29Figure 4: CFP2 Host Connector Pinout for 4x25G/28G Module Interface as Defined by the CFP2 MechanicalSpecificationAltera CorporationDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedback

AN-6842013.03.29Stratix V GT to CFP2 Interface Layout Design5Figure 5: CFP2 Host Connector Layout FootprintThe high-speed transceiver pins are identified in the following figure to show their position within theconnector. Blue pins are the TX transceiver channels and red pins are the RX transceiver 5209015951010051041Stratix V GT to CFP2 Interface Layout DesignThe TX and RX channels are connected directly to the CFP2 connector with approximately 5.5 inches ofdifferential trace routing on the top and bottom layer of the board. DC blocking capacitors are included inthe optical module for both the TX and RX traces. Nominal trace impedance is controlled at approximately100Ω differential and the board material used is Panasonic Megtron-6.Figure 6: Stratix V GT to CFP2 Interface Layout Design ExampleThe figure shows an example layout design where the green traces are the TX channels routed on the toplayer while the orange traces are the RX channels routed on the bottom layer.CFP2 ConnectorCover KeepoutRX0RX1RX2RX3Channel RoutingTX0TX1TX2TX3TX Signals ChangingLayer to Avoid CFP2Metal Connector CoverCFP2 ConnectorStratix V GT BGAIn this example, vias are used for the RX channel breakout at the BGA, and for both the TX and RX channelsat the CFP2 connector. To avoid the top layer keep out requirement of the CFP2 metal connector coverassembly, the TX channel routing is switched briefly to the bottom layer and then back to the top layer atthe CFP2 connector as illustrated by the circled area in the above figure. Top to bottom routing is used toavoid via stubs.Design Guidelines for 100 Gbps - CFP2 InterfaceFeedbackAltera Corporation

6AN-6842013.03.29Board Stack Up DimensionsThe BGA pads, signal vias, and CFP2 trace to pad interfaces are large discontinuity sources in the channel.Ansoft HFSS ( High Frequency Structure Solver) 3-D field solver simulation is used to optimize the BGAbreakout and CFP2 interface design. The trace impedance is kept within 10% of the nominal 100ΩBoard Stack Up DimensionsThe detailed trace design and board stack up dimensions are shown in the figure below.Figure 7: Differential Trace Construction and Stack Up Details1SIG2PLANE3PLANE4SIG4.002.23.70R - 5,775 K0.64.00R - 5,775 K0.68.805SIGR - 5,775 K0.64.006PLANE7SIGR - 5,775 K0.64.80R - 5,775 K0.612.008SIGR - 5,775 K0.64.809PLANE10PLANER - 5,775 K0.63.200.63.7011PLANE12PLANE13SIGR - 5,775 K3.20R - 5,775 KR - 5,775 K0.6SIGR - 5,775 K0.64.80PLANE16SIGR - 5,775 K0.64.00Dk 3.460.610.7017SIGDk 3.560.64.0018PLANE19PLANE20SIGThickness over Copper 119.4 milsThickness over Solder Mask 121 mils0.612.0015R - 5,775 K0.64.8014R - 5,775 K0.6Dk 3.460.63.70R - 5,775 K0.64.002.2Dk 3.46Width 6.20 MilsSpace 11.80 milsBGA Breakout OptimizationBGA breakout optimization targets both the BGA pads and dog bone vias. A cutout is provided in thereference plane under the BGA pad and large oval via anti-pads are used for better BGA pad and via impedancematching.Altera CorporationDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedback

AN-6842013.03.29BGA Breakout Optimization7Figure 8: BGA Via Breakout Layout OptimizationCutout underBGA PadTX ChannelRX ChannelOval Via Anti-PadFigure 9: TDR of BGA Via BreakoutHFSS simulation results show that the TDR deviation of the BGA escape is maintained within 10% of thenominal 100Ω channel target impedance.Design Guidelines for 100 Gbps - CFP2 InterfaceFeedbackAltera Corporation

8AN-6842013.03.29CFP2 Interface OptimizationCFP2 Interface OptimizationThe CFP2 host connector layout optimization reduces the impact of discontinuity at the differential pair tothe CFP2 connector interface. A reference plane cutout is provided beneath the connector pads and largeroval anti-pads are used for the signal vias. Four nearby ground return vias are provided to help reduce theconnector interface discontinuity.Figure 10: CFP2 Connector Interface Layout OptimizationOval ViaAnti-PadsCutout Under CFP2Connector PadGND ReturnVias NearSignal ViaAltera CorporationDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedback

AN-6842013.03.29Example Design Channel Performance9Figure 11: HFSS Simulated TDR of the CFP2 Connector interfaceThe following figure shows the HFSS simulated TDR results. With the layout optimizations, the TDRdeviation due to the discontinuity caused by the via and connector pad is kept within 10% of the nominal100Ω target impedance.Example Design Channel PerformanceThe CEI-28G-VSR working clause defines several mask requirements for the channel, including insertionloss, return loss, and differential-to-common mode conversion. Because it is difficult to verify electricalparameters of a full channel in a system, the working clause also defines a Host Compliance Board (HCB)with test points for verifying the host-to-module channel performance at various test points.Figure 12: Host Compliance Board Measurement PointsTPOHost-to-ModuleTransmit FunctionHCB PCBHost PCB TraceTraceTPOaTP1aHost-to-ModuleReceive FunctionTP4aHost ChannelFor example, TP1a and TP4a define the measurement points and the associated mask requirements for thehost-to-module electrical signal performance for insertion loss, return loss, and differential-to-commonDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedbackAltera Corporation

10AN-6842013.03.29Simulation Results for Stratix V GT to CFP2 Connector Layout Designmode conversion. For more information about these definitions, refer to the CEI-28G-VSR working clausespecification (document number OIF2010.404.08).Simulation Results for Stratix V GT to CFP2 Connector Layout DesignSimulation results for the insertion loss (SDD21), return loss (SDD11) and differential-to-common modeconversion (SDC11) of the channel with the CFP2 connector included are shown in the following figures.The simulation models the HCB for validating the channel layout against the CEI-28G-VSR defined masks.Figure 13: Insertion Loss versus CEI-28G-VSR Mask RequirementsThe SDD21 resides within the HCB minimum and maximum insertion loss masks as defined by theCEI-28G-VSR specification. This insertion loss meets the complete VSR channel (host board connector optical module) mask requirement with ample margin to accommodate the additional loss of an insertedCFP2 optical module. Note that the complete channel with the optical module is not simulated.Similarly, the figures below show that the return loss and differential-to-common mode conversion bothmeet their respective masks as defined by the CEI-28G-VSR requirement.Altera CorporationDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedback

AN-6842013.03.29Simulation Results for Stratix V GT to CFP2 Connector Layout Design11Figure 14: Return Loss versus CEI-28G-VSR Mask RequirementsFigure 15: Mode Conversion versus CEI-28G-VSR Mask RequirementsDesign Guidelines for 100 Gbps - CFP2 InterfaceFeedbackAltera Corporation

12AN-6842013.03.29Document Revision HistoryDocument Revision HistoryTable 1: Document Revision HistoryDateMarch 2013Altera CorporationVersion2013.03.29ChangesInitial release.Design Guidelines for 100 Gbps - CFP2 InterfaceFeedback

Figure 14: Return Loss versus CEI-28G-VSR Mask Requirements Figure 15: Mode Conversion versus CEI-28G-VSR Mask Requirements Design Guidelines for 100 Gbps - CFP2 Interface Altera Corporation Feedback Simulation Results for Stratix

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