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VLSIUNIT - IINTRODUCTIONP.VIDYA SAGAR ( ASSOCIATE PROFESSOR)Department of Electronics and Communication Engineering, VBIT

contentsUNIT IINTRODUCTION: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOStechnologies.BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits:Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds, figure of merit ωo ; Pass transistor,NMOS Inverter, Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.2Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

A Brief History Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable 1947: first point contact transistor (3 terminal devices) 3Shockley, Bardeen and Brattain at Bell LabsDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

A Brief History, contd. 1958: First integrated circuit Flip-flop using two transistorsBuilt by Jack Kilby (Nobel Laureate) at Texas InstrumentsRobert Noyce (Fairchild) is also considered as a co-inventorKilby’s ICsmithsonianchips.si.edu/ augarten/4Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

MOS Integrated Circuits 1970’s processes usually had only nMOS transistors Inexpensive, but consume power while idle 1980s-present: CMOS processes for low idle power Intel 1101 256-bit SRAM5Intel 4004 4-bit ProcDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scaleTransistor counts have doubled every 26 months1,000,000,000Integration 0,00080286100,000Pentium 4Pentium IIIPentium IIPentium ProPentiumSSI:10 gatesMSI: 1000 751980198519901995200010,000 gatesVLSI: 10k ooreslaw/6Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

The First ComputerThe BabbageDifference Engine(1832)25,000 partscost: 17,4707Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

ENIAC - The first electronic computer (1946)8Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

WHY VLSI?Integration Improves the Design Lower parasitics, higher clocking speed Lower power Physically smallIntegration Reduces Manufacturing Costs (almost) no manual assembly About 1-5billion/fab Typical Fab 1 city block, a few hundred people Packaging is largest cost Testing is second largest cost9Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Design LevelsSYSTEM MODULEGATECIRCUITGSn 10DDEVICEn Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Moore’s Law 1965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scaleTransistor counts have doubled every 26 monthsHe predicted that the number of transistors on a chip would double about every18 sIntel4861,000,00080286100,000Pentium 4Pentium IIIPentium IIPentium 1197519801985199019952000YearDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

INTEGRADED CIRCUIT (IC):Multi terminal electronic device in whichdiscrete components liketransistors,resisters,capacitors are fabricated in a single construction process.Classification of ICs : Based on application -Analog , digital Based on complexity -SSI, MSI, LSI, VLSI Based on fabrication-Monolithic , hybrid Based on technology -RTL ,DTL, TTL, MOS.12Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

IC Evolution :13NameYearTransistors number Logic gates numbersmall-scale integration (SSI)19641 to 101 to 12medium-scale integration (MSI)196810 to 50013 to 99large-scale integration (LSI)1971500 to 20,000100 to 9,999very large scale integration (VLSI)198020,000 to 1,000,00010,000 to 99,999Ultra large scale integration (ULSI)19841,000,000 and more100,000 and moreDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Pentium 4 /online/hist micro/hof/index.htm14Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Modern transistors are few microns wide and approximately 0.1 micron or less in length Human hair is 80-90 microns in diameterRef: zematters.html15Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Metal-oxide-semiconductor (MOS) and related VLSI technology MOS (Metal-oxide-silicon) although invented before bipolar transistor, was initially difficult to manufacture nMOS (n-channel MOS) technology developed in 1970s required fewer masking steps,was denser, and consumed less power than equivalent bipolar Ics. CMOS (Complementary MOS): n-channel and p-channel MOS transistors lower power consumption, simplified fabrication process Bi-CMOS - hybrid Bipolar, CMOS (for high speed) GaAs - Gallium Arsenide (for high speed) Si-Ge - Silicon Germanium (for RF)16Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Mos transistors– Basic MOS transistors with the doping concentration of transistor two types of MOS transistorsare available as NMOS transistor and PMOS transistor. With their mode of operation further theyare classified as depletion mode transistor and enhancement mode transistor.nMOS enhancement mode transistor– nMOS devices are formed in a p-type substrate of moderate doping level. The source and drainregions are formed by diffusing n-type impurities through suitable masks into these areas.Thus source and drain are isolated from one another by two diodes and their Connections aremade by a deposited metal layer. The basic block diagrams of nMOS enhancement modetransistor is shown in figure.17Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS enhancement mode transistornMOS depletion mode transistor– The basic block diagram of nMOS depletion mode transistor is shown in figure. In depletion modetransistor the channel is established even the voltage Vgs 0 by implanting suitable impurities inthe region between source and drain during manufacture and prior to depositing the insulationand the gate.18Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

MOS Transistors– Four terminal device: gate, source,drain, bodyNMOSSourceGateDrainPolysiliconSiO 2– Gate – oxide – body stack looks like acapacitorp – Gate and body are conductors (bodyis also called the substrate)p nbulk Si– SiO2 (oxide) is a “good” insulator(separates the gate from the body– Called metal–oxide–semiconductor(MOS) capacitor, even though gate ismostly made of poly-crystallinesilicon (polysilicon)SourceGateDrainPolysiliconSiO 2n n pbulk SiPMOS19Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

MOS Capacitor Gate and body form MOS capacitor Operating modes Accumulationpolysilicon gatesilicon dioxide insulatorVg 0 Depletion -p-type body Inversion(a)0 V g Vt -depletion region(b)V g Vt -inversion regiondepletion region(c)20Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Terminal Voltages– Mode of operation depends on Vg, Vd, VsVg– Vgs Vg – Vs– Vds Vd – Vs Vgs - Vgd– Source and drain are symmetric diffusion terminals Vgd- Vgs-– Vgd Vg – VdVs-Vds Vd– By convention, source is terminal at lower voltage– Hence Vds 0– nMOS body is grounded. First assume source is 0 too.– Three regions of operation– Cutoff– Linear– Saturation21Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Cutoff– No channel– Ids 0Vgs 0 -g -sdn n Vgdp-type bodyb22Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Linear– Channel forms– Current flows from d to s– e- from s to d– Ids increases with VdsVgs Vt -– Similar to linear resistorg -sdn n Vgd VgsVds 0p-type bodybVgs Vt -gs dn n Vgs Vgd VtIds0 Vds Vgs-Vtp-type bodyb23Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Saturation– Channel pinches off– Ids independent of Vds– We say current saturates– Similar to current sourceVgs Vt -g -Vgd Vtd Idssn n Vds Vgs-Vtp-type bodyb24Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

I-V CharacteristicsNMOS:Vgs VtVds Vgs -VtVds Vgs – Vt25OFFLINEARSATURATIONPMOSVsg Vt Vsd Vsg – Vt Vsd Vsg – Vt Department of Electronics and Communication Engineering, VBITOFFLINEARSATURATIONVIDYA SAGAR P

CMOS26Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Structure: n-channel MOSFET(NMOS)body(bulk orBsubstrate)sourceSygate: metal or heavily doped poly-SiGdrainIG 0DID ISISmetaloxiden n pxL27WDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Channel Charge– MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel– Qchannel gateVgpolysilicongateWtoxn Ln SiO2 gate oxide(good insulator, ox 3.9) Cg Vgd drainsource VgsVsVdchannel n n Vdsp-type bodyp-type body28Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Channel Charge– MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel– Qchannel CV– C gateVgpolysilicongateWtoxn Ln SiO2 gate oxide(good insulator, ox 3.9) Cg Vgd drainsource VgsVsVdchannel n n Vdsp-type bodyp-type body29Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Channel Charge– MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel– Qchannel CV– C Cg oxWL/tox CoxWL– V Cox ox / toxgateVgpolysilicongateWtoxn Ln SiO2 gate oxide(good insulator, ox 3.9) Cg Vgd drainsource VgsVsVdchannel n n Vdsp-type bodyp-type body30Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Channel Charge– MOS structure looks like parallel plate capacitor while operating in inversion– Gate – oxide – channel– Qchannel CV– C Cg oxWL/tox CoxWL– V Vgc – Vt (Vgs – Vds/2) – VtCox ox / toxgateVgpolysilicongateWtoxn Ln SiO2 gate oxide(good insulator, ox 3.9) Cg Vgd drainsource VgsVsVdchannel n n Vdsp-type bodyp-type body31Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Carrier velocity– Charge is carried by e– Carrier velocity v proportional to lateral E-field between source and drain– v 32Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Carrier velocity– Charge is carried by e– Carrier velocity v proportional to lateral E-field between source and drain– v E called mobility– E 33Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Carrier velocity– Charge is carried by e– Carrier velocity v proportional to lateral E-field between source and drain– v E called mobility– E Vds/L– Time for carrier to cross channel:– t 34Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Carrier velocity– Charge is carried by e– Carrier velocity v proportional to lateral E-field between source and drain– v E called mobility– E Vds/L– Time for carrier to cross channel:– t L/v35Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Linear I-V– Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to crossI ds 36Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Linear I-V– Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to crossQchannelI ds t 37Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Linear I-V– Now we know– How much charge Qchannel is in the channel– How much time t each carrier takes to crossQchannelI ds tW CoxL V V Vds gs t2 V Vgs Vt ds Vds2 38 V ds W CoxLDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Saturation I-V– If Vgd Vt, channel pinches off near drain– When Vds Vdsat Vgs – Vt– Now drain voltage no longer increases currentI ds 39Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Saturation I-V– If Vgd Vt, channel pinches off near drain– When Vds Vdsat Vgs – Vt– Now drain voltage no longer increases currentVI ds Vgs Vt dsat Vdsat2 40Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS Saturation I-V– If Vgd Vt, channel pinches off near drain– When Vds Vdsat Vgs – Vt– Now drain voltage no longer increases currentVdsat I ds Vgs Vt 2 41 V 2gs Vt V dsat 2Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

nMOS I-V Summary– Shockley 1st order transistor models 0 VdsI ds Vgs Vt 2 2 Vgs Vt 242Vgs Vt V V V dsdsdsat Vds VdsatcutofflinearsaturationDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Transistors as Switches– We can view MOS transistors as electrically controlled switches– Voltage at gate controls path from source to draing 0dnMOSdsONsddgOFFONs43dOFFgspMOSdg 1sDepartment of Electronics and Communication Engineering, VBITsVIDYA SAGAR P

CMOS InverterAY0110VDDONA 0Y 1OFFAYGND44Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

CMOS NAND GateAB00011011YYAB45Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

CMOS NAND Gate46ABY001011011ONONY 1A 0B 0Department of Electronics and Communication Engineering, VBITOFFOFFVIDYA SAGAR P

CMOS NAND Gate47ABY0010111011OFFONY 1A 0B 1Department of Electronics and Communication Engineering, VBITOFFONVIDYA SAGAR P

CMOS NAND Gate48ABY00101110111ONA 1B 0Department of Electronics and Communication Engineering, VBITOFFY 1ONOFFVIDYA SAGAR P

CMOS NAND Gate49ABY001011101110OFFA 1B 1Department of Electronics and Communication Engineering, VBITOFFY 0ONONVIDYA SAGAR P

CMOS NOR Gate50ABY001010100110ABDepartment of Electronics and Communication Engineering, VBITYVIDYA SAGAR P

nMOS FABRICATION51Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

52Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Department of Electronics and Communication Engineering, VBIT

54Department of Electronics and Communication Engineering, VBITVIDYA SAGAR P

Pure silicon is melted in a pot (1400º C) and a small seed containing the desired crystalorientation is inserted in to molten silicon and slowly(1mm/minute) pulled out. The wafersare generally available in diameters of 150 mm, 200 mm, or 300 mm, and are mirror-polishedand rinsed before shipment from the wafer manufacturer.WaferFabricationDepartment of Electronics and Communication Engineering, VBIT

Oxidation It refers to the chemical process of silicon reacting with oxygen to form silicon dioxide, SiO2.Si O2 SiO2 The process can be classified as two types:Dry oxide: introduce high-purity gas. It gives better electrical characteristics.Wet oxide. Introduce water vapor.SiO2 is used to form insulator, capacitor, an effective maskagainst many impurities in SiO2 region, but allowing theintroduction of dopants into Si region. Thin oxide is usually grown using dry oxidationFig. Schematic of the Oxidation Process Thick oxide is usually grown using wet oxidationDry oxidation results in slower growth rate, but high density — higher breakdown voltage.Department of Electronics and Communication Engineering, VBIT

Oxidation– Grow SiO2 on top of Si wafer– 900 – 1200 C with H2O or O2 in oxidation furnaceSiO2p substrateDepartment of Electronics and Communication Engineering, VBIT

Diffusion It introduces impurity atoms (dopants) into silicon to change its resistivity. Dopant types:-p-type dopants: boron-n-type dopants: phosphorus and arsenic A pn junction (PN)- formed by diffusing p-type dopants into an n-type substrate. Diffusion of impurities is usually carried out at high temperatures (1000 to 1200 C) toobtain the desired doping profile. When the wafer is cooled to room temperature, theimpurities are essentially “frozen” in position.Department of Electronics and Communication Engineering, VBIT

Ion implantation An alternative process to replace diffusion--used to introduceimpurities into silicon. An ion implanter-produces ions of the desired impurity,accelerates them by an electric field,allows them to strike thesilicon surface. It is used for accurate control of the dopants.Department of Electronics and Communication Engineering, VBIT

Ion Implantationphosphorus(-) ionsFocusBeam trap andgate plateNeutral beam andbeam path gatedphotoresist maskfield oxiden-w ellp- epip-channel transistorp substrateNeutral beam trapand beam gateY - axisscannerDepartment of Electronics and Communication Engineering, VBITX - axisscannerWafer in waferprocess chamber

Photolithography1.Photoresist application: the surface to be patterned isspin-coated with a light-sensitive organic polymer called photoresist2.Printing (exposure):the mask pattern is developed on thephotoresist, with UV light exposure depending on the type ofphotoresist(negative or positive), the exposed or unexposed partsbecome resistant to certain types of solvents3.Development: the soluble photoresist is chemically removed Thedeveloped photoresist acts as a mask for patterning of underlyinglayers and then is removed.Department of Electronics and Communication Engineering, VBIT

Photolithographic istremoval(ashing)photoresist coatingphotoresistdevelopmentprocessstepspin, rinse,dry62acid etchDepartment of Electronics and Communication Engineering, VBITVIDYA SAGAR P

PhotolithographyExposure ProcessesDepartment of Electronics and Communication Engineering, VBIT

EtchingOnce the desired shape is patterned with photoresist,the etching process allows unprotected materials to beremoved Wet etching: uses chemicals Dry or plasma etching: uses ionized gasesDepartment of Electronics and Communication Engineering, VBIT

EtchCluster LoadlockGas InletRIE ChamberDie-electric EtchPlasma EtchWaferTransferChamberRF PowerExhaustDepartment of Electronics and Communication Engineering, VBIT

Chemical Vapor Deposition (CVD) To develop nitride films and polysilicon films, the chemical vapordeposition (CVD) method is used, in which a gaseous reactant is introducedto the silicon substrate, and chemical reaction produce the deposited layermaterial. The metallic layers used in the wiring of the circuit are also formed byCVD, spattering (PVD: physical vapor deposition)Department of Electronics and Communication Engineering, VBIT

Metallization Interconnecting the devices, such as transistors, formed on the silicon wafer completes thecircuit. the wafer is first covered with a thick and flat interlayer insulation film (oxide film).Next, contact holes are drilled by lithograph and etching, through the interlayer insulationfilm, above the devices to be connected. Many metal films used in IC fabrication aredeposited by sputtering. In the sputtering process, argon gas is excited by a high energy fieldto split up into positively charged argon ions and free electrons. An electric field attracts theargon ions toward a target made out of the material to be deposited. .Sputter process.Department of Electronics and Communication Engineering, VBIT

EncapsulationDuring Encap

Department of Electronics and Communication Engineering, VBIT IC Evolution : 13 VIDYA SAGAR P Name Year Transistors number Logic gates number small-scale integration (SSI) 1964 1 to 10 1 to 12 medium-scale integration (MSI) 1968 10 to 500 13 to 99 large-scale integration (LSI) 1971 500 to 20,000 100 to 9,999 very large scale integration

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