Very Large Scale Integration (VLSI)
Very Large Scale Integration(VLSI)Lecture 1Dr. Ahmed H. MadianAh madian@hotmail.comDr. Ahmed H. Madian-VLSI1
Course outline Overview of VLSITechnologies for Micro- and NanostructuresLow-Voltage and power designSynchronous and Asynchronous Circuit DesignArchitectures for VLSI ApplicationsTest and Measurement Techniques for VLSICircuitsDr. Ahmed H. Madian-VLSI2
What is VLSI? VLSI stands for (Very Large Scale Integratedcircuits)Craver Mead of Caltech pioneered the filed of VLSIin the 1970’s.Digital electronic integrated circuits could beviewed as a set of geometrical patterns on thesurface of a silicon chip.Complexity could thus be dealt with using theconcept of repeated patterns that were fittedtogether in structured manner.Dr. Ahmed H. Madian-VLSI3
VLSI History Jack Kilby, working at Texas Instruments, first dreamed up the idea of amonolithic “integrated circuit” in July 1959. By the end of the year, he hadconstructed several examples, including the flip-flop shown in the patentdrawing above. Components are connected by hand-soldered wires andisolated by “shaping” and pn diodes used as resistors.Dr. Ahmed H. Madian-VLSI4
VLSI History (cont.) 1961: TI and Fairchild introduced the first logic IC’s (cost 50 in quantity!). This is a dual flip-flop with 4 transistors.1963: Densities and yields are improving. This circuit hasfour flip flops.In 1970, making good on its promise to itsinvestors Intel starts selling a 1K bit RAM,the 1103.Dr. Ahmed H. Madian-VLSI5
VLSI History (cont.) Introduced in 1972, the 8008 had 3,500transistors supporting a byte-wide datapath. Despite its limitations, the 8008was the first microprocessor capable ofplaying the role of computer CPU asdemonstrated on the cover of the July‘74 issue of Radio-Electronics.Dr. Ahmed H. Madian-VLSI6
Today Many disciplines havecontributed to the currentVLSI designs: solid-state physicsmaterials sciencelithography and fabdevice modelingarchitecturealgorithmsCAD toolscircuit design & layoutDr. Ahmed H. Madian-VLSI7
Chip ComplexityChip classification according to number of active elements and minimal feature size:Dr. Ahmed H. Madian-VLSI8
VLSI Chip Types Full customEvery circuit is custom designedApplication-specific integrated circuits(ASICS) Design is created using astandard CAD tools without the need tointeract with the silicon structureSemi-customIn between of full-custom and ASIC-typecircuits. The majority of the chip is designedusing a primitive predefined cells (standardcells) from library as building blocks.Dr. Ahmed H. Madian-VLSI9
Top design levelDesignhierarchyoverviewbottom design levelSystem specificationsInitial conceptAbstract High-level modelVHDL, Verilog, HDLSystem designand verificationLogic synthesisLogic designand verificationCircuit designCMOS designand verificationphysical designManufacturingFinishedVLSIchipDr. Ahmed H.Madian-VLSISilicon logic designand verificationMass production,testing andpackagingMarketing10
Top design levelVLSIDesignbottom design levelSystem specificationsInitial conceptAbstract High-level modelVHDL, Verilog, HDLSystem designand verificationLogic synthesisLogic designand verificationCircuit designCMOS designand verificationphysical designManufacturingFinishedVLSIchipDr. Ahmed H.Madian-VLSISilicon logic designand verificationMass production,testing andpackagingMarketing11
Physical design CMOS ICs are electronic switchingnetworks that are created on small area ofsilicon wafer using complex set of physicaland chemical processes.A primary task for VLSI designer is totranslate circuit schematics into siliconform (this process is called physical design)Dr. Ahmed H. Madian-VLSI12
Design Examples VLSI Draw the CMOS realization and the layout oflogic functionf a b. c Colors of layerspolysilicon (gates): RedDoped n /p (active) : GreenN-Well: YellowMetal 1: BLUEMetal 2: GreyContacts: Black X’sDr. Ahmed H. Madian-VLSI13
CMOS RealizationVDDbcafbacDr. Ahmed H. Madian-VLSI14
Logic function LayoutVDDN-WellbPFETcP afbaNFETN cDr. Ahmed H. Madian-VLSI15
Logic function LayoutVDDVDDN-WellcPFETXbXbacXafbaNFETcDr. Ahmed H. Madian-VLSI16
Logic function LayoutVDDVDDN-WellbcPFETXXbaXcXafbfaNFETXXXcGNDDr. Ahmed H. Madian-VLSI17
Layout Rules Layout rules are the common language between design andprocess engineersconservative rules absorb process disturbances and variationslayout rules must be respected by the designerlayout rules reflect the limits of a process, they describe: minimal distance, overlapminimal width (e.x. channel length, λ)layout readability is improved using colors: ct, viablueredgreenyellowbrownblackDr. Ahmed H. Madian-VLSI18
LayoutDr. Ahmed H. Madian-VLSI19
Stick Diagram stick diagrams aretechnology independentno layout rules need tobe knownmask layout may begenerated automaticallyDr. Ahmed H. Madian-VLSI20
Digital Layout: horizontal or verticalgates? Vertical gates Good for circuits where fetssizes are similar and eachgate has limited fanout. Bestchoice for multiple input staticgates and for datapaths.Horizontal gates Good for circuits where long and shortfets are needed or where nodes mustcontrol many fets. Often used inmultiple-output complex gates (e.g,sum/carry circuits).Dr. Ahmed H. Madian-VLSI21
Eliminating GapsDr. Ahmed H. Madian-VLSI22
Complex CMOS Gates compactlayout. Euler Rule: Generate an n-graph by replacing the nfet blockwith vertices for nodes and edges for fetsGenerate a dual p-graphFind a sequence containing all edges in the ngraph. This sequence is called Euler n-path.Generate an Euler p-path with the same labelingas the Euler n-path. If not possible start again.The labeling sequence of the 2 Euler paths are thegate sequence of the single row nfet/pfet CMOSgate.Dr. Ahmed H. Madian-VLSI23
Example Draw the most compact layout for thefollowing logic function using Euler’s rule.F A.(B C)Dr. Ahmed H. Madian-VLSI24
SolutionVDDFACN1ABFAN2CN2VDDCN1BFBGNDGNDDr. Ahmed H. Madian-VLSIA B C25
Layout of ExampleA B CABCDr. Ahmed H. Madian-VLSI26
Design Rules Why we need design rules? We can specify the design rules using someconvenient units, e.g., microns but what happens ifwe want to manufacture the chip using differentmanufacturers? use an abstract unit, the lambda ( ), and scale the designto the appropriate actual dimensions when the chip is to bemanufactured.Each piece of fabrication equipment used in the ICmanufacturing process has limited accuracy.So, we need rules to ensure that the inaccuracy inthe fabrication will not result in malfunction IC.Dr. Ahmed H. Madian-VLSI27
Lambda Rule Design rules based on single parameter, λSimple for the designerWide acceptanceProvide feature size independent way of setting out maskIf design rules are obeyed, masks will produce workingcircuitsMinimum feature size is defined as 2 λUsed to preserve topological features on a chipPrevents shorting, opens, contacts from slipping out of areato be contactedDr. Ahmed H. Madian-VLSI28
Lambda-based Rules One lambda (λ) one half ofthe “minimum” maskdimension, typically the lengthof a transistor channel. Thiscan be used to derive designrules and to estimate minimumdimensions of a junction areaand perimeter before atransistor has to be laid out.Dr. Ahmed H. Madian-VLSI29
Lambda-based Rules, why? probably okay for retargeting between “similar”processes, e.g., when later process is a simple“shrink” of the earlier process. Some 0.35μmprocesses are shrinks of an earlier 0.5μm process.Can be useful for “fabless” semiconductorcompanies.most industrial designs use micron rules to getthe extra space efficiency. Cost of retargeting byhand is acceptable for a successful product, butusually it’s time for a redesign anyway.Dr. Ahmed H. Madian-VLSI30
Design Rules wpA set of geometrical specifications that dictate the design ofthe layout masks.It provides numerical values for minimum dimensions, linespacing, and other geometrical quantities that are derivedfrom the limits of a specific processing line.This rules must be followed to ensure functional structureson the fabricated chip.Poly (gate)Sp-pwpPoly (gate)Wp min. width of a polysiliconlineSp-p min. poly-to-poly spacingDr. Ahmed H. Madian-VLSI31
Design Rules Classified into four maintypes wpwpMin. width to avoid breaksMin. spacing to avoidshortsMin. surroundMin. extensionoxideActivecontactcutoxideSa-acN P-substrateoxideoxidePoly (gate)N Sp-pP-substratePoly (gate)Dr. Ahmed H. Madian-VLSI32
Design Rules Min. extension to ensurecomplete overlapsdpoDrain-sourceshortDr. Ahmed H. Madian-VLSI33
Design Rules (cont.) Most foundry allows submission of designs usingsimpler set of design rules that can be easily scaled todifferent processes.These are called “lambda design rules” that has unitsof µm.All distance and widths and spacing are written asvalue m , where m is scaling multiplier.for ex.: w 3 , s 4 If the factory will use technology 0.15 µmw 0.45 µm, s 0.6 µmDr. Ahmed H. Madian-VLSI34
Design Rules The masking sequence was established as: P-type substratenWellActivePolypSelectnSelectActive contactPoly contactMetal1ViaMetal2OverglassDr. Ahmed H. Madian-VLSI35
DR for N-Wells Required for pFET Snw-nwWnw-nwN-WellSnw-nwN-WellP-substratewnw-nwDr. Ahmed H. Madian-VLSIwnw-nw36
DR for Active Areas Silicon devices are built on active areas of thesubstrate FOXWa min width of active featureSa-a min. edge-to-edge spacing of active mask polygonActiveActiveSilicon substrateWaSa-aDr. Ahmed H. Madian-VLSI37
DR for Doped silicon (n ) FOXWa min width of an active areasa-n min. active-to-nSelect spacingActiveActiveN N Sa-nwaSilicon substrateSa-nDr. Ahmed H. Madian-VLSI38
DR for Doped silicon (P )Wa min width of an active areasa-p min. active-to-nSelect spacingSa-nw min. p to nWell spacing P SelectFOXSp-nwP SelectActivewaP N-wellSilicon substrateSa-nSa-nSp-nwDr. Ahmed H. Madian-VLSIActive39
MOSFETs MOSFET structure exists every time a poly gate line completelycrosses an n or p regionDRs for poly features are Wp min. poly width of a poly line dpo min. extension of poly beyond ActivePolywpLN Sp-pN N N N P substratedpoDr. Ahmed H. Madian-VLSI40
DR for Active contact Active contact is a cut in the oxide that allows the first layer ofmetal to contact as active n or p region. Sa-ac min. spacing between active and active contactdac,v vertical size of the contactdac,h horizontal size of the contactActive contactN P N-wellP-substrateSa-acdac,vdac,hDr. Ahmed H. Madian-VLSI41
DR for Metal1 Metal1 is applied to the wafer after oxide. It is used as interconnectfor signals and also for power supply distribution. Wm1 min. width of Metal1 lineSm1-ac min. spacing from Metal1 to Active ContactSm1-acMetal 1wm1N P-substrateDr. Ahmed H. Madian-VLSI42
DR Vias and higher level Metals Vias is a cut in the oxide layers to contact between twometals.wm2Metal2metal2dvViaMetal 1metal1Sv-m2Sv-m1N P-substrateSm2-m2Dr. Ahmed H. Madian-VLSIVia43
Layout Design Rules summaryDr. Ahmed H. Madian-VLSI
Layout Design Rules (cont.) Transistor dimensions are in W/L ratio NFETs are usually twice the width PFETs are usually twice the width of NFETs Holes move more slowly than electrons (must be wider to deliver samecurrent)Dr. Ahmed H. Madian-VLSI
Layout example3-input NANDDr. Ahmed H. Madian-VLSI46
VLSI layout libraryLayoutDr. Ahmed H. Madian-VLSI47
1st assignmentIt’s required to draw the layout of: Inverter 4 input NAND gate 4 input NOR gate 3 input XOR gateaccording to the Design rules given in the lecture due datenext lecture.(use layout tool submission will be soft copy and hardcopy)Dr. Ahmed H. Madian-VLSI48
Dr. Ahmed H. Madian-VLSI 3 What is VLSI? VLSI stands for (Very Large Scale Integrated circuits) Craver Mead of Caltech pioneered the filed of VLSI in the 1970’s. Digital electronic integrated circuits could be viewed as a set
VLSI Design 2 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
VLSI Fabrication Process Om prakash 5th sem ASCT, Bhopal omprakashsony@gmail.com Abstract VLSI stands for "Very Large Scale Integration". This is the field which involves packing more and more logic devices into smaller and smaller areas. Thanks to VLSI, circuits that would have
VLSI IC would imply digital VLSI ICs only and whenever we want to discuss about analog or mixed signal ICs it will be mentioned explicitly. Also, in this course the terms ICs and chips would mean VLSI ICs and chips. This course is concerned with algorithms required to automate the three steps “DESIGN-VERIFICATION-TEST” for Digital VLSI ICs.
VL2114 RF VLSI Design 3 0 0 3 VL2115 High Speed VLSI 3 0 0 3 VL2116 Magneto-electronics 3 0 0 3 VL2117 VLSI interconnects and its design techniques 3 0 0 3 VL2118 Digital HDL Design and Verification 3 0 0 3 VL2119* Computational Aspects of VLSI 3 0 0 3 VL2120* Computational Intelligence 3 0 0 3
Department of Electronics and Communication Engineering, VBIT IC Evolution : 13 VIDYA SAGAR P Name Year Transistors number Logic gates number small-scale integration (SSI) 1964 1 to 10 1 to 12 medium-scale integration (MSI) 1968 10 to 500 13 to 99 large-scale integration (LSI) 1971 500 to 20,000 100 to 9,999 very large scale integration
15A04604 VLSI DESIGN Course Objectives: To understand VLSI circuit design processes. To understand basic circuit concepts and designing Arithmetic Building Blocks. To have an overview of Low power VLSI. Course Outcomes: Complete Knowledge about Fabrication process of ICs Able to design VLSIcircuits as per specifications given.
55:131 Introduction to VLSI Design 10 . Simplified Sea of Gates Floorplan 55:131 Introduction to VLSI Design 11 . SoG and Gate Array Cell Layouts 55:131 Introduction to VLSI Design 12 . SoG and Gate Array 3-in NAND 55:131 Introdu
additif alimentaire ainsi que d’une nouvelle utilisation pour un additif alimentaire déjà permis. Les dispositions réglementaires pour les additifs alimentaires figurent à la partie B du titre 16 du RAD. L’article B.16.001 énumère les exigences relatives à l’étiquetage des additifs alimentaires. En particulier, l’article B.16.002 énumère la liste des critères qui doivent .
