Memory Testing And Built -In Self -Test
Chapter 8Memory Testing and Built-In Self-Test1EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 1
What is this chapter about? Basicconcepts of memory testing andBIST Memory fault models and test algorithms Memory fault simulation and testalgorithm generation RAMSES: fault simulator TAGS: test algorithm generator MemoryBIST BRAINS: BIST generator2EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 2
Typical RAM Production FlowWaferMarkingFinal TestFull Probe TestLaser RepairPost-BI TestBurn-In (BI)Visual InspectionQA Sample TestPackagingPre-BI TestShipping3EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 3
Off-Line Testing of RAMParametric Test: DC & AC Reliability Screening Long-cycle testing Burn-in: static & dynamic BI Functional Test Device characterization– Failure analysis Fault modeling– Simple but effective (accurate & realistic?) Test algorithm generation– Small number of test patterns (data backgrounds)– High fault coverage– Short test time4EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 4
DRAM Functional ModelRefreshAddressAddress latchRowdecoderColumn decoderMemorycellarraySense amplifiersData flowControl flowRefresh logicWrite driverData registerDataoutDatainRead/write&chip enable5EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 5
DRAM Functional Model Example6EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 6
Functional Fault ModelsClassical fault models are not sufficient torepresent all important failure modes in RAM. Sequential ATPG is not possible for RAM. Functional fault models are commonly usedfor memories: They define functional behavior of faultymemories. New fault models are being proposed tocover new defects and failures in modernmemories: New process technologies New devices7EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 7
Static RAM Fault Models: SAF/TF Stuck-At Fault (SAF) Cell (line) SA0 or SA1– A stuck-at fault (SAF) occurs when the value of a cell orline is always 0 (a stuck-at-0 fault) or always 1 (a stuckat-1 fault).– A test that detects all SAFs guarantees that from eachcell, a 0 and a 1 must be read. Transition Fault (TF) Cell fails to transit from 0 to 1 or 1 to 0 in specifiedtime period.– A cell has a transition fault (TF) if it fails to transit from 0to 1 (a /0 TF) or from 1 to 0 (a /1 TF).8EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 8
Static RAM Fault Models: AF Address-DecoderFault (AF) An address decoder fault (AF) is afunctional fault in the address decoder thatresults in one of four kinds of abnormalbehavior:– Given a certain address, no cell will beaccessed– A certain cell is never accessed by any address– Given a certain address, multiple cells areaccessed– A certain cell can be accessed by multipleaddresses9EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 9
Static RAM Fault Models: SOF Stuck-OpenFault (SOF) A stuck-open fault (SOF) occurs when thecell cannot be accessed due to, e.g., abroken word line. A read to this cell will produce thepreviously read value.10EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 10
RAM Fault Models: CF Coupling Fault (CF) A coupling fault (CF) between two cells occurswhen the logic value of a cell is influenced by thecontent of, or operation on, another cell. State Coupling Fault (CFst)– Coupled (victim) cell is forced to 0 or 1 if coupling(aggressor) cell is in given state. Inversion Coupling Fault (CFin)– Transition in coupling cell complements (inverts) coupledcell. Idempotent Coupling Fault (CFid)– Coupled cell is forced to 0 or 1 if coupling cell transitsfrom 0 to 1 or 1 to 0.11EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 11
Intra-Word & Inter-Word CFs12EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 12
RAM Fault Models: DF DisturbFault (DF) Victim cell forced to 0 or 1 if we(successively) read or write aggressor cell(may be the same cell):– Hammer test Read Disturb Fault (RDF)– There is a read disturb fault (RDF) if the cellvalue will flip when being read (successively).13EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 13
RAM Fault Models: DRF DataRetention Fault (DRF) DRAM– Refresh Fault– Leakage Fault SRAM– Leakage Fault Static Data Losses---defective pull-up14EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 14
Test Time Complexity c16G2.8m28m1.6h255d915cSize15EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 15
RAM Test Algorithm A test algorithm (or simply test) is a finitesequence of test elements: A test element contains a number of memoryoperations (access commands)– Data pattern (background) specified for the Read andWrite operation– Address (sequence) specified for the Read and Writeoperations A march test algorithm is a finite sequence ofmarch elements: A march element is specified by an address orderand a finite number of Read/Write operations16EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 16
March Test Notation : address sequence is in the ascendingorder : address changes in the descending order : address sequence is either or r: the Read operation Reading an expected 0 from a cell (r0); reading an expected1 from a cell (r1) w: the Write operation Writing a 0 into a cell (w0); writing a 1 into a cell (w1) Example (MATS ): {c (w0); (r0, w1); (r1, w0)}17EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 17
Classical Test Algorithms: MSCAN Zero-One Algorithm [Breuer & Friedman 1976] Also known as MSCAN SAF is detected if the address decoder is correct(not all AFs are covered):– Theorem: A test detects all AFs if it contains the marchelements (ra, ,wb) and (rb, ,wa), and the memoryis initialized to the proper value before each marchelement Solid background (pattern) Complexity is 4N{c ( w 0 ); c ( r 0 ); c ( w1); c ( r1)}18EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 18
Classical Test Algorithms: Checkerboard Checkerboard Algorithm Zero-one algorithm with checkerboard pattern Complexity is 4N Must create true physical checkerboard, notlogical checkerboard For SAF, DRF, shorts between cells, and half ofthe TFs– Not good for AFs, and some CFs cannot be detected1 0 10 1 01 0 119EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 19
Classical Test Algorithms: GALPAT Galloping Pattern (GALPAT) Complexity is 4N**2 only for characterization A strong test for most faults: all AFs, TFs, CFs, andSAFs are detected and located1. Write background 0;2. For BC 0 to N-1{ Complement BC;For OC 0 to N-1, OC ! BC;{ Read BC; Read OC; }Complement BC; }3. Write background 1;4. Repeat Step 2;BC20EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 20
Classical Test Algorithms: WALPAT Walking Pattern (WALPAT) Similar to GALPAT, except that BC is read onlyafter all others are read. Complexity is 2N**2.BC21EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 21
Classical Test Algorithms: Sliding Sliding (Galloping) Row/Column/Diagonal Based on GALPAT, but instead of shifting a 1through the memory, a complete diagonal of 1s isshifted:– The whole memory is read after each shift Detects all faults as GALPAT, except for some CFs Complexity is 4N**1.5.1111122EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 22
Classical Test Algorithms: Butterfly Butterfly Algorithm Complexity is 5NlogN All SAFs and some AFs are detected1. Write background 0;2. For BC 0 to N-1{ Complement BC; dist 1;While dist mdist /* mdist 0.5 col/row length */6{ Read cell @ dist north from BC;1Read cell @ dist east from BC;Read cell @ dist south from BC;945 ,1 0Read cell @ dist west from BC;3Read BC; dist * 2; }8Complement BC; }3. Write background 1; repeat Step 2;2723EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 23
Classical Test Algorithms: MOVI Moving Inversion (MOVI) Algorithm For functional and AC parametric test– Functional (13N): for AF, SAF, TF, and most CF{ (w0); (r0, w1, r1); (r1, w0, r0); (r0, w1, r1); (r1, w0, r0)}– Parametric (12NlogN): for Read access time 2 successive Reads @ 2 different addresses with differentdata for all 2-address sequences differing in 1 bit Repeat T2 T5 for each address bit GALPAT---all 2-address sequences24EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 24
Classical Test Algorithms: SD Surround Disturb Algorithm Examine how the cells in a row are affected whencomplementary data are written into adjacent cells ofneighboring rows. Designed on the premise that DRAM cells are mostsusceptible to interference from their nearest neighbors(eliminates global sensitivity checks).1. For each cell[p,q] /* row p and column q */{ Write 0 in cell[p,q-1];Write 0 in cell[p,q];Write 0 in cell[p,q 1];Write 1 in cell[p-1,q];Read 0 from cell[p,q 1];Write 1 in cell[p 1,q];Read 0 from cell[p,q-1];Read 0 from cell[p,q]; }2. Repeat Step 1 with complementary data;1000125EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 25
Simple March TestsZero-One (MSCAN) Modified Algorithmic Test Sequence (MATS) OR-type address decoder fault{c (w0);c (r0, w1);c (r1)} AND-type address decoder fault{c (w1);c (r1, w0);c (r0)} MATS For both OR- & AND-type AFs and SAFs The suggested test for unlinked SAFs{c ( w 0); ( r 0, w1); ( r1, w 0)}26EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 26
March Tests: Marching-1/0 Marching-1/0 Marching-1: begins by writing a background of 0s,then read and write back complement values (andread again to verify) for all cells (from cell 0 to n-1,and then from cell n-1 to 0), in 7N time Marching-0: follows exactly the same pattern, withthe data reversed For AF, SAF, and TF (but only part of the CFs) It is a complete test, i.e., all faults that should bedetected are covered It however is a redundant test, because only thefirst three march elements are necessary{ ( w0); ( r 0, w1, r1); ( r1, w0, r 0); ( w1); ( r1, w0, r 0); ( r 0, w1, r1)}27EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 27
March Tests: MATS MATS Also for AF, SAF, and TF Optimized marching-1/0 scheme—complete andirredundant Similar to MATS , but allow for the coverage of TFs The suggested test for unlinked SAFs & TFs{c ( w0); (r0, w1); (r1, w0, r0)}28EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 28
March Tests: March X/C March X Called March X because the test has been usedwithout being published For AF, SAF, TF, & CFin{c (w0); (r0, w1); (r1, w0);c (r0)} March C For AF, SAF, TF, & all CFs, but semi-optimal(redundant){c ( w0); (r0, w1); (r1, w0);c (r0); (r0, w1); (r1, w0);c (r0)}29EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 29
March Tests: March C March C Remove the redundancy in March C Also for AF, SAF, TF, & all CFs Optimal (irredundant){c(w0); (r0, w1); (r1, w0); (r0, w1); (r1, w0);c(r0)} Extended March C Covers SOF in addition to the above faults{c(w0); (r0, w1, r1); (r1, w0); (r0, w1); (r1, w0);c(r0)}30EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 30
Fault Detection Summary31EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 31
Comparison of March TestsSAFTFAFSOFCFinCFidCFstMATS March X March Y March Test Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 32
Word-Oriented Memory Aword-oriented memory hasRead/Write operations that access thememory cell array by a word instead ofa bit. Word-oriented memories can be testedby applying a bit-oriented test algorithmrepeatedly with a set of different databackgrounds: The repeating procedure multiplies thetesting time33EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 33
Testing Word-Oriented RAM Background bit is replaced by backgroundword MATS : {c (wa); (ra, wb); (rb, wa, ra)}Conventional method is to use logm 1different backgrounds for m-bit words Called standard backgrounds m 8: 00000000, 01010101, 00110011, and00001111 Apply the test algorithm logm 1 4 times, socomplexity is 4*6N/8 3NNote: b is the complement of a34EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 34
Cocktail-March Algorithms Motivation: Repeating the same algorithm for alllogm 1 backgrounds is redundant so far asintra-word coupling faults are concerned Different algorithms target different faults. Approaches:1. Use multiple backgrounds in a singlealgorithm run2. Merge and forge different algorithms andbackgrounds into a single algorithm Good for word-orientedRef:memoriesWu et al., IEEE TCAD, 04/0235EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 35
March-CW Algorithm: March C- for solid background (0000) Then a 5N March for each of other standardbackgrounds (0101, 0011): Results:{c (wa, wb, rb, wa, ra)} Complexity is (10 5logm)N, where m is word lengthand N is word count Test time is reduced by 39% if m 4, as comparedwith extended March C Improvement increases as m increasesRef: Wu et al., IEEE TCAD, 04/0236EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 36
Multi-Port Memory Fault Models CellFaults: Single cell faults: SAF, TF, RDF Two-cell coupling faults– Inversion coupling fault (CFin)– State coupling fault (CFst)– Idempotent coupling fault (CFid) PortFaults: Stuck-open fault (SOF) Address decoder fault (AF) Multi-port fault (MPF)37EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 37
2-Port RAM TopologyBLABLAWLAInterport WL shortWLABLABLA3WLB1WLBInterport BL t Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 38
Inter-Port Word-Line ShortFault-FreePort APort BAddress 1Address 2FaultyCell 1Address 1Cell 1Address 2Cell 2Address 3Cell 3Cell 2* Functional test complexity: O(N3)39EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 39
Inter-Port Bit-Line ShortFault-FreePort A Address αPort BAddress βFaultyAddress αCell αAddress βCell βAddress αCell αAddress βCell βCell αCell β* Functional test complexity: O(N2)40EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 40
Why Memory Fault Simulation?Fault coverage evaluation can be doneefficiently, especially when the number offault models is large. In addition to bit-oriented memories, wordoriented memories can be simulated easilyeven with multiple backgrounds. Test algorithm design and optimization canbe done in a much easier way. Detection of a test algorithm on unexpectedfaults can be discovered. Fault dictionary can be constructed for easydiagnosis. 41EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 41
Sequential Memory Fault Simulation Complexityis N**3 for 2-cell CFFor each fault/* N**2 for 2-cell CF */Inject fault;For each test element/* N for March */{Apply test element;Report error output;}42EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 42
Parallel Fault Simulation RAMSES [Wu, Huang, & Wu, DFT99 & IEEE TCAD 4/02] Each fault model has a fault descriptor# S/1AGR : w0SPT : @VTM : r0RCV : w1/* Single-cell fault */# CFst 0;s/1 AGR : v0SPT : */* All other cells are suspects */VTM : r0RCV : w143EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 43
RAMSES Complexityis N**2For each test operation{If op is AGR then mark victim cells;If op is RCV then release victim cells;If op is VTM then report error;}44EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 44
RAMSES Algorithm45EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 45
RAMSES Example for CFin ; 46EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 46
Coverage of March TestsSAFTFAFSOFCFinCFidCFstMATS March X March Y March C1111111111111.0021.002.75111.375.5.51.5.625.6251 Extended March C- has 100% coverage of SOF47EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 47
Test Algorithm Generation GoalsGiven a set of target fault models, generate atest with 100% fault coverage Given a set of target fault models and a testlength constraint, generate a test with thehighest fault coverage Priority setting for fault models Test length/test time can be reduced Diagnostic test generation Need longer test to distinguish faults48EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 48
Test Algorithm Generation by Simulation (TAGS) Marchtemplate abstraction: (w0); (r0,w1); (r1,w0,r0) (w) (r,w); (r,w,r)(w)(rw)(rwr)49EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 49
Template SetExhaustive generation: complexity is veryhigh, e.g., 6.7 million templates when N 9 Heuristics should be developed to selectuseful templates )(wr)(w)(w)(w)(wr)(w)(r)(w)(rw) .50EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 50
TAGS Procedure1.2.3.4.5.6.7.Initialize test length as 1N, T(1N) {(w)};Increase test length by 1N: apply generationoptions;Apply filter options;Assign address orders and databackgrounds;Fault simulation using RAMSES;Drop ineffective tests;Repeat 2-6 using the new template set untilconstraints met;51EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 51
Template Generation/Filtering Generation heuristics:(r) insertion( r), (r ) expansion(w) insertion( w), (w ) expansion Filteringheuristics: Consecutive read: ( rr ) Repeated read: (r)(r) Tailing single write: (w)52EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 52
TAGS Example (1/2) Target fault models (SAF, TF, AF, SOF, Cfin,Cfid, CFst), time constraints :53EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 53
TAGS Example (2/2)54EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 54
RAMSES Simulation Results55EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 55
FC Spectrum for 6N Tests56EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 56
Word-Oriented TAGS1.2.3.4.Construct bit-oriented test algorithmsGenerate initial Cocktail-March: Assign each data backgroundto the test in Step 1 a cascade of multiple March algorithmsOptimize the Cocktail-March (!P1) /* non-solid backgrounds */Optimize the Cocktail-March (P1) /* solid background */57EE141VLSITest Principles and ArchitecturesCh. 8 - Memory Testing & BIST - P. 57
3. Cocktail March Optimization (!P1)For each non-solid data background P (P ! P1)a) Generate a new Cocktail–March test byreplacing the March algorithm having P asits background with a shorter one from theset of algorithms generated in Step 1.b) Run RAMSES for the new Cocktail–March.c) Repeat 3(a) and 3(b) until the FC drops andcannot be recovered by any other testalgorithm of the same length.d) Store the test algorithm candidates used inthe previous step.58EE141VL
VLSI Test Principles and Architectures Ch. 8-Memory Testing &BIST -P. 8 Static RAM Fault Models: SAF/TF Stuck-At Fault (SAF) Cell (line) SA0 or SA1 – A stuck-at fault (SAF) occurs when the value of a cell or line is always 0 (a stuck-at-0 fault) or always 1 (a stuck-at-1 fault).
Memory Management Ideally programmers want memory that is o large o fast o non volatile o and cheap Memory hierarchy o small amount of fast, expensive memory -cache o some medium-speed, medium price main memory o gigabytes of slow, cheap disk storage Memory management tasks o Allocate and de-allocate memory for processes o Keep track of used memory and by whom
In memory of Paul Laliberte In memory of Raymond Proulx In memory of Robert G. Jones In memory of Jim Walsh In memory of Jay Kronan In memory of Beth Ann Findlen In memory of Richard L. Small, Jr. In memory of Amalia Phillips In honor of Volunteers (9) In honor of Andrew Dowgiert In memory of
The BlueNRG-LP embeds high-speed and flexible memory types: Flash memory of 256 kB, RAM memory of 64 kB, one-time-programmable (OTP) memory area of 1 kB, ROM memory of 7 kB. Direct data transfer between memory and peripherals and from memory-to-memory is supported by eight DMA channels with
Chapter 2 Memory Hierarchy Design 2 Introduction Goal: unlimited amount of memory with low latency Fast memory technology is more expensive per bit than slower memory –Use principle of locality (spatial and temporal) Solution: organize memory system into a hierarchy –Entire addressable memory space available in largest, slowest memory –Incrementally smaller and faster memories, each .
CMPS375 Class Notes (Chap06) Page 2 / 17 by Kuo-pao Yang 6.1 Memory 281 In this chapter we examine the various types of memory and how each is part of memory hierarchy system We then look at cache memory (a special high-speed memory) and a method that utilizes memory to its fullest by means of virtual memory implemented via paging.
An Introduction to Memory LO 1 Define memory. LO 2 Describe the processes of encoding, storage, and retrieval. Flow With It: Stages of Memory LO 3 Explain the stages of memory described by the information-processing model. LO 4 Describe sensory memory. LO 5 Summarize short-term memory. LO 6 Give examples of how we can use chunking to improve our memory span.
Memory -- Chapter 6 2 virtual memory, memory segmentation, paging and address translation. Introduction Memory lies at the heart of the stored-program computer (Von Neumann model) . In previous chapters, we studied the ways in which memory is accessed by various ISAs. In this chapter, we focus on memory organization or memory hierarchy systems.
21-07-2017 2 Chap. 12 Memory Organization Memory Organization 12-5 12-1 Memory Hierarchy Memory hierarchy in a computer system Main Memory: memory unit that communicates directly with the CPU (RAM) Auxiliary Memory: device that provide backup storage (Disk Drives) Cache Memory: special very-high-
