55:131 Introduction To VLSI Design - University Of Iowa
55:131Introduction to VLSI DesignImplementation OptionsAdapted from Weste and Harris notes
Implementation OptionsUse an existing chip Field Programmable Gate Array Sea of Gates/Gate Array Standard Cell Full Custom 55:131 Introduction to VLSI Design2
Implementation Options Use an existing chip Pros Minimal hardware development cost – hardware is “done”! Cons May need a (big) software development!Other features may not be a great fitBeware of performance limitationsBeware of power consumptionDon’t forget about other hardware (memories, PHYs, etc)Examples Off-the-shelf microprocessor Application Specific device55:131 Introduction to VLSI Design3
Applied Micro PPC460EXCourtesy of Applied Micro (APM)55:131 Introduction to VLSI Design4
Implementation Options FPGAs or PLDs Pros Back-end (fabrication) is done Saves time and money Cons Clock rate usually won’t match that of a Gate Array/Std Cell Usually has higher recurring cost “Fixed” feature set (RAM, PLLs, etc) may limit your options Examples RAM-based FPGA from Xilinx or Altera Flash-based FPGA from Actel55:131 Introduction to VLSI Design5
Simplified FPGA Floorplan55:131 Introduction to VLSI Design6
“Configured” FPGA55:131 Introduction to VLSI Design7
Xilinx CLB – a.k.a. “Slice”55:131 Introduction to VLSI Design8
4-input Look-up Table ImplementationIn0In1In216SRAMCellsIn3Out Out f (in0, in1, in2, in3)55:131 Introduction to VLSI Design9
Implementation Options Sea of Gates/Gate Array Pros Much of the fabrication is done Base wafers have transistors and memories done “User”-defined logic implemented in (a few) metal layers Lower development costs than Standard Cell because suppliercan amortize mask costs over all base array designs Better clock rate and lower power than FPGA Cons Clock rate usually won’t match that of a Std Cell “Fixed” feature set (RAM, PLLs, etc) may limit your options Examples LSI Logic LCA500K55:131 Introduction to VLSI Design10
Simplified Sea of Gates Floorplan55:131 Introduction to VLSI Design11
SoG and Gate Array Cell Layouts55:131 Introduction to VLSI Design12
SoG and Gate Array 3-in NAND55:131 Introduction to VLSI Design13
Implementation Options Standard Cell Pros Smaller, faster, lower power than FPGA or SoG/GA Faster development time than full custom because a standardcell library is used as the basic building blocks of the design Cons Custom mask set is expensive Resistance to add library elements Economical only for High volume or High cost devices Examples AMIS SC13 standard cell55:131 Introduction to VLSI Design14
Standard Cell Layout55:131 Introduction to VLSI Design15
Standard Cell Library Example55:131 Introduction to VLSI Design16
Implementation Options Full Custom Pros Custom design at the physical level Smallest, fastest, or lowest power circuit You get exactly what you want Or are capable of designing! Cons Design at physical level! Custom mask set is expensive Economical only for High volume or High cost devices Examples Microprocessor datapath, cache, IO cell55:131 Introduction to VLSI Design17
Custom Design Flow55:131 Introduction to VLSI Design18
CMOS Design Methods55:131 Introduction to VLSI Design19
55:131 Introduction to VLSI Design 10 . Simplified Sea of Gates Floorplan 55:131 Introduction to VLSI Design 11 . SoG and Gate Array Cell Layouts 55:131 Introduction to VLSI Design 12 . SoG and Gate Array 3-in NAND 55:131 Introdu
VLSI Design 2 Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.
VLSI IC would imply digital VLSI ICs only and whenever we want to discuss about analog or mixed signal ICs it will be mentioned explicitly. Also, in this course the terms ICs and chips would mean VLSI ICs and chips. This course is concerned with algorithms required to automate the three steps “DESIGN-VERIFICATION-TEST” for Digital VLSI ICs.
VL2114 RF VLSI Design 3 0 0 3 VL2115 High Speed VLSI 3 0 0 3 VL2116 Magneto-electronics 3 0 0 3 VL2117 VLSI interconnects and its design techniques 3 0 0 3 VL2118 Digital HDL Design and Verification 3 0 0 3 VL2119* Computational Aspects of VLSI 3 0 0 3 VL2120* Computational Intelligence 3 0 0 3
Dr. Ahmed H. Madian-VLSI 3 What is VLSI? VLSI stands for (Very Large Scale Integrated circuits) Craver Mead of Caltech pioneered the filed of VLSI in the 1970’s. Digital electronic integrated circuits could be viewed as a set
Principles of VLSI Design Introduction CMPE 315 Principles of VLSI Design Instructor Chintan Patel (Contact using email: cpatel2@cs.umbc.edu). Text CMOS VLSI Design: A Circuits and Systems Perspective, Third Edition. by Neil H.E. Weste and David Harris. ISBN: 0-321-14901-7, Addison Wesl
131 EMMOTT JP EE 101666 AA LAN Targets: 79 84 163 131 GIBBS AP EE 82084 A SUF Targets: 87 76 163 131 GREEN R EE 123409 AA KEN Targets: 78 85 163 131 Hodgkinson K EE 104418 AA STA Targets: 80 83 163 131 SUNDSTROM R EE 131282 B ROW Targets: 81 82 163 131 TOWNSEND FC EE 93880 AAA OXO Targets
15A04604 VLSI DESIGN Course Objectives: To understand VLSI circuit design processes. To understand basic circuit concepts and designing Arithmetic Building Blocks. To have an overview of Low power VLSI. Course Outcomes: Complete Knowledge about Fabrication process of ICs Able to design VLSIcircuits as per specifications given.
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