3D VLSI: Next Generation 3D Integration Technology

3D VLSI: Next Generation3D Integration TechnologyKarim ArabiVice President, R&D 2014 QUALCOMM Technologies, Inc. All rights reserved. Qualcomm, is a trademark of QUALCOMM Incorporated, registered in the United Statesand other countries.

Continued smartphone momentumWorld’s largest technology platform 8BCumulative smartphoneunit shipments forecastbetween 2014-2018Source: Gartner, Sept ‘13(c) 2015 Qualcomm Technologies, Inc.2

Mobile scaleCumulative global unit shipments, 2013–2017Smartphones& Tablets PCsAudio systemsVehiclesBlu-ray disc playersDigital media adaptersDigital camerasDigital video recordersGame consolesPortable game consolesFlat-panel TVsPortable media playersSet-top-boxesSources: Smartphones, tablets and PCs: Gartner, Sep. ‘13; Vehicles: ABI, Apr. 2013; All others: Strategy Analytics, Mar. ‘13(c) 2015 Qualcomm Technologies, Inc.3

Cloud and Mobile ComputingBig Dataand abundantcomputing powerare pushingcomputing to theCloudInstant Datagenerated by sensorsand users are pushingcomputing to theEdge(c) 2015 Qualcomm Technologies, Inc.4

Power EfficiencyMobile Heterogeneous Compute Units to Lower PowerNeural Processing Unit(NPU)CustomAcceleratorsGPU&DSPKey Drivers Mobile Computing Cloud Computing Big Data Analytic Deep Learning Machine LearningVeNumVeNumCPUCPUL2CPUVeNumCPUVeNumHigh Flexibility(c) 2015 Qualcomm Technologies, Inc.5

CMOS Scaling Outlook – The Roadmap Ahead20122013Technology 20nm1.0/0.9V0.5VTransistor Planar/Tri-gate,Si /GePlanar bulk RMG20215nm0.6VFinFET/NanowireSiGe/Ge/ III-V?Tunnel FETSiGe/Ge/III-V?FinFET III-V channelNanowire, vertical?Nanowire, horizontalTunnel FET, vertical?FinFET Si/SiGe/Ge channelTri-gate, FinFET Si(c) 2015 Qualcomm Technologies,6 Inc.

CMOS Scaling Outlook – The Roadmap AheadPotential Issues to Address for 7nm and Beyond:- FinFET/NWFET self-heating (phonon confinement)- Feasibility of TFET and vertical channel devices- System performance degradation (contact/BEOL bottleneck)More MooreThe 3rd Dimension Nano-wire TFET Ge/III-V 3DVLSI (3DV) MRAM &RRAM(c) 2015 Qualcomm Technologies,7 Inc.

QUALCOMM RESEARCHIntroduction: TSV-based 3D ICs TSV-based 3D ICs are close to marketTSMC (ISPD 2014)IBM (VLSI 2011) TSV-based 3D ICs shortens the interconnects, still quite large (5-10um,C 10-30fF)Courtesy Panth et al., ISLPED’148

QUALCOMM RESEARCH3D VLSI - An Emerging 3D TechnologyVertical viaGateHigh quality thin silicon(single crystal)3D VLSI SRAMSamsung (2010)3D VLSI for generallogic LETI (2011)Courtesy Panth et al., ISLPED’149

QUALCOMM RESEARCH3D VLSI: Face-to-Back Fabrication ProcessBottom tier is created as usualThin Si layer is attachedFabricate top-tier devices interconnectsCourtesy Panth et al., ISLPED’1410

QUALCOMM RESEARCH3D VLSI: Face-to-Face Fabrication Process11

QUALCOMM RESEARCHDesign Styles Available in 3D VLSI (1/2) Transistor-level [1]MIV NORINVNOR Each standard cell is folded Pin density increases significantly Footprint reduction is 40%, not 50% Standard cell re-design required CELONCEL [2] Gate-level, but cell redesign required Simplified design flow Same disadvantages as transistor-level[1] Y.-J. Lee, D. Limbrick and S. K. Lim, “Power Benefit Study for Ultra-High Density Transistor-Level Monolithic 3D ICs,” DAC, 2013.[2] S Bobba et al., “CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits,” ASPDAC, 2011.Courtesy Panth et al., ISLPED’1412

QUALCOMM RESEARCHDesign Styles Available in 3D VLSI (2/2) Block-level [1] Functional blocks are 2D & they arefloorplanned on to a 3D space Reuse of IP Does not fully take advantage of the highdensity offered by M3DBlockBulkINVNAND Gate-level Use existing standard cells & place them in 3D Reuse of cellsBulk[1] S. Panth et al. "Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations", DAC, 2014.Courtesy Panth et al., ISLPED’1413

Block-Level 3D VLSIPhysical Implementation14

QUALCOMM RESEARCHSequential 3D: Source of Inter-Tier Performance Variation FEOL processing of top tier RTA at 1200C will damage bothdevices and interconnects Process improvement: 625C without performance loss still too high for Cuinterconnect Preventing damage to interconnects – Two options: Use Tungsten (W) on the bottom tier Worse interconnects on bottom tier– Identical devices on both tiers 450C processing on the top tier Worse transistors on the top tier– Identical interconnects on both tiersCourtesy Panth et al., DAC’1415

QUALCOMM RESEARCHDegraded Transistors PMOS worsens by 27.8% and NMOS worsen by 16.2% (TTm20p corner)Change in delays of select standard 20pDFFTT WIdentical devices, butW interconnect[1] Low Thermal Budget Processing for Sequential 3D IC Fabrication, Rajendran et al., TED, 2007Courtesy Panth et al., DAC’1416

QUALCOMM RESEARCHDesign FlowRTLSynthesisFloorplanningVertical Via PlanningDerive WLMP&R of all blocks/tiersFeedback loopGDSII3D Timing and PowerAnalysisCourtesy Panth et al., DAC’14Determine the block outlinesin a 3D spaceDetermine block pin andvertical via locationsFinal signoff analysis17

QUALCOMM RESEARCHVariation-Aware 3D Block-Level FloorplanningBlock Timing ConstraintsNormal/Degraded LibrariesBlock RTLCu/W WLMBlock SynthesisTTTTm10pTT WTTm20pPerturb Solution3D Move ?Block flavorsPerformance-aware floorplannerNoYesUpdate Block Areaand Delay CostCourtesy Panth et al., DAC’1418

QUALCOMM RESEARCHPower-Performance Study: Identical Tier Performancedes3 benchmarkM3D closes 37% ofthe performance gapto idealM3D closes 41% of thepower gap to ideal Ideal: Zero RC for inter-block nets: Best possible block-level implementationCourtesy Panth et al., DAC’1419

QUALCOMM RESEARCHPower-Performance Study: Identical Tier Performance#Vertical Via 3,750#Vertical Via 13,460#Vertical Via 7,261 Similar results for all benchmarks 3D closes the power gap to ideal by at least 40% 3D closes the performance gap to ideal by up to 50% and 40% on averageCourtesy Panth et al., DAC’1420

QUALCOMM RESEARCHVariation-Aware Power-Performance Results Dashed lines no variation-aware floorplanning Solid lines variation-aware floorplanningCourtesy Panth et al., DAC’1421

QUALCOMM RESEARCHVariation-Aware Power-Performance Results Variation-aware floorplanning always gives better results W on the bottom tier seems to be the best optionCourtesy Panth et al., DAC’1422

QUALCOMM RESEARCHSummary of .950.97411.031.1551.051.0581.10.9711.151.0363D closes a significantportion of the gap to idealIso-power quency 0.70.8830.80.7160.90.931W interconnects havemarginal urtesy Panth et al., DAC’14mul12823

Gate-Level 3D VLSIPhysical Implementation24

QUALCOMM RESEARCHInitial Work in Gate-level 3D VLSI Placement-driven partitioning using academic placers [1]First, make the 3D footprint 50% of 2DPartitioning binIn a 2D placer, double the placementcapacity of each global bin (for two-tier)Partition the design, maintaining local areabalance within each partitioning bin“Placement-driven Partitioning”[1] S. Panth et. al., "Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs“, ISPD, 2014.Courtesy Panth et al., ISLPED’1425

QUALCOMM RESEARCH“Shrunk 2D” Placement using a Commercial Tool In a commercial tool, we cannot “double” the supply. Instead, we first halve the std. cell areas (multiply W/H by 0.707)Original 2DStd. CellsShrunk 2DStd. CellsNote: We do not touch the .lib file Timing information is maintainedW 0.707 * W2DShrunk 2D PlacementCell ExpansionPlacement-driven PartitioningCourtesy Panth et al., ISLPED’1426

QUALCOMM RESEARCHHandling Memory Macros: Issues Memory is usually pre-placed before placement startsTier 0Tier 1 We cannot simply superimpose them before feeding it to the commercialtool for shrunk 2D P&RThis will cause a placement blockage in theseregions, which is wrongShrunk 2D FootprintCourtesy Panth et al., ISLPED’1427

QUALCOMM RESEARCHHandling Memory Macros: Decomposition Memory macros can be thought of as a combination of a placementblockage and memory pins If we can isolate each component, then they can be handled separatelyduring shrunk 2D P&RCourtesy Panth et al., ISLPED’1428

QUALCOMM RESEARCHHandling Memory Placement Blockages (1/2) Consider the two memory regions overlapping as shown earlierThis region has memory inboth tiersThese regions have memory inone tier only The other tiercan contain cellsAfter partitioning, neithertier will contain cellsIf the target density 70% in thefinal 3D design, we set the maxdensity of these regions 35%( 70% once cells are expandedback to original area)Therefore, it will be a fullplacement blockage in theshrunk 2D footprintThis can be achieved by creatinga partial placement blockage inthese areasCourtesy Panth et al., ISLPED’1429

QUALCOMM RESEARCHHandling Memory Placement Blockages (2/2)Pre-Placed MemoryTier 0Projected MemoryLocationsMemory ProjectionFull BlockagePartial BlockageMemory Blockage ExtractionTier 1Pre-placed MemoryCourtesy Panth et al., ISLPED’1430

QUALCOMM RESEARCHDesign Flow ScreenshotsTier 0Reduced Placement Densityover partial blockagesFullBlockageMemory PinsTier 1PartialBlockageMemory ProjectionShrunk 2D P&RTier PartitioningPre-Placed MemoryCourtesy Panth et al., ISLPED’1431

QUALCOMM RESEARCHDesign FlowShrunk 2DPlacementTier PartitioningPre-CTS OptimizationMIV/F2F InsertionCTSTier-by-tier RoutePost-CTS OptimizationTier-by-tier RC ExtractionRouting3D Timing & Power AnalysisPost-route OptimizationCourtesy Panth et al., ISLPED’1432

QUALCOMM RESEARCHMatching Wire Parasitics between Shrunk 2D and 3D Consider two cells connected to each other in Shrunk 2D & then in 3DLS2D Lx LyL3D Lx Ly LMIV But LMIV 1um. Therefore LS2D L3D However, the wire widths are different; WS2D 0.707 W3D Since we want RS2D R3D and CS2D C3D, we do not scale the per-unitlength RC values in the cap table file for shrunk 2D design.Courtesy Panth et al., ISLPED’1433

QUALCOMM RESEARCHVertical Via Insertion (Face-to-Back) Trick the commercial router into inserting MIVs for us [1]Routing blockageto prevent MIVinsertionLEF files are modified for 3DRoute with EncounterAll gates are then placed in the same placement layerCreate separate verilog/DEF for each tier[1] S. Panth et. Al., "Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs", ISPD 2014.Courtesy Panth et al., ISLPED’1434

QUALCOMM RESEARCHVertical Via Insertion (Face-to-Face)LEF files are modified for 3DReverse the order ofmetals in Tier 0All gates are then placed in the same placement layerDo not add any routingblockage to prevent F2Finsertion over cellsCourtesy Panth et al., ISLPED’1435

QUALCOMM RESEARCHF2B / F2F MIV Insertion ScreenshotsF2B MIVF2F MIVCourtesy Panth et al., ISLPED’1436

QUALCOMM RESEARCHSingle vs. Multiple MIV Insertion: Screenshots Conventional 3D flows have a tier-by-tier optimization step It is very difficult to derive timing budgets for multiple MIVs per net Shrunk 2D flow enables multiple MIV insertion Lower WL and powerSingle MIV InsertionTier0Tier0Multiple MIV InsertionMultiple MIVsSingle 3D connectionTier1Tier1Courtesy Panth et al., ISLPED’1437

QUALCOMM RESEARCHSingle vs. Multiple Vertical Via Insertion: ResultsF2B 3DF2F 3DSingleMultipleSingleMultipleTotal WL (m)15.6114.29 (-8.43%)15.4413.89 (-10.05%)#MIV/F2F106k235k ( 120.44%)106k202k ( 89.72%)Total Power (mW)534.10522.10 (-2.25%)538.30524.00 (-2.66%)Cell Power (mW)126.90126.10 (-0.63%)127.30126.40 (-0.71%)Net Power (mW)293.90282.70 (-3.81%)297.80284.30 (-4.53%)Leak. Power (mW)113.30113.30 ( 0.0%)113.30113.30 (0.00)Courtesy Panth et al., ISLPED’1438

QUALCOMM RESEARCH3D Clock-Tree SynthesisClock BufferTier 0Clock gateTier 03D NetTier 0Tier 1Tier 0 Tier 1Flip-flopTraditional 3D CTS: Source-levelProposed 3D CTS: Leaf-levelOne clock-tree per clock-gating groupin each tier, tied together at the rootlevelKeep the entire backbone on one tier.Only insert clock MIVs to connect theFF on different tiers at the leaf levelCourtesy Panth et al., ISLPED’1439