NAND Flash And Mobile LPDRAM
Preliminary‡152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPFeaturesNAND Flash and Mobile LPDRAM152-Ball Package-on-Package (PoP)Combination Memory (TI OMAP )MT29C FamilyCurrent production part numbers: See Table 1 on page 3FeaturesFigure 1: Micron NAND Flash and Mobile LPDRAMcomponents RoHS-compliant, “green” package Separate NAND Flash and Mobile LPDRAMinterfaces Space-saving package-on-package combination Low-voltage operation (1.70–1.95V) Industrial temperature range: –40 C to 85 CPoP Block DiagramNAND FlashPowerNAND FlashDeviceNAND FlashInterfaceLP-DRAMDeviceLP-DRAM InterfaceNAND Flash-Specific Features Organization– Page sizex8: 2112 bytes (2048 64 bytes)x16: 1056 words (1024 32 words)– Block size: 64 pages (128K 4K bytes)LP-DRAM PowerMobile LPDRAM-Specific Features No external voltage reference requiredNo minimum clock rate requirement1.8V LVCMOS-compatible inputsProgrammable burst lengthsPartial-array self refresh (PASR)Deep power-down (DPD) modeSelectable output drive strengthSTATUS REGISTER READ (SRR) supported1Options LP-DRAM166 MHz CL32133 MHz CL3Marking-6-75Notes: 1. Contact factory for remapped SRR output.2. CL CAS (READ) latency.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN1Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change byMicron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPPart Numbering Information – 152-Ball PoPPart Numbering Information – 152-Ball PoPMicron NAND Flash and LPDRAM devices are available in different configurations anddensities.Figure 2:152-Ball Part Number ChartMT 29C 1G 24MACJACG–xITESProduction StatusMicron TechnologyBlank ProductionProduct FamilyES Engineering sample29C NAND LPDRAM MCPMS Mechanical sampleNAND DensityOperating Temperature Range1G 1GbIT Industrial (–40 to 85 C)2G 2GbLPDRAM Self Refresh Current4G 4GbBlank StandardLPDRAM Density12M 512Mb24M 1024MbLPDRAM Access Time48M 2048Mb–6 166 MHz CL3–75 133 MHz CL3Operating Voltage RangePackage CodesA 1.8V (1.70–1.95V)CA 152-ball PoP VFBGA (14 x 14 x 0.9mm)CG 152-ball PoP VFBGA (14 x 14 x 1.0mm)NAND Flash 82GbSecondKx162GbSecondNx84GbFirstPx164GbJQ 152-ball PoP TFBGA (14 x 14 x 1.1mm)GenerationChip CountFirstUx81GbSecondVx161GbSecondLPDRAM Configuration1, 11 NAND, 1 DRAM1GbFirstB1, 12 NAND, 1 DRAMx321GbFirstC1, 21 NAND, 2 DRAMDDRx16512MbSecondD1, 22 NAND, 2 DRAMDDRx32512MbSecondDensityJDDRx16LDDRNRPDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 ENChip CountAWidthNote:CE#, CS#GenerationTypeNot all possible combinations are available. Contact factory for availability.2Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPDevice MarkingTable 1:Production Part NumbersPart NumberMT29C4G48MAPLCCA-6 ITMT29C4G48MAPLCCA-75 ITMT29C4G48MAPLCJQ-6 ITMT29C4G48MAPLCJQ-75 ITMT29C1G12MADRACG-6 ITMT29C1G12MADRACG-75 ITMT29C2G24MAKLACG-6 ITMT29C2G24MAKLACG-75 ITMT29C1G12MAURACA-6 ITMT29C1G12MAURACA-75 ITMT29C1G12MAVRACA-6 ITMT29C1G12MAVRACA-75 ITNAND ProductLPDDR ProductPhysical PartMarkingMT46H32M32LFJG-6 ITMT46H32M32LFJG-6 ITMT46H32M32LFJG-6 ITMT46H32M32LFJG-6 ITMT46H16M32LFCM-6 ITMT46H16M32LFCM-6 ITMT46H32M32LFJG-6 ITMT46H32M32LFJG-6 ITMT46H16M32LFCM-6 ITMT46H16M32LFCM-6 ITMT46H16M32LFCM-6 ITMT46H16M32LFCM-6 5JW384JW375JW374Device MarkingDue to the size of the package, the Micron-standard part number is not printed on thetop of the device. Instead, an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are cross-referenced to the Micronpart numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder. Toview the location of the abbreviated mark on the device, refer to customer service noteCSN-11, “Product Mark/Label,” at www.micron.com/csn.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN3Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPGeneral DescriptionGeneral DescriptionMicron package-on-package (PoP) products combine NAND Flash and Mobile LPDRAMdevices in a single MCP. These products target mobile applications with low-power,high-performance, and minimal package-footprint design requirements. The NANDFlash and Mobile LPDRAM devices are also members of the Micron discrete memoryproducts portfolio.The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (noshared address, control, data, or power balls). This bus architecture supports an optimized interface to processors with separate NAND Flash and Mobile LPDRAM buses.The NAND Flash and Mobile LPDRAM devices have separate core power connectionsand share a common ground (i.e., VSS is tied together on the two devices).The bus architecture of this device also supports separate NAND Flash and MobileLPDRAM functionality without concern for device interaction. Operational characteristics for the NAND Flash and Mobile LPDRAM devices are found in the standard Microndata sheets for each of the discrete devices.For device specifications and complete Micron NAND Flash features documentation,please refer to the component data sheet at www.micron.com/products/nand, or contact your local Micron sales office.For device specifications and complete Mobile LPDRAM features documentation,please refer to the component data sheet at www.micron.com/products/mobiledram, orcontact your local Micron sales office.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN4Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPBall Assignments and DescriptionsBall Assignments and DescriptionsFigure 3:152-Ball VFBGA Ball Assignments (NAND x8; LPDDR DQ0DQ9 DQ10CK#VSSQ UDQSCVSSQDTop View – Ball DownNote:PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN1516VDDQ DQ13 DQ12NANDVDDDQ15 DQ14LPDDRSupplyGroundContact factory for availability of x16 LPDDR configuration.5Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPBall Assignments and DescriptionsFigure 4:152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32)67891011172021VDDQ DQ21 DQ20 DM3 DQS3NCNCADQ23 DQ22 DQDM1 DQ13 DQ15BNCNCDQ6DQ7CVSSQDQS0DQ24 DQ26CDDQ3DQ5DQ25 DQ29DEDQ0DQ1DQ27 VSSA7A6MNI/O10VCCA8A11NPI/O12 71819202145VDDQDQ9VSSQDQ10 DQ12 DQ16 DQ19DQ14 DQS1 DQ11DQ8DQ17 DQ18Top View(Ball Down)PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN6NAND16VDDLP-DRAMSupplyGroundMicron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPBall Assignments and DescriptionsTable 2:x8/x16 NAND Ball DescriptionsSymbolTypeALEInputCE1#, CSupplyDescriptionAddress latch enable: When ALE is HIGH, addresses can be transferred to the on-chip addressregister.Chip enable: Gates transfers between the host system and the NAND Flash device.Command latch enable: When CLE is HIGH, commands can be transferred to the on-chipcommand register.When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCKLOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).Read enable: Gates information from the NAND device to the host system.Write enable: Gates information from the host system to the NAND device.Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information.Data is output only during READ operations; at other times the I/Os are inputs.I/O[15:8] are RFU1 for NAND x8 devices.Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is inprogress.VCC: NAND power supply.Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.Contact the factory for details.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN7Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPBall Assignments and DescriptionsTable 3:x16/x32 LPDDR Ball DescriptionsSymbolTypeA[14:0]InputBA1, BA0CAS#CK, CK#InputInputInputCKE0, CKE1InputCS1#, CS0#InputLDM, UDM(x16)InputDescriptionAddress inputs: Specifies the row or column address. Also used to load the mode registers. Themaximum LPDDR address is determined by density and configuration. Consult the LPDDRproduct data sheet for the maximum address for a given density and configuration. Unusedaddress pins become RFU.Bank address inputs: Specifies one of the 4 banks.Column select: Specifies the command to execute.CK is the system clock. CK and CK# are differential clock inputs. All address and control signalsare sampled and referenced on the crossing of the rising edge of CK with the falling edge ofCK#.Clock enable:CKE0 is used for a single LPDDR product.CKE1 is used for dual LPDDR products.Chip select:CS0# is used for a single LPDDR product.CS1# is used for dual LPDDR products and is considered RFU for single LPDDR MCPs.Data mask: Determines which bytes are written during WRITE operations.For x16 LPDDR, unused DM balls become t/outputRow select: Specifies the command to execute.Write enable: Specifies the command to execute.Data bus: Data inputs/outputs.DQ[31:16] are RFU for x16 LPDDR devices.DQ[31:0](x32)LDQS, UDQS(x16)Input/outputData strobe: Coordinates READ/WRITE transfers of data; one DQS per DQ byte.For x16 LPDDR, unused DQS balls become pplyTemperature sensor output: TQ HIGH when LPDDR TJ exceeds 85 C.VDD: LPDDR power supply.VDDQ: LPDDR I/O power supply.VSSQ: LPDDR I/O ground.Table 4:SymbolVSSNCRFU1Non-Device-Specific Ball DescriptionsTypeSupply––DescriptionVSS: Shared ground.No connect: Not internally connected.Reserved for future use.Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.Contact the factory for details.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN8Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPElectrical SpecificationsElectrical SpecificationsTable 5: Absolute Maximum RatingsParameters/ConditionsSymbolMinMaxUnitVCC, VDD, VDDQ Supply voltagerelative to VSSVoltage on any pinrelative to VSSStorage temperature rangeVCC, VDD,VDDQVIN–1.02.4V–0.5V––552.4 or (supply voltage1 0.3V), whichever is less 150 CNotes: 1. Supply voltage references either VCC,VDD, or VDDQ.Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of thedevice at these or any other conditions above those indicated in the operational sectionsof this specification is not implied. Exposure to absolute maximum rating conditions forextended periods may affect reliability.Table 6: Recommended Operating ConditionsParametersSymbolMinTypMaxUnitSupply voltageI/O supply voltageOperating temperature rangeVCC, VDDVDDQ–1.701.70–401.801.80–1.951.95 85VV CPDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN9Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPDevice DiagramsDevice DiagramsFigure 5:152-Ball Functional Block Diagram (Single LPDDR)CE0#VCCCLEALENAND RCKE0RAS#DQCAS#WE#DQSTQAddress,VSSQBA0, BA1PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN10Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPDevice DiagramsFigure 6:152-Ball Functional Block Diagram (Dual LPDDR)CE0#VCCCLEALENAND FlashRE#I/OWE#WP#R/B#VSSCS0#, CS1#VDDCKVDDQCKE0, CKE1DQMRAS#LPDDRCAS#(Die 0 and 1)DQWE#TQPDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 ENAddress,VSSBA0, BA1VSSQ11Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPPackage DimensionsPackage DimensionsFigure 7:152-Ball VFBGA (Package Code: CA)0.46 0.1SeatingplaneA0.12 A152X Ø0.45Solder ballmaterial: SAC105.Dimensions applyto solder balls postreflow on Ø0.35SMD ball pads.14 0.1Ball A1 IDBall A1 ID21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1ABCDEFGHJK1314 0.1CTRLMNPRTUVW0.65 TYPYAA0.65 TYP0.9 MAX0.35 MIN13 CTRNote:PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 ENAll dimensions are in millimeters.12Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPPackage DimensionsFigure 8:152-Ball VFBGA (Package Code: CG)SeatingplaneA0.6 0.10.1 A152X Ø0.46Solder ballmaterial: SAC105.Dimensions applyto solder balls postreflow on Ø0.35SMD ball pads.Ball A1 ID21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1ABCDBall A1 IDEFGHJKL13 CTR14 0.1MNPRTUVW0.65 TYPYAA1.0 MAX0.65 TYP0.35 MIN13 CTR14 0.1Note:PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 ENAll dimensions are in millimeters.13Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPPackage DimensionsFigure 9:152-Ball TFBGA (Package Code: JQ)SeatingplaneA0.75 0.10.12 A152X Ø0.45Solder ballmaterial: SAC105.Dimensions applyto solder balls postreflow on Ø0.35SMD ball pads.Ball A1 ID21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1Ball A1 ID13 CTR0.65 TYPABCDEFGHJKLMNPQRTUVWX14 0.11.1 MAX0.65 TYP0.35 MIN13 CTR14 0.1Notes: 1. All dimensions are in millimeters.8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900www.micron.com/productsupport Customer Comment Line: 800-932-4992Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners.Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of productiondevices.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN14Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Preliminary152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCPRevision HistoryRevision HistoryRev. E, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/09 “NAND Flash-Specific Features” on page 1: Deleted device size bullet. Figure 2: “152-Ball Part Number Chart,” on page 2: Added U and V options underNAND Flash configurations; deleted low-power option under LPDRAM self refreshcurrent; added dimensions to package codes; added CS# to first column under chipcount; changed CE# from 2 to 1 for B and D under chip count. Table 1, “Production Part Numbers,” on page 3: Replaced former table 1. Figure 3: “152-Ball VFBGA Ball Assignments (NAND x8; LPDDR x16),” on page 5:Updated figure. Figure 4: “152-Ball VFBGA Ball Assignments (NAND x16; LPDDR x32),” on page 6:Updated figure. Table 2, “x8/x16 NAND Ball Descriptions,” on page 7: Updated table. Table 3, “x16/x32 LPDDR Ball Descriptions,” on page 8: Updated table. Table 4, “Non-Device-Specific Ball Descriptions,” on page 8: Updated table. Table 5, “Absolute Maximum Ratings,” on page 9: Updated table. Table 6, “Recommended Operating Conditions,” on page 9: Updated table. Figure 5: “152-Ball Functional Block Diagram (Single LPDDR),” on page 10: Updatedfigure title; updated figure. Figure 6: “152-Ball Functional Block Diagram (Dual LPDDR),” on page 11: Added figure.Rev. D, Preliminary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/08 Updated template; ready for external publication.Rev. C, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/08 Added part number for JQ package code, page 1. Figure 2, Marketing Part Number Example, on page 2: added JQ package code. Added JQ package diagram, Figure 9, 152-Ball TFBGA (Package Code: JQ), on page 14.Rev. B, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 On page 1, added part number for CA package code.Figure 2: Marketing Part Number Example on page 2: Added CA package code.Removed former capacitance tables. See component data sheets for capacitance.Figure 7: 152-Ball VFBGA (Package Code: CA) on page 12, and Figure 8: 152-BallVFBGA (Package Code: CG) on page 13: Updated figures.Rev. A, Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/08 Initial release.PDF: 09005aef8326e5ac / Source: 09005aef8326e59a152ball nand lpdram j4xx omap.fm - Rev. E 4/09 EN15Micron Technology, Inc., reserves the right to change products or specifications without notice. 2008 Micron Technology, Inc. All rights reserved.
Flash and Mobile LPDRAM devices are also members of the Micron discrete memory products portfolio. The NAND Flash and Mobile LPDRAM devices are packaged with separate interfaces (no shared address, control, data, or power balls). This bus architecture supports an opti - mized interface to processors with separate NAND
Context: NAND and NAND driver I Provide an abstraction layer for raw NAND devices I Take care of registering NAND chips to the MTD layer I Expose an interface for NAND controllers to register their NAND chips: struct nand_chip I Implement the glue between NAND and MTD logics I Provide a lot of interfaces for other NAND related stu
Android (version lower than 2.3) mobile phone’s internal memory is a NAND flash chip using YAFFS2 file system to manage data. NAND flash memory contains three logical structures: flash erasable zone, flash block and flash page. The flash erasable zone is the unit of managing bad block, because the NAND flash
Universal Gate -NAND I will demonstrate The basic function of the NAND gate. How a NAND gate can be used to replace an AND gate, an OR gate, or an INVERTER gate. How a logic circuit implemented with AOI logic gates can be re-implemented using only NAND gates. That using a single gate type, in this case NAND, will reduce the number of integrated circuits (IC) required to implement a
An XOR built from four NAND gates.MODEL P PMOS.MODEL N NMOS.SUBCKT NAND A B Y Vdd Vss M1 Y A Vdd Vdd P M2 Y B Vdd Vdd P M3 Y A X Vss N M4 X B Vss Vss N.ENDS X1 A B I1 Vdd 0 NAND X2 A I1 I2 Vdd 0 NAND X3 B I1 I3 Vdd 0 NAND X4 I2 I3 Y Vdd 0 NAND
a 3D NAND flash memory block quickly increases by an order of magnitude within 3 hours after programming. (3) 3D NAND flash memory experiencesretention interference, a new phenomenon where the rate at which charge leaks from a flash cell is dependent on the amount of charge stored in neighboring flash cells (Section4.4).
years to load the BIOS from the slower ROM into the higher-speed RAM. There is a limit to the number of times NAND Flash blocks can reliably be programmed and erased. Nominally, each NAND block will survive 100,000 PROGRAM/ERASE cycles. A technique known as wear leveling
C. Nand Flash Memory and eMMC As shown in Fig. 3, flash memory cell consists of one transistor with a floating gate. Information is stored in floating gate. There are 2 kinds of flash memory, NAND and NOR but currently the dominating type is NAND Flash. So we consid
transactions would allow participants to enter in commercial bilateral transactions to find a counterparty that will assume the Capacity Supply Obligation (“CSO”) and mitigate exposure ‒Reliability can be improved by finding a counterparty in the bilateral window for a given season since in times of scarcity, in ARA3 the CSO may not be acquired by another resource . Current Rules 3 T
