Introduction To The MIPS Architecture

Introduction to the MIPS ArchitectureJanuary 14–16, 20131 / 24

Unofficial textbookMIPS Assembly Language Programmingby Robert BrittonA beta version of this book (2003) is available free online2 / 24

Exercise 1 clarificationThis is a question about converting between bases bit – base-2 (states: 0 and 1) flash cell – base-4 (states: 0–3) hex digit – base-16 (states: 0–9, A–F) Each hex digit represents 4 bits of information:0xE 1110 It takes two hex digits to represent one byte:1010 0111 0xA73 / 24

OutlineOverview of the MIPS architectureWhat is a computer architecture?Fetch-decode-execute cycleDatapath and control unitComponents of the MIPS architectureMemoryOther components of the datapathControl unit4 / 24

What is a computer architecture?One view: The machine language the CPU implementsInstruction set architecture (ISA) Built in data types (integers, floating point numbers)Fixed set of instructionsFixed set of on-processor variables (registers)Interface for reading/writing memoryMechanisms to do input/output5 / 24

What is a computer architecture?Another view: How the ISA is implementedMicroarchitecture6 / 24

How a computer executes a programFetch-decode-execute cycle (FDX)1. fetch the next instruction from memory2. decode the instruction3. execute the instructionDecode determines: operation to execute arguments to use where the result will be storedExecute: performs the operation determines next instruction to fetch (by default, next one)7 / 24

Datapath and control unitDatapathMajor hardware components of the FDX cycle path of instructions and data through the processor components connected by busesBus – parallel path for transmitting values in MIPS, usually 32 bits wide8 / 24

Datapath and control unitControl unitControls the components of the datapath determines how data moves through the datapathreceives condition signals from the componentssends control signals to the componentsswitches between buses with multiplexersMultiplexer – component for choosing between busesselectAMUXBout9 / 24

OutlineOverview of the MIPS architectureWhat is a computer architecture?Fetch-decode-execute cycleDatapath and control unitComponents of the MIPS architectureMemoryOther components of the datapathControl unit10 / 24

Components of the MIPS architectureMajor components of the datapath: program counter (PC) instruction register (IR) register file arithmetic and logic unit (ALU) memoryControl unithttp://www.cise.ufl.edu/ mssz/CompOrg/Figure4.3-MIPSarch2.gif11 / 24

Memory: text segment vs. data segmentIn MIPS, programs are separated from data in memoryText segment “instruction memory” part of memory that stores the program (machine code) read onlyData segment “data memory” part of memory that stores data manipulated by program read/write12 / 24

Memory: text segment vs. data segmentDistinction may or may not be reflected in the hardware: von Neumann architecture – single, shared memory Harvard architecture – physically separate memories13 / 24

Memory addressing in MIPSFor reading/writing the data segmentBase address plus displacementMemory address computed as base offset: base is obtained from a register offset is given directly as an integerLoad word (read word from memory into register):lw t1,8( t2) t1 : Memory[ t2 8]Store word (write word from register into memory):sw t1,4( t2) Memory[ t2 4] : t1We’ll talk about addressing in the text segment later14 / 24

Program counter (PC)Program: a sequence of machine instructionsin the text 10800040x2129ffff0x1d20fff9Program counterRegister that stores the address of the next instruction to fetch also called the instruction pointer (IP)15 / 24

Incrementing the PCIn MIPS, each instruction is exactly 32-bits longWhat is the address of the next instruction?PC 4(Each address refers to one byte, and 32/8 4)16 / 24

Instruction register (IR)Instruction registerRegister that holds the instruction currently being decodedNote condition signals from the IR to the control unit!17 / 24

Register fileRegister: component that stores a 32-bit valueMIPS register file contains 32 registers18 / 24

Register names and conventionsNumber 0 1 2– 3 4– 7 8– 15 16– 23 24– 25 26– 27 28 29 30 31Name zero at v0– v1 a0– a3 t0– t7 s0– s7 t8– t9 k0– k1 gp sp fp raUsageconstant 0x00000000assembler temporaryfunction return valuesfunction argumentstemporariessaved temporariesmore temporariesreserved for OS kernelglobal pointerstack pointerframe pointerreturn addressPreserved?N/A777737N/A333319 / 24

Arithmetic and logic unit (ALU)Implements binary arithmetic and logic operationsInputs: operands – 2 32-bit operation – control signalOutputs: result – 1 64-bit(usually just use 32 bits of this) status – condition signals20 / 24

Control unitControls components of datapath to implement FDX cycle Inputs: condition signals Outputs: control signalsImplemented as a finite state machine21 / 24

MIPS data path with control ures/MIPS datapath control.gif22 / 24

Control unitCondition signals from IR – decode operation, arguments, result location from ALU – overflow, divide-by-zero, . . .Control signals to multiplexors – buses to selectto each register – load new valueto ALU – operation to performto all – clock signal23 / 24

Clock signalEach component is implemented as an electrical circuit when inputs change, outputs change – not instantaneous! clock signal ensures we don’t use outputs until readyClock generator produces the clock signal10 synchronizes the components in the data path the faster the clock, the faster the program executes clock rate is limited by the slowest component!24 / 24

What is a computer architecture? One view: The machine language the CPU implements Instruction set architecture (ISA) Built in data types (integers, floating point numbers) Fixed set of instructions Fixed set of on-processor variables (registers) Interface for