Hands-on Homework 2: Modeling Transmission Lines

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Hands-on Homework 2: Modeling transmission linesIntroductionIn class, we developed a model for a infinite length lossless transmission line (t-line). It wasconfigured as a ladder network of vanishingly small, identical, series L and shunt C elements.Such a transmission line will have a fixed characteristic impedance Zo and time-of-flight delay Tfwhich we derrived. Using circuit simulation we will confirm the models validity. Then using thismodel, you will build a delay line with a specified Zo and delay.This exercise also serves as a jumpstart to driving spice (specifically ngspice) from a netlist. Adetailed examination of the simulation files used will be given. Feel free to copy and modify foryour needs. However, you are not relieved of understanding what is going on in the files.Spice Simulation of the Infinite Length T-line ModelConsider the infinite length t-line model we developed.VinZoFigure 1: Infinite length t-line modelThe characteristicimpedance Zo and the flight time Tf of such a line was developed in lecture.2LThe values of L and C are measured on a per-unit-length basis. Note that the series L, shunt Cconfiguration a lowIf however, L and C are allowed to be arbitrarily small, the tranI pass filter.ICCsimssion line will have a correspondingly large bandwidth. A network with a large bandwidthwill allow digital pulses to traverse the network with low distortion.LIn lecture we found that:rwavefrontwavefront LTf LC MCP1702 3.3Zo v3.3C32 VinVoutWe now confirm these results by building a slightly simplified t-line model. Consider a digitalC2the edge, constant currentwave edge propagating downB1the networkin Figure 2. BehindC1 as shownGNDL 4.5V10uF1 U10.1uF1v3.3C30.1uFACOL 20 EK14 VDDNC 17 GNDOUT 8U2R1L1L2L3L4Zo 14?nH?nH?nH?nHdly out

L9L10iout.C9.Vinflows. In front of the edge, no current flows. Only at the edge,is there a changing current. Thus,Zowe can look at one section of the network composed of two L’s and one C. Since this is a seriescircuit, we can simplify it by consolidating the two inductors into one.tline seginC10outgndL2LIICCLwavefrontdly outwavefrontten instances of the subcircuitL1?nHC1?pFaMCP1702 3.32 VinVout 3Figure 2: Combining two series inductors into oneGNDB1The second simplifcation is to limit the size of the network to one-hundredC1L and C elements.1 U14.5V0.1uFAlthough it’s nowhere near an infinite number of elements, we will find that it’s actually quiteaccurate for our situation. In addition, with a termination resistor at the end of the network, it willlook infinitely long.ACOL 20 EKv3.3Let’s build our test case around a 80 ohm transmissionline thatexhibits a 4ns delay. Using the14 VDDNC 1R1 valuesL1equations we derived for delay Tf , and characteristic impedance Zo , thefor total L L2and C7 GND OUT 8are easily determined. Dividing the total L o 140.1uFU2L and C element.C2Below, we will develop the ngspice file for simulating the 100 element-lengthC1line. If you?pF?pFL2 concatenateL3L4inc order, each dly outpiece shown, you will have a complete, executable ngspice file.b?nH?nH?nHLC network simulating 4ns, 80ohm line*This model usesC2C3 100 sectionsC4 to create the 4ns line?pF?pF.param Vdd 3.3.param Vth ’3.3/2’v3.3 R280?pF;Vdd is assumed to be 3.3 Volts;set the swithing threshold to 1/2 VddTITLE or you use line one as a title line, itsThe first line in any spice file is the title line. WetherREVISION:still a title. If you put a netlist element or simulation FILE:command here, it will become the titleandOFBY:otherwise ignored. There is no need for a comment PAGEcharacter in the title.You may also DRAWNremindyourself that line one is the title by putting .title on line one.Comment lines in spice usually begin with a *. A semicolon may be used as an end of linecomment delimiter as well.Two parameters are defined; one for Vdd and Vth . They allow the use of a text variable in thespice file improving readability and flexibility. For example, if the supply voltage changes, we canchange it in one place instead of everywhere it was used. Smart software practices hold true inspice files too!Since we are going to build a model with 100 LC sections, a hierarchical approach is the onlypractical way. Imagine trying to draw a schematic with 100 L and C elements. We build thespice model by using ten subcircuits that each hold ten L and C elements. A spice subcircuit isa hierarchical block that contains another spice netlist. It is placed within a top-level netlist toencapsulate circuitry for complexity hiding.2C210uFL3?nHC3?pF

A subcircuit is analogous to a function call in C. It is called from another body of code. Itis supplied arguments, but they are the ports on the subcircuit block. Our subcircuit internalrepresentation and equivalent block diagram are shown below.L1inaL2L9iL10out.gndC1C2C9C10tline seginoutgndLFigure 3: Encapsulation of 10 LC sections into one subcircuitICThe subcircuit below creates a 10 LC element portion of a 100 element, 80 ohm ****************************R1 used to make up the longer tline*subcircuit composed of 10 LCv insectionsdly indly out.subckt tline seg in out gndL val 3.2nhC val 0.5pften instances of the subcircuitl1inaL val0.1 l2abL vall3bcL valV1l4cdL val l5deL vall6efL vall7fgL vall8ghL vall9hiL vall10 ioutL valc1agndC valc2bgndC valc3cgndC valc4dgndC valc5egndC valc6fgndC valc7ggndC valc8hgndC valR1L1L2L3v inadly inbcc9igndC valc10 outgndC val?nH?nH?nHZo.ends tline seg **********V1 C1?pFC2?pFC3?pFwavefrontR280vC30.1uFL4dly out?nHC4?pFSubcircuits begin with .subckt followed by the subcircuit name then the names of its ports.The port names are understood internal to the subcircuit. The elements in the subcircuit are connected as with any spice netlist. The subcircuit ends with the ”.ends” command.In cases where there are many elements of the same value, or where you may want to overridevalues, parameters may be added to the subcircuit. Here L val and C val at the subcircuit callset the values of all the L and C elements. These values are defaults and my be overridden atinstaniation time.3

To use the subcircuit in the top level circuit, it is called with a line that begins with an X,followed by a unique number if there are multiple instances of the subcircuit. A small x will alsowork, but the capital version stands out more in the netlist. Wires are connected to the subcircuitin the same orderin L1whichathey wereL2 declared in the subcircuitL9L10out At the end of the line,i declaration.inthe name of the subcircuit being used is named.Below we see ten instantiations of the subcircuit. . . . . .called. . tline seg tied in series. Pay attentiongndC1C2C9C10to indentation. It’s not just pretty; it helps prevent mistakes.*10 subcircuit calls to the tline segments*inputoutputgndnameX1 dly inagndtline segX2abgndtline segX3bcgndtline segX4cdgndtline segX5degndtline segX6efgndtline segX7fggndtline segX8ghgndtline segX9higndtline segX10idly outgndtline segtline seginoutgndLIBelow is the entire circuit we are modeling.v inR10.1VinCLdly inwavefrontdly outten instances of the subcircuitR280 V1 Figure 4: Top level schematicv3.3*input source with 1ns delay, 2nS edges, 25ns pulse width, 50ns cycle timeV1 vin 0 PULSE(0 Vdd 1ns 2ns 2ns 25ns 50ns)R1 vindly in 0.1 ;0.1 ohm resistor used to determine the input currentR2 dly out gnd80;terminating resistor at end of networkR1L1L2L3C30.1uFL4abcdly outA pulsed sourcev inis declared dly inalong with a 0.1ohm currentsensing resistor.This resistoris used?nH?nH?nH?nHto determine the input currentZo into the network. We will need it to determine the input impedanceof the network. You will see how this is done later. We have also placed an 80 ohm resistor at theC1C2C3C4V1end of the network to terminate it. This?pFmakes the networklook?pFlike it is infinitelylong as any?pF?pFwavefront cannot tell the difference from ”looking into” a longer segement of 80 ohm transmissionline and a resistor. This completes our circuit netlist.We need to tell the simulator what to do. This is done via simulation directives. In this casewe use the .tran command to run a transient simulation. The simulation will run for 50ns andsample data every 100ps.4

.tran 100ps 50ns;run tranisient simulation for 50ns*measure the time delay at switching threshold (Vth) from input to output of tline.meas tran tdelay trig v(dly in) val Vth rise 1 td 100ps targ v(dly out) val Vth rise 1 td 100ps*measure the input impedance during the rising edge at the switching threshold.meas tran z in find par(’(v(dly in)/((v(vin)-v(dly in))/0.1))’) when v(dly in) Vth.control* plot v(dly in) v(dly out) v(vin) xl 100ps 50ns* gnuplot gnuplt 4ns 80ohm v(dly in) v(dly out) v(vin).endc.endxl 100ps 50nsOnce the simulation has run, we can gather data and make automated measurements. We usethe .meas command to do this. The.meas command is complex with many options and possibilities for making measurements. With the measure command, we confirm the t-line delay anddetermine its input impedance.The first .meas command measures the delay. The result generated is called tdelay. Themeasurement is triggered when the first rising edge of node v(dly in) reaches Vth . The check forthe trigger begins after a 100ps delay. The target or point at which the measurement is ended isreached when first rising edge of node v(dly out) reaches Vth .The second .meas command measures the input impedance. We choose Vth as the point onthe rising edge to take the measurement. The result generated is called zin. The input impedanceis determined by dividing the voltage at the input of the network by the current flowing into thenetwork. The current into the network is sampled by the 0.1 ohm resistor.After we run the simulation, ngspice prints results into the invoking shell window showingthe delay to be close to 4ns and the input impedance to be about 82 ohms.Measurements for Transient Analysistdelay 4.025456e-09 targ z in 8.161427e 016.026681e-09 trig 2.001225e-09Its also important to also see the waveforms of the signals generated. This maybe done with eitherthe plot or gnuplot command inside the .control and .endc commands. Uncomment plot tosee results interactively or use gnuplot for nice looking plots. The simulation result from gnuplothere shows an approximate 4ns delay and good pulse shape fidelity.5

L1inaL2L9L10iout.gndC1lc network simulating 4ns,C9 80ohm lineC2C103.5Vinv(dly in)v(dly out)v(vin)3tline seg2.5in2outgndVL2L1.5I1L0.5v in 0ICR1dly in0.1 5e-091e-081.5e-082e-082.5e-08s V1wavefrontdly outten instances of the subcircuit3e-083.5e-084e-084.5e-085e-08R280Figure 5: Pulse applied to 100 section t-line model Building a working delay linev3.3The last digit of your student ID will determine the characteristics of the delay line you will build.See the table in the grading section to find your variation of the network parameters. Develop thespice circuit simulation model of your delay line and then physically build the circuit. Here is the C3schematic of the simulation model.0.1uFv in V1 R1Zodly inL1?nHC1?pFaL2b?nHC2?pFL3?nHC3?pFcL47 GNdly out?nHC4?pFFigure 6: Simulation model of the circuit to buildThis circuit is slightly different than the first model. Instead of a parallel termination resistorat the output of the network, there is a Zo ohm series termination resistor at the input. Anotherdifference is that to simplify the circuit, only four LC sections are used instead of one-hundred.The oscillator is modeled using the same pulse statement as before.For an example, suppose you are building a 50 ohm, 5ns delay line with four sections. Ourspice netlist would look like the following.6ACO14 VDTITLEFILE:PAGE

LC network simulating 5ns, 50ohm line.param Vdd .param Vth 3.31.5;Vdd is 3.3 Volts;set the sampling voltage to 1.5 volts*input source with 1ns delay, 2nS edges, 25ns pulse width, 50ns cycle timeVin vin 0 PULSE(0 Vdd 1ns 2ns 2ns 25ns **************************subcircuit composed of 1 LC section used to make up the longer tline.subckt tline seg in out gndL1inout?nH ; student suppliedC1outgnd?pF ; student supplied.ends tline *************R1X1X2X3X4vindly inabcdly inabcdly out50gndgndgndgnd;series termination resistortline segtline segtline segtline seg.controltran 100ps 50nsplot v(dly in) v(dly out) xl 100ps 50ns.endc*measure the time delay at switching threshold (Vth) from input to output of tline.meas tran tdelay trig v(dly in) val Vth rise 1 td 100ps targ v(dly out) val Vth rise 1 td 100ps*measure the input impedance during the rising edge at the switching threshold.meas tran z in find par(’(v(dly in)/((v(vin)-v(dly in))/50))’) when v(dly in) Vth.endHere are the simulation results from ngspice. The delay is pretty close to our target valueseven with only four LC sections. The input impedance is rather off. This may be an artifact of thesmall number of elements in the delay line.Measurements for Transient Analysistdelay 4.990899e-09 targ z in 8.583434e 017.430053e-09 trig 2.439154e-09Note that the voltage at which the delay and input impeadance was changed to allow a measurement with the ”voltage pedestal” present at the network input.7

v(vin)v(dly in)v(dly e-082.5e-08s3e-083.5e-084e-084.5e-085e-082LFigure 7: Waveforms from 5ns, 50ohm delay networkILICCBuild the real thingHere is the circuit you will build. It is the physical realization of the model we just developed.wavefrontwavefrontMCP1702 3.32 VinVout 3v3.3 C4pFsimulation of 4 section, 5ns, 50ohm lineB14.5Vv3.3C30.1uFC210uFGND1 U1C10.1uFACOL 20 EK14 VDDNC 17 GNDOUT 8U2R1L1L2L3L4Zo 14?nH?nH?nH?nHC1?pFdly outC2?pFC3?pFdly outC4?pFFigure 8: Breadboard circuit of delay line to buildThe value of the termination resistor R1 depends on the output impedance of the oscillator. Theoscillator has an output impedance of about 14 ohms. So the value of R1 to properly terminate thenetwork is Zo 14.The inductors are built using toroidal cores. The physical shape of the toroids keep the magTITLEnetic field well contained and lessens interaction with nearby objects. One turn on a toroid isREVISION:defined as one FILE:pass through the toroid, not a lap aroundthe core. The winding on the toroidsPAGEOFDRAWN BY:8

should occupy about two thirds of the form. Don’t allow the turns to overlap. On the protoboard,keep the toroids spaced a bit so they do not capacitively or inductively couple.The number of turns required for a Micrometals T25-12 with an Al value of 1.2 is given by:rdesired inductance in nHN 1.2Determine the turns required and wind all four inductors. Remembering that wires are inductors, assemble the circuit on the breadboard using short leads. However, leave yourself enoughroom to make measurements. Also, remember that your scope probe tip will change the capacitance required at the end of the delay network.Here is a a picture of a 5ns, 50 ohm delay network built on the protoboard to give you a roughidea of what it should look like. Note both probes are using short ground leads.Figure 9: Delay line built on protoboardMeasure the delay by using two scope probes (borrow one from a friend). This will be measured at the same points as your simulation. Capture the waveform at both points with the scopeand include in your lab report. Here is a scope capture of my 5ns, 50 ohm delay network. The actual delay is 5.7ns. The output waveform shape is maintained fairly well. The top trace is dly out,the bottom trace dly in.Note that the pedestal on dly in is 10ns; or twice the delay of the network. The network isworking like an actual transmission line. The end of the pedestal on dly out corresponds to thereflection returning from the end of the network. You will learn more about this soon.9

Figure 10: dly out (top) dly in (bottom) from 5ns, 50 ohm delay networkUsing the characteristics of voltage dividers and your measurements, determine the inputimpedance of your delay line. Include your calculations in your lab report.GradingLast digit of student ID0-12-34-56-78-9Tf5ns10ns3.5ns7ns7nsZo100 ohms100 ohms70 ohms70 ohms141 ohmsTable 1: IDs verses network values10

DeliverableDemonstratable, working prototype of delay lineReport, consisting of :spice file used to simulate the delay line you builtoutput from spice run showing delay and input impedancescope picture showing dly in, dly out, and delaycalculation of input impedancePoorly formatted writeupCan’t make measurement from scope pictureIncorrect scope readingCan’t read scope settingsPrototype circuit is obviously wrongLate, up to one weekTable 2: Grading metrics11Grade Weighting30%10%10%30%20%-10%-20%-20%-20%-40%-20%

LC network simulating 4ns, 80ohm line *This model uses 100 sections to create the 4ns line.param Vdd 3.3 ;Vdd is assumed to be 3.3 Volts.param Vth ’3.3/2’ ;set the swithing threshold to 1/2 Vdd The first line in any spice file is the title line. Wethe

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