Flip Chip Ball Grid Array Package Reference Guide (Rev. A)
Flip Chip Ball Grid Array PackageReference GuideLiterature Number: SPRU811AMay 2005
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ContentsContents1Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1Package Drawing Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.1 Daisy-Chained Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.2 Package Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.3 Board Level Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.4 Reliability Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.5 Electrical Modeling and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.1.6 Thermal Modeling and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2PCB Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.1 Land and Solder Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.2 Signal Line Space and Trace Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.3 Routing and Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.4 Pad Surface Finish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.2.5 PCB Stack and Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3System Level Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.3.1 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101010111212131315162022282932324SMT Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.1Handling, Storage, Preparation and Bake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2Solder Paste Printing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2.1 Stencil Design, Aperture, Material of Construction . . . . . . . . . . . . . . . . . . . . . . . .4.2.2 Soldering Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.2.3 Coplanarity (Warpage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.3Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.4Solder Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5Defluxing (Cleaning) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3538393941414344475Repair and Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485.1TI Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486Mechanical Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516.1External Heat Sink Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
Contents7Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.1Non-Destructive Failure Analysis at the SMT Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.2Destructive Failure Analysis at the SMT Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.3Component Removal for Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535559608Other Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.1Moisture Sensitivity of Surface Mount and BGA Packages . . . . . . . . . . . . . . . . . . . . . . . .8.1.1 Recommended Baking Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.1.2 Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.1.3 Floor Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.2Packing Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.2.1 Tray Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8.3Electrostatic Discharge Sensitive Devices (ESDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62626366686969709Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
16.17.18.19.20.21.22.23.24.25.26.27.28.29.Typical Flip Chip BGA Package (Cross-Sectional View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Flip Chip BGA Package Footprint – Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Daisy-Chain Test Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Typical Flow of Heat in a Flip Chip BGA Package Without Heat Sink . . . . . . . . . . . . . . . . . . 13Heat Flow Analysis for Device Thermal Modeling With Heatsink . . . . . . . . . . . . . . . . . . . . . . 15NSMD and SMD Pads – Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16NSMD and SMD Pads – Cross-Sectional View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16NSMD Versus SMD Lands Pads as Package is Mounted onPCB—Cross-Sectional View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Solder Ball Areas Susceptible to Stress Caused by Non-Optimized PackagePad/PCB Land Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Trace Routing Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Cross-Section of Different Via Types for Signal Transfer Through PCB . . . . . . . . . . . . . . . . 22Connection Between Vias, Via Capture Pads, Surface Lands, and Stringers . . . . . . . . . . . 23Space Between Surface Land Pads for a 0.45 mm NSMD Pad . . . . . . . . . . . . . . . . . . . . . . . 23Via Capture Pad Layout for Escape Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Typical and Premium Via Capture Pad Sizes (in mils) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25PCB Escape Routing for a 0.8 mm BGA Pitch Using Laser-Drilled Blind Vias . . . . . . . . . . 27Impact of Number of Thermal vias Versus Die (Chip) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Impact of Number of 0.33-mm (0.013 inch) Diameter Thermal Vias Versus Die(Chip) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Thermal Management Options for Flip Chip BGA Packages . . . . . . . . . . . . . . . . . . . . . . . . . 32Compact Package Model in a System-Level Thermal Simulation . . . . . . . . . . . . . . . . . . . . . 34Typical SMT Assembly Process Flow for Flip Chip BGA Packages . . . . . . . . . . . . . . . . . . . . 35Ideal Reflow Profile for Eutectic Solder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Recommended Lead-Free Reflow Profile for SnAgCu Solder Paste . . . . . . . . . . . . . . . . . . . 47Thermal Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Major Thermal Conduction Paths to Optimize Thermal Dissipation . . . . . . . . . . . . . . . . . . . . 51Schematic of a Die-Substrate-PCB System Showing Circuit Loop for TDRAnalysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Schematic of TDR Waveforms for a Flip Chip BGA Package. . . . . . . . . . . . . . . . . . . . . . . . . 59JEDEC Shipping Trays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Typical Tray Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
TablesTables12345678910116Flip Chip BGA Package Qualification Test Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Optimum PCB Land Diameters for Flip Chip BGA Pad Pitches . . . . . . . . . . . . . . . . . . . . . . .Number of Traces Routed Based on Space and Trace Line Width . . . . . . . . . . . . . . . . . . . .Via Types for Signal Transfer Through PCB Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Formula for Via Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Typical Via Capture Pad Sizes Used by PCB Vendors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Solder Paste Types Used for Surface Mounting of BGA Devices . . . . . . . . . . . . . . . . . . . . .Typical Stages and Characteristics on a Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Typical Defects Found During SMT Assembly and Probable Causes . . . . . . . . . . . . . . . . .X-Ray Versus Optical Inspection Defect Detection (Courtesy of Metcal) . . . . . . . . . . . . . .Moisture Classification Level and Floor Life . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1120212225264045535768
Flip Chip Ball Grid Array Package1AbstractTexas Instruments (TI ) Flip Chip Ball Grid Array (BGA) packages provide thedesign flexibility to incorporate higher signal density and overall ICfunctionality into a smaller die and package footprint.Flip chip BGA packages can be mounted using standard printed circuit board(PCB) assembly techniques, and can be removed and replaced usingstandard repair procedures.This document provides application guidelines for effective flip chip BGAdevice handling and management, including board design rules, ement,troubleshooting, and other critical factors.SPRU811Flip Chip Ball Grid Array Package7
Introduction2IntroductionThe term flip chip describes the method of electrically connecting the die to thepackage substrate. Flip chip microelectronic assembly is the direct electricalconnection of face-down (or flipped) integrated circuit (IC) chips ontosubstrates, circuit boards, or carriers, using conductive bumps on the chipbond pads.In contrast to wire-bonding technology, the interconnection between the dieand carrier in flip chip packaging occurs when using a conductive bump placeddirectly on the die surface. The bumped die is then flipped and placed facedown so that the bumps connect directly to the carrier.Figure 1 shows a cross-section of a typical flip chip BGA package.Figure 1.Typical Flip Chip BGA Package (Cross-Sectional View)LidUnderfillSolder ballDieFC bumpChip capacitorDie/lid attach adhesiveOrganicsubstrateFlip chip components are predominantly semiconductor devices; however,components such as passive filters, detector arrays, and MEMs devices arenow used in flip chip form.A more descriptive term, direct chip attach (DCA), is used when the chip isdirectly attached to the printed circuit board or carrier by the conductivebumps.The advantages of flip chip interconnect include reduced signal inductance,power/ground inductance, and package footprint, along with higher signaldensity and die shrink.TI’s flip chip BGA packages are assembled on either two-metal layer ormulti-layered, high-density organic laminate or ceramic substrates, and usedextensively in ASIC, HPA, and DSP applications. Package handling andmanagement is critical for successful operation in the field.8Flip Chip Ball Grid Array PackageSPRU811
Introduction2.1Package Drawing OutlineThe flip chip BGA package outline drawing provides important mechanicaldesign data, including package dimensions (length, width, and thickness) andsolder ball number, size, and pitch.Package mechanical drawings can be obtained directly from TI’s database bysimply specifying the package descriptor. Figure 2 shows the mechanicaldimensions for a 288-ball package coinciding with TI’s package designator288GTS.NOTE: Figure 2 is provided for reference only. Please refer to TI’s packagedatabase for the latest dimensional data for the 288GTS package.Figure 2.Flip Chip BGA Package Footprint – Mechanical DrawingGTS (S PBGA N288) Plastic Ball Grid Array23,10SQ22,9021,10SQ20,9021,00 TYP1,000,50ABAAYVTPMKA1 CornerHFWUR1,00NLJ0,50GEDCBA12345678911 13 15 17 19 2110 12 14 16 18 20 22Bottom View2,80 MAX1,90 NOMSeating Plane0,50 NOM0,700,500,100,600,400,154205308/B 01/04NOTES: A.B.C.D.SPRU811All linear dimensions are in millimetersDrawing subject to change without noticeFlip chip application onlyFalls within JEDEC MO 034BFlip Chip Ball Grid Array Package9
Design Considerations3Design ConsiderationsEach flip chip BGA goes through rigorous qualification tests before thepackage is released to production. The following sections discuss the varioustools that are used to predict package performance in an application.3.1Reliability3.1.1Daisy-Chained UnitsUse daisy-chained units (mechanical samples) to gain experience in:- Handling and mounting flip chip BGA packages for board-reliability testing- Checking PCB electrical layouts- Confirming the accuracy of the mounting equipmentDaisy-chained packages provide a continuous path through the package forease-of-testing. TI issues a net list for each package that correlates each ballposition to a corresponding die bump number.Assembling a daisy-chained package on the PCB forms a complete circuit andallows continuity testing. The circuit includes the following:-Solder ballsMetal pattern on the dieBumpsPackage interconnects/tracesPCB tracesYou can interconnect and test the entire package or only a quadrant. Figure 3shows the test configuration.Figure 3.Daisy-Chain Test ConfigurationTesterChipSolder ballsPCBCopper traces10Flip Chip Ball Grid Array PackageTest padsSPRU811
Design ConsiderationsEach flip chip BGA goes through rigorous qualification tests before thepackage is released to production. Samples used in these tests arepreconditioned according to Joint Electronic Device Committee (JEDEC)A113 at various levels. Table 1 summarizes typical package qualification tests.Additional environmental or mechanical tests may be performed. Please referto the product data sheet for specific package reliability data.3.1.2Package LevelPackage reliability focuses on:-Table 1.Materials of constructionThermal flowsMaterial adherence/delamination issuesResistance to high temperaturesMoisture resistanceFlip chip joint/interconnectFlip Chip BGA Package Qualification Test SummaryTest EnvironmentsConditionsHighly-accelerated stress test (HAST)85%RH/85 CAutoclave121 C, 15 psigTemperature cycle, air-to-air 65/150 C, or 55/125 C 65/150 C, or 40/125 CThermal shock, liquid-to-liquid 65/150 C, or 55/125 C, or 40/125 CHigh temperature operating life (HTOL)125 C, Op. voltageHTOL‡140 C, Op. voltageHTOL‡155 C, Op. voltageBake high temperature storage life (HTSL‡)150 CBoard level/solder joint reliability temperature cycle 40/125 C, or0/100 CHAST130 C† RH relative humidity‡ One or more optional tests may be added to meet customer requirements.SPRU811Flip Chip Ball Grid Array Package11
Design Considerations3.1.3Board Level ReliabilityIn addition to device/package testing, TI performs board-level reliability (BLR)testing on flip chip BGA packages.BLR testing includes:- Assembling daisy-chained packages to testing boards and exposing themto temperature cycles- Taking electrical measurements in the initial state and then at intervalsafter temperature cycles are runTwo important conclusions can be drawn from BLR testing:- PCB land size should match the package pad size.- Solder paste and flux is required for attachment to give optimal reliability.3.1.4Reliability ModelingReliability modeling is another important tool used to predict packageperformance in an application. Thermal, electrical, and thermo-mechanicalmodeling, verified by experimental results, provide insight into systembehavior. This modeling process also shortens package development time,predicts system lifetimes, and provides an important analytical tool.In applications such as BGAs, where interconnections are made throughsolder balls, the useful life of the package usually depends on the useful lifeof the solder itself. Because this area has been studied extensively, accuratemodels exist, both for predicting solder behavior and for interpretingaccelerated life testing.TI methodology includes extensive model refinement and constantexperimental verification. For a given package, a detailed 2D finite elementmodel (FEM) is constructed that performs 2D plain strain elastoplasticanalysis to predict areas of high stress.These models also account for the thermal variation of material properties,such as modulus of elasticity, coefficient of thermal expansion (CTE), andPoisson’s ratio as a function of temperature. These allow the FEM to calculatethe thermo-mechanical plastic strains in the solder joints for a given thermalloading.Package and board-level stress analysis is performed using finite elementmodeling, which provides full 3D nonlinear capabilities for package stress,component warpage, and solder joint reliability studies.12Flip Chip Ball Grid Array PackageSPRU811
Design Considerations3.1.5Electrical Modeling and AnalysisTexas Instruments extensive package characterization capabilities include anelectrical measurements lab with time domain reflectometer/inductanceresistance capacitance (TDR/LRC) and network analysis capabilities.Package electrical design (PACED), an internally-developed tool, performselectrical modeling that provides 2.5D and full 3D capability for LRC models,transmission lines, dielectrics, and SPICE deck outputs.3.1.6Thermal Modeling and AnalysisThe high operating temperature of a device, caused by the combination ofambient conditions and device power dissipation, is an important reliabilityconcern. For instance, instantaneous high temperature rises can possiblycause catastrophic failure, as well as long-term degradation in the chip andpackage materials, both of which may eventually lead to failure.Most TI flip chip BGA devices are designed to operate reliably with a junctiontemperature of no more than 105 C. To ensure this condition is met, thermalmodeling is used to estimate the performance and capability of IC packages.Design changes can be made and thermally tested from a thermal modelbefore any time is spent on manufacturing.Components with the most influence on the heat dissipation of a package canalso be determined. Models can approximate the performance of a packageunder many different conditions.Figure 4 shows the typical heat flow paths in a flip chip BGA package for atypical system without an exposed heat spreader or heat sink.Figure 4.Typical Flow of Heat in a Flip Chip BGA Package Without Heat Sink80 90% of heat 10 20% of heatThermal modeling is performed using ThermCAL, a TI internal thermalsimulation tool, and a third-party computer simulation package. Modelingincludes complex geometries, transient analysis, and anisotropic materials.These capabilities provide a full range of thermal modeling, from devicethrough system level.SPRU811Flip Chip Ball Grid Array Package13
Design ConsiderationsIn addition, the flip chip BGA packages undergo extensive empirical thermalcharacterization. The package thermal dissipation capabilities are physicallymeasured in an internal lab with JEDEC standard test conditions up to 1,000watts.The following metrics are commonly used to characterize flip chip BGApackages in thermal design:- RθJC: Resistance from die (junction) to the top of the package (case);--measured using an infinite heat sink on the top of the package. This metricis useful primarily when the case of the package is connected to anexternal heat sink.RθJB: Resistance from die to the bottom of the package (board, measured1 mm from package), as defined in the Joint Electronic Device Committee(JEDEC) standard, JESD 51 8. This metric includes some of the boardcharacteristics and their coupling with the package.RθJA: (JESD 51 2) Total resistance of the whole system from die toambient still air under standard conditions.RθJMA: (JESD 51 6) Total resistance of the whole system from die tomoving air under standard conditions.Psi-jt: Pseudo resistance from die to the top of the package (value variesby environment).Psi–jb: Pseudo resistance from die to board (measured 1 mm frompackage; value varies by environment).Figure 5 shows the heat flow analysis for thermal modeling of a device with aheat sink.14Flip Chip Ball Grid Array PackageSPRU811
Design ConsiderationsFigure 5.Heat Flow Analysis for Device Thermal Modeling With HeatsinkTaAirThermocoupleattachmentSinkCase/sink jointSink to airRcsCase to sinkRjcTcJunctionCaseBoardPower planesand viasAir3.2RsaTjJunction to caseRcbCase to boardRbBoardRbaBoard to airTaPCB DesignThe primary board design considerations include metal-pad sizes andassociated solder-mask openings. PCB pads/land patterns, which are usedfor surface mount assembly, can be:- Non-solder mask defined (NSMD) — The metal pad on the PCB (to whicha package BGA solder ball is attached) is smaller than the solder maskopening.- Solder mask defined (SMD) — The solder mask opening is smaller thanthe metal pad.Figure 6 and Figure 7 illustrate the metal-pad and associated solder-maskopenings.SPRU811Flip Chip Ball Grid Array Package15
Design ConsiderationsFigure 6.NSMD and SMD Pads – Top ViewNon-solder mask defined padFigure 7.SoldermaskSolder mask defined padNSMD and SMD Pads – Cross-Sectional ViewSolder maskopeningCopperpadSoldermaskSolder maskopeningCopperpadThe most common PCB material sets on which assembly can be performedare:- Standard epoxy glass substrate- FR-4- BT (bismaleimide triazine)The mechanical properties of the PCB, such as its CTE, can be affected by thenumber of metal layers, laminate materials, trace density, operatingenvironment, site population density, and other considerations.The more flexible, thinner PCBs consequently show greater reliability duringthermal cycling. The industry standard PCB thickness ranges from 0.4 mm to2.3 mm.3.2.1Land and Solder MaskThe design of the PCB and the flip chip BGA itself is important in achievinggood manufacturability and optimum reliability. When designing a PCB forfine-pitch BGA packages, consider the following factors:-16Surface land pad dimensionVia capture pad layout and dimensionSignal line space and trace widthNumber of PCB layersFlip Chip Ball Grid Array PackageSPRU811
Design ConsiderationsFigure 8 shows the location of the package pad (A) and board lands (B).Figure 8.NSMD Versus SMD Lands Pads as Package is Mounted onPCB—Cross-Sectional ViewABGA packageBGA solder ballSolder maskPCBBCopperpadFigure 9 illustrates why the layout and dimensions of the package pads andthe board lands are critical. Matching the diameters of the PCB pad to thepackage side BGA pad helps form a symmetrical interconnect, and preventsone end of the interconnect from exhibiting a higher stress condition than theother.SPRU811Flip Chip Ball Grid Array Package17
Design ConsiderationsFigure 9.Solder Ball Areas Susceptible to Stress Caused by Non-Optimized PackagePad/PCB Land RatioPackagePCBPackagePCBPackagePCBIn fact, if the design of the PCB pad diameters are even slightly smaller thanthe package side BGA pad diameter, the joint stress on the PCB side isemphasized rather than on the typically weaker package BGA side.The top view of Figure 9 shows a package pad that is larger than the PCB land.In this case, the solder ball is prone to crack prematurely at the PCB interface.In the middle view of Figure 9, the PCB land is larger than the package pad,which leads to cracks at the package surface.In the bottom view of Figure 9, where the ratio is almost 1:1, the stresses areequalized and neither site is more susceptible to cracking than the other. Thisis the preferred design.Solder lands on the PCB are generally simple round pads. Solder lands areeither SMD or non-solder-mask-defined NSMD.18Flip Chip Ball Grid Array PackageSPRU811
Design ConsiderationsNon-Solder-Mask-Defined (NSMD) LandWith NSMD-configured pads, there is a gap between the solder mask and thecircular contact pad (refer to Figure 6). With this configuration, the solder flowsover the top surface and the sides of the contact pad.The additional NSMD soldering area results in a stronger mechanical bond.In addition, the additional area allows NSMD pads to be smaller than SMDpads. The smaller size is beneficial for system designers, as they allow moreroom for escape trace routing.Table 2 shows optimum land diameters for a current flip chip BGA pitch. ForPCB land definition, the NSMD land is recommended. So
SPRU811 Flip Chip Ball Grid Array Package 9 2.1 Package Drawing Outline The flip chip BGA package outline drawing provides important mechanical design data, including package dimensions (length, width, and thickness) and solder ball number, size, and pitch. Package mechanica
Auto Flip Settings - Flipbooks can flip automatically. Enable Auto Flip and set Flip Interval, Flip loops: set -1: Auto flip all the time; set N (N 0): Flip N times then stop. Check Auto Flip from start to make the flipbook flip automatically from start. Click the Auto Flip Button when you need if you don't check this option.
Abstract—Recent advanced flip chip ball grid array (FCBGA) packages require high input/output (I/O) counts, fine-pitch bumps and large/thin package substrates. One of the key hurdles to accommodate these requirements is the flip chip bonding process. Therefore, advanced flip chip bonding technologies are continuously being developed and one .
Rangkaian Flip-Flop JK Pada flip-flop JK ini, masukan J dan K disebut masukan pengendali karena kedua masukan ini yang menentukan keadaan yang harus dipilih oleh flip-flop pada saat pulsa clock tiba (dapat pinggiran positif atau negatif, tergantung kepada jenis flip-flopnya). flip-flop ini berbeda dengan flip-flop-D karena pada flip-flop-JK
Some Flip Flops may have a reset (or clear) and/or a set line that directly change the output. All Flip Flops change states according to data lines on clock pulses. All Flip Flops have an output usually labeled Q, the inverse of the output, labeled Q, a SET, and a RESET. Figure 11.1 - D Flip Flop and JK Flip Flop
Fig 1. One-Piece Lid High Performance Flip Chip BGA (HP-fcBGA) Package. A new design of flip chip BGA package (patent pending) has been looked into for improved board level performance. In this new design, the flip chip will be plastic encapsulated (with the die top surface expo
Ball Screw Selection White Paper Ball Screw Basics A ball screw assembly consists of a ball screw and a ball nut with recirculating ball bearings. (Figure 1) The interface between the screw and the nut is made by ball bearings that roll in matching forms in the ball screw and ball nut. The load on the ball screw
D Flip Flop. Seperti yang diketahui, flip-flop (Bistable Multivibrator) dalah suatu rangkaian sel biner yang memiliki dua buah output yang saling berkebalikan keadaannya (0 atau 1). Di dalam FPGA, terdapat sebuah jenis flip-flop yaitu D flip-flop atau Data flip flop. Rangkaian D flip-flop ini berfungsi sebagai rangkaian
NORTH & WEST SUTHERLAND LOCAL HEALTH PARTNERSHIP Minutes of the meeting held on Thursday 7th December 2006 at 12:00 Noon in the Rhiconich Hotel, Rhiconich. PRESENT: Dr Andreas Herfurt Lead Clinician Dr Moray Fraser CHP Medical Director Dr Alan Belbin GP Durness Dr Anne Berrie GP Locum Dr Cameron Stark Public Health Consultant Mrs Sheena Craig CHP General Manager Mrs Georgia Haire CHP Assistant .
