AN4488 Application Note - STMicroelectronics

2y ago
42 Views
3 Downloads
1.19 MB
50 Pages
Last View : 5d ago
Last Download : 2m ago
Upload by : Harley Spears
Transcription

AN4488Application noteGetting started with STM32F4xxxx MCU hardware developmentIntroductionThis application note is intended for system designers who require an overview of thehardware implementation of the development board, with focus on features like power supply package selection clock management reset control boot mode settings debug management.This document shows how to use the high-density high-performance microcontrollers listedin Table 1, and describes the minimum hardware resources required to develop anapplication based on those products.Detailed reference design schematics are also contained in this document, together withdescriptions of the main components, interfaces and modes.Table 1. Applicable productsTypePart numbers and Product linesSTM32F401xB / STM32F401xCSTM32F401xD / STM32F401xESTM32F405/415 lineSTM32F407/417 lineSTM32F410x8 / STM32F410xBMicrocontrollersSTM32F411xC / STM32F411xESTM32F412xE / STM32F412xGSTM32F413/423 lineSTM32F427/437 lineSTM32F429/439 lineSTM32F446 lineSTM32F469/479 lineOctober 2018AN4488 Rev 71/50www.st.com

ContentsAN4488Contents1Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.13Digital supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.1Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.2Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.2Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.3Analog Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Reset and power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1.13.24Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.1PDR ON circuitry example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.2Power on reset (POR) / power down reset (PDR) . . . . . . . . . . . . . . . . . 173.2.3Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 18Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.1Package Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2Pinout Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224.2.14.34.4Handling unused pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.4.12/50I/O speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Alternate Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244.3.15NRST circuitry example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254.5Boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274.6Embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.1SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2.1SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295.2.2Internal pull-up and pull-down resistors on JTAG pins . . . . . . . . . . . . . . 30AN4488 Rev 7

AN4488Contents5.2.36SWJ debug port connection with standard JTAG connector . . . . . . . . . 30Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.1HSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.2LSE OSC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337Reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348Recommended PCB routing guidelines forSTM32F4xxxx devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368.1PCB stack-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368.2Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378.3Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378.4High speed signal layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388.598.4.1SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388.4.2Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 398.4.3Quadrature serial parallel interface (Quad SPI) . . . . . . . . . . . . . . . . . . . 398.4.4Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Package layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418.5.1BGA 216 0.8 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . . . 418.5.2WLCSP143 0.4 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . 42FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.1Identify the STM32F4xxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.2Hardware tools available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.39.2.1Nucleao Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.2.2Discovery kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.2.3Evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459.2.4Where to find IBIS models? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46MCU does not work properly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4610Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4711Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AN4488 Rev 73/503

List of tablesAN4488List of tablesTable 1.Table 2.Table 3.Table 4.Table 5.Table 6.Table 7.Table 8.Table 9.Table 10.Table 11.Table 12.4/50Applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Referenced documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Package summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22Alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26STM32F4xxxx bootloader communication peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30BGA 216 0.8 mm pitch package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Wafer level chip scale package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42MCU does not work properly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AN4488 Rev 7

AN4488List of figuresList of figuresFigure 1.Figure 2.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.Figure 10.Figure 11.Figure 12.Figure 13.Figure 14.Figure 15.Figure 16.Figure 17.Figure 18.Figure 19.Figure 20.Figure 21.Figure 22.Figure 23.Figure 24.Figure 25.Figure 26.Figure 27.Figure 28.BYPASS REG supervisor reset connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Power supply scheme (excluding STM32F469xx/F479xx) . . . . . . . . . . . . . . . . . . . . . . . . . 10Power supply scheme for STM32F469xx/F479xx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13NRST circuitry example (only for STM32F410xx, STM32F411xx,STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xxand STM32F479xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14NRST circuitry timings example (not to scale, only for STM32F410xx,STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx,STM32F469xx and STM32F479xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15PDR ON simple circuitry example (not needed for STM32F410xx,STM32F411xx, STM32F413xx, STM32F423xx, STM32F412xx, STM32F446xx,STM32F469xx and STM32F479xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16PDR ON timings example (not to scale, (not needed for STM32F410xx,STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx,STM32F469xx and STM32F479xx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19STM32CubeMX example screen-shot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29JTAG connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31HSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32HSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32LSE external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33LSE crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Four layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Six layer PCB stack-up example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Typical layout for VDD/VSS pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38BGA 0.8mm pitch example of fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Via fan-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42FMC signal fan-out routing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42143-bumps WLCSP, 0.40 mm pitch routing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44STM32 ST-LINK Utility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45AN4488 Rev 75/505

Reference documents1AN4488Reference documentsThe following documents are available on www.st.com.Table 2. Referenced documentsReferenceTitleAN2867Oscillator design guide for ST microcontrollersAN2606STM32 microcontroller system memory boot modeAN3364Migration and compatibility guidelines for STM32 microcontroller applicationsThis document applies to Arm (a)-based devices.a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.6/50AN4488 Rev 7

AN44882Power suppliesPower suppliesThe operating voltage supply (VDD) range is 1.8 V to 3.6 V, which can be reduced down to1.7 V with some restrictions, as detailed in the product datasheets. An embedded regulatoris used to supply the internal 1.2 V digital power.The real-time clock (RTC), backup registers and backup registers can be powered from theVBAT voltage when the main VDD supply is powered off.2.1Digital supply2.1.1Voltage regulatorThe voltage regulator is always enabled after reset. It works in three different modesdepending on the application modes. in Run mode, the regulator supplies full power to the 1.2 V domain (core, memoriesand digital peripherals) in Stop mode, the regulator supplies low power to the 1.2 V domain, preserving thecontents of the registers and SRAM in Standby mode, the regulator is powered down. The contents of the registers andSRAM are lost except for those concerned with the Standby circuitry and the Backupdomain.Note:Depending on the selected package, there are specific pins that should be connected eitherto VSS or VDD to activate or deactivate the voltage regulator. Refer to section “Voltageregulator “ in datasheet for details.2.1.2Regulator OFF modeRefer to section “Voltage regulator” in datasheet for details. When BYPASS REG VDD, the core power supply should be provided through VCAP1and VCAP2 pins connected together.–The two VCAP ceramic capacitors should be replaced by two 100 nF decouplingcapacitors.–Since the internal voltage scaling is not managed internally, the external voltagevalue must be aligned with the targeted maximum frequency.–When the internal regulator is OFF, there is no more internal monitoring on V12.An external power supply supervisor should be used to monitor the V12 of thelogic power domain (VCAP).AN4488 Rev 77/5049

Power suppliesAN4488PA0 pin should be used for this purpose, and act as power-on reset on V12 powerdomain. In regulator OFF mode, the following features are no more supported:–PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logicpower domain which is not reset by the NRST pin.–As long as PA0 is kept low, the debug mode cannot be used under power-onreset. As a consequence, PA0 and NRST pins must be managed separately if thedebug connection under reset or pre-reset is required.–The over-drive and under-drive modes are not available.–The Standby mode is not available.Figure 1. BYPASS REG supervisor reset connections ϭϮ([WHUQDO 9& 3B SRZHU VXSSO\ VXSHUYLVRU([W UHVHW FRQWUROOHU DFWLYH ZKHQ 9& 3B 0LQ 9 W Ϭ ƉƉůŝĐĂƚŝŽŶ ƌĞƐĞƚ ƐŝŐŶĂů ;ŽƉƚŝŽŶĂůͿEZ d zW ͺZ 's ϭϮ;ŶŽƚĞ ϭͿ;ϭ dž ϭϬϬ Ŷ&ͿϮ dž ϭϬϬ Ŷ&s s Wϭs WϮs ϭͬϮͬ͘͘͘EE п ϭϬϬ Ŷ&н ϭ п ϰ͘ϳ ђ&s ϭͬϮͬ͘͘͘EĂŝϭϴϰϵϴsϱ1. VCAP2 is not available on all packages. In that case, a single 100 nF decoupling capacitor is connected toVCAP1The following conditions must be respected:8/50 VDD should always be higher than VCAP to avoid current injection between powerdomains. If the time for VCAP to reach V12 minimum value is smaller than the time for VDD toreach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP reachesV12 minimum value and until VDD reaches 1.7 V. Otherwise, if the time for VCAP to reach V12 minimum value is smaller than the time forVDD to reach 1.7 V, then PA0 could be asserted low externally. If VCAP goes below V12 minimum value and VDD is higher than 1.7 V, then PA0 mustbe asserted low externally.AN4488 Rev 7

AN44882.2Power suppliesPower supply schemesThe circuit is powered by a stabilized power supply, VDD.Caution:The VDD voltage range is 1.8 V to 3.6 V (down to 1.7 V with some restrictions, see relativeDatasheet for details). The VDD pins must be connected to VDD with external decoupling capacitors: onesingle Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package one100 nF Ceramic capacitor for each VDD pin. The VBAT pin can be connected to the external battery (1.65 V VBAT 3.6 V). If noexternal battery is used, it is recommended to connect this pin to VDD with a 100 nFexternal ceramic decoupling capacitor. The VDDA pin must be connected to two external decoupling capacitors (100 nFCeramic 1 µF Tantalum or Ceramic). The VREF pin can be connected to the VDDA external power supply. If a separate,external reference voltage is applied on VREF , a 100 nF and a 1 µF capacitors mustbe connected on this pin. In all cases, VREF must be kept between (VDDA-1.2 V) andVDDA with minimum of 1.7 V. Additional precautions can be taken to filter analog noise: –VDDA can be connected to VDD through a ferrite bead.–The VREF pin can be connected to VDDA through a resistor.For the voltage regulator configuration, there is specific BYPASS REG pin (notavailable on all packages) that should be connected either to VSS or VDD to activate ordeactivate the voltage regulator specific.– Refer to Section 2.1.2 and section "Voltage regulator" of the related devicedatasheet for details.When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to2*2.2 µF LowESR 2Ω Ceramic capacitor (or 1*4.7 µF LowESR 1Ω Ceramiccapacitor if only VCAP1 pin is provided on some packages).AN4488 Rev 79/5049

Power suppliesAN4488Figure 2. Power supply scheme (excluding STM32F469xx/F479xx)9% 79% 7 WR 9*3,2V,1 [ ) î ) 9& 3B 9& 3B 9'' 1966 11 [ Q) [ ),2/RJLF.HUQHO ORJLF &38 GLJLWDO 5 0 9ROWDJH UHJXODWRU% 3 66B5(*9''86% 9''86% Q) )3'5B219'')ODVK PHPRU\27*)63 5HVHW FRQWUROOHU9'' 95() Q) )/HYHO VKLIWHU2879''%DFNXS FLUFXLWU\26& . 57& :DNHXS ORJLF%DFNXS UHJLVWHUV EDFNXS 5 03RZHU VZLWFK Q) ) 95() 95() '& QDORJ5&V 3// 966 06Y 9 1. Optional. If a separate, external reference voltage is connected on VREF , the two capacitors (100 nF and1 µF) must be connected.2. VCAP2 is not available on all packages. In that case, a single 4.7 µF (ESR 1Ω) is connected to VCAP1.3. VREF is either connected to VREF or to VDDA (depending on package).4. VREF- is either connected to VREF- or to VSSA (depending on package).5. N is the number of VDD and VSS inputs.6. Refer to datasheet for BYPASS REG and PDR ON pins connection.7. VDDUSB is only available on STM32F446xx.8. Backup RAM is not available on STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx, andSTM32F423xx.10/50AN4488 Rev 7

AN4488Power suppliesFigure 3. Power supply scheme for STM32F469xx/F479xx9% 7287*3,2V î )9'' [ Q) [ ) ,19& 3B 9& 3B 9'' 966 /HYHO VKLIWHU9% 7 WR 9 %DFNXS FLUFXLWU\26& . 57& :DNHXS ORJLF%DFNXS UHJLVWHUV EDFNXS 5 03RZHU VZLWFK,2/RJLF.HUQHO ORJLF &38 GLJLWDO 5 0 9ROWDJH UHJXODWRU% 3 66B5(*9''86%9''86%)ODVK PHPRU\27* )63 Q)9'''6,9& 3'6,9'' '6, )'6,3 966'6,3'5B219''5HVHW FRQWUROOHU9'' 95() Q) Q) ) )'6,9ROWDJH UHJXODWRU95() 95() '& QDORJ5&V 3// 966 06Y 9 1. Optional. If a separate, external reference voltage is connected on VREF , the two capacitors (100 nF and1 µF) must be connected.2. VREF is either connected to VREF or to VDDA (depending on package).3. VREF- is either connected to VREF- or to VSSA (depending on package).4. Refer to datasheet for BYPASS REG and PDR ON pins connection.AN4488 Rev 711/5049

Power supplies2.3AN4488Analog SupplyTo improve conversion accuracy, the ADC has an independent power supply that can befiltered separately, and shielded from noise on the PCB. The ADC voltage supply input is available on VDDA pin. An isolated supply ground connection is provided on the VSSA pin.In all cases, the VSSA pin should be externally connected to same supply ground than VSS.To ensure a better accuracy on low-voltage inputs, the user can connect a separate externalreference voltage ADC input on VREF . The voltage on VREF may range from (VDDA- 1.2V) to VDDA with a minimum of 1.7 V.When available (depending on package), VREF– must be externally tied to VSSA.12/50AN4488 Rev 7

AN4488Reset and power supply supervisor3Reset and power supply supervisor3.1System resetA system reset sets all registers to their reset values except for the reset flags in the clockcontroller CSR register and the registers in the Backup domain (see Figure 2).A system reset is generated when one of the following events occurs:1.A low level on the NRST pin (external reset)2.window watchdog end-of-count condition (WWDG reset)3.Independent watchdog end-of-count condition (IWDG reset)4.A software reset (SW reset)5.Low-power management resetThe reset source can be identified by checking the reset flags in the Control/Status register,RCC CSR.The products listed in Table 1 do not require an external reset circuit to power-up correctly.Only a pull-down capacitor is recommended to improve EMS performance by protecting thedevice against parasitic resets, as exemplified in Figure 4.Charging and discharging a pull-down capacitor through an internal resistor increases thedevice power consumption. The capacitor recommended value (100 nF) can be reduced to10 nF to limit this power consumption.Figure 4. Reset circuit9''([WHUQDOUHVHW FLUFXLW15675 38)LOWHU6\VWHP UHVHW )3XOVHJHQHUDWRUPLQ V::'* UHVHW,:'* UHVHW3RZHU UHVHW6RIWZDUH UHVHW/RZ SRZHU PDQDJHPHQW UHVHWDL 3.1.1NRST circuitry exampleThis example applies to STM32F410xx, STM32F411xx, STM32F412xx, STM32F413xx,STM32F423xx, STM32F446xx and STM32F469 where PDR ON can be connected to VSSto permanently disable internal reset circuitry.Restrictions: PDR ON 0 is mostly intended for VDD supply between 1.7 V and 1.9V (i.e. 1.8V /5% supply).Supply ranges which never go below 1.8V minimum should be better managed byAN4488 Rev 713/5049

Reset and power supply supervisorAN4488internal circuitry (no additional component needed, thanks to fully embedded resetcontroller). When the internal reset is OFF, the following integrated features are no longersupported:–The integrated power-on reset (POR) / power-down reset (PDR) circuitry isdisabled.–The brownout reset (BOR) circuitry must be disabled.–The embedded programmable voltage detector (PVD) is disabled.–VBAT functionality is no more available and VBAT pin should be connected to VDD.Figure 5. NRST circuitry example (only for STM32F410xx, STM32F411xx,STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xxand STM32F479xx)9ROWDJH 9 W\S 9 PLQUHJXODWRU9'' 9'' 3'5B219% 75HVHW FRQWUROOHU9''670 1 9ROWDJH VXSHUYLVRU287 Nȍ1567DFWLYH ORZ RSHQ GUDLQ RXWSXW )670 ) 966 966 06 9 Even with PDR ON 0, during power up, the NRST is driven low by internal Reset controllerduring TRSTTEMPO in order to allow stabilization of internal analog circuitry. Refer toSTM32F4xxxx datasheets for actual timing value.14/50AN4488 Rev 7

AN4488Reset and power supply supervisorFigure 6. NRST circuitry timings example (not to scale, only for STM32F410xx,STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx,STM32F469xx and STM32F479xx)9''9'' GXULQJ RSHUDWLRQ NHSW DERYH 9 9VXSHUYLVRU KLJK WULS SRLQWVXSHUYLVRU ORZ WULS SRLQW3RZHU 2Q SKDVH2SHUDWLRQ15673RZHU 'RZQ SKDVHWLPH7VXSHUYLVRU ! 75677(0329''7VXSHUYLVRU5HVHW E\ LQWHUQDO VRXUFHV75677(0327VXSHUYLVRU 75677(032WLPH1567 .HSW ORZ E\ LQWHUQDO FLUFXLWU\1567 .HSW ORZ E\ H[WHUQDO VXSHUYLVRU1567 IRUFHG ORZ E\ H[WHUQDO VXSHUYLVRU06 9 Selection of NRST voltage supervisorVoltage supervisor should have the following characteristics Reset output active-low open-drain (output driving low when voltage is below trippoint).–Supervisor trip point including tolerances and hysteresis should fit the expectedVDD range.Notice that supervisor spec usually specify trip point for falling supply, sohysteresis should be added to check the power on phase.3.2Power supply supervisor3.2.1PDR ON circuitry exampleNote:This example doesn’t apply to STM32F410xx, STM32F411xx, STM32F412xx,STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xx and STM32F479xx, wherePDR ON can be connected to VSS to permanently disable internal reset circuitry (externalvoltage supervisor required on NRST pin). Thanks to backward compatibility, circuitry builtfor other STM32F4xxxx products will work for STM32F410xx, STM32F411xx,STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx, STM32F469xx andSTM32F479xx.AN4488 Rev 715/5049

Reset and power supply supervisorNote:AN4488Please contact your local STMicroelectronics representative or visit www.st.com in case youwant to use circuitry different from the one described hereafter.Restrictions: PDR ON 0 is mostly intended for VDD supply between 1.7 V and 1.9V (i.e. 1.8V /5% supply).Supply ranges which never go below 1.8V minimum should be better managed withinternal circuitry (no additional component thanks to fully embedded reset controller). To ensure safe power down, the external voltage supervisor (or equivalent) is requiredto drive PDR ON 1 during power off sequence.When the internal reset is OFF, the following integrated features are no longer supported: The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled. The brownout reset (BOR) circuitry must be disabled. The embedded programmable voltage detector (PVD) is disabled. VBAT functionality is no more available and VBAT pin should be connected to VDD.Figure 7. PDR ON simple circuitry example (not needed for STM32F410xx,STM32F411xx, STM32F413xx, STM32F423xx, STM32F412xx, STM32F446xx,STM32F469xx and STM32F479xx)9ROWDJH UHJXODWRU 9 W\S 9 PLQ9'' 9'' 9ROWDJH VXSHUYLVRU567DFWLYH KLJKRXWSXW3'5B219% 75HVHW FRQWUROOHUDFWLYH KLJK SXVK SXOO RXWSXW9'' Nȍ%66 1567RU HTXLYDOHQWRSWLRQDO LI 7VXSHUYLVRU 75677(032 )670 ) 966 966 06 9 16/50AN4488 Rev 7

AN4488Reset and power supply supervisorFigure 8. PDR ON timings example (not to scale, (not needed for STM32F410xx,STM32F411xx, STM32F412xx, STM32F413xx, STM32F423xx, STM32F446xx,STM32F469xx and STM32F479xx)9''9'' GXULQJ RSHUDWLRQ NHSW DERYH 9VXSHUYLVRU KLJK WULS SRLQW 9VXSHUYLVRU ORZ WULS SRLQW3RZHU 2Q SKDVH2SHUDWLRQ3'5B211567WLPH7VXSHUYLVRU ! 75677(0329'' 93RZHU 'RZQ SKDVH3'5B21 PXVW JR DERYH 97VXSHUYLVRU5HVHW E\ LQWHUQDO VRXUFHV9, 75677(0329,/7VXSHUYLVRU 75677(032WLPH1567 .HSW ORZ E\ LQWHUQDO FLUFXLWU\1567 .HSW ORZ E\ H[WHUQDO VXSHUYLVRU1567 IRUFHG ORZ E\ H[WHUQDO DQG LQWHUQDO FLUFXLWU\06 9 Selection of PDR ON voltage supervisorVoltage supervisor should have the following characteristics3.2.2 Reset output active-high push-pull (output driving high when voltage is below trippoint) Supervisor trip point including tolerances and hysteresis should fit the expected VDDrange.Notice that supervisor spec usually specify trip point for falling supply, so hysteresisshould be added to check the power on phase.Example:–Voltage regulator 1.8V /- 5% mean VDD min1.71V–Supervisor specified at 1.66V /- 2.5% with an hysteresis of 0.5% mean- rising trip max 1.71V (1.66V 2.5% 0.5%)- falling trip min 1.62V (1.66V - 2.5%).Power on reset (POR) / power down reset (PDR)The device has an integrated POR/PDR circuitry that allows proper operation starting from1.8 V.The device remains in the Reset mode as long as VDD is below a specified threshold,VPOR/PDR, without the need for an external reset circuit. For more details concerning theAN4488 Rev 717/5049

Reset and power supply supervisorAN4488power on/power down reset threshold, refer to the electrical characteristics in the productdatasheets.Figure 9. Power-on reset/power-down reset waveform6 60/2 0 2RISING EDGE60/2 0 2FALLING EDGE0/2 M6HYSTERESIS0 24EMPORIZATIONT2344%-0/2%3%4AI B1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge is1.70 V (typ.). Refer to STM32F4xxxx datasheets for actual value.The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled throughthe PDR ON pin. An external power supply supervisor should monitor VDD and shouldmaintain the device in reset mode as long as VDD is below a specified threshold. PDR ONshould be connected to this external power supply supervisor. See Section 3.2.1 for details.3.2.3Programmable voltage detector (PVD)You can use the PVD to monitor the VDD power supply by comparing it to a thresholdselected by the PLS[2:0] bits in the Power control register (PWR CR).The PVD is enabled by setting the PVDE bit.A PVDO flag is available, in the Power control/status register (PWR CSR), to indicatewhether VDD is higher or lower than the PVD threshold. This event is internally connected toEXTI Line16 and can generate an interrupt if enabled through the EXTI registers. The PVDoutput interrupt can be generated when VDD drops below the PVD threshold and/or whenVDD rises above the PVD th

October 2018 AN4488 Rev 7 1/50 AN4488 Application note Getting started with STM32F4xxxx MCU

Related Documents:

STM32CubeIDE quick start guide - User manual Author: STMICROELECTRONICS Subject: STM32CubeIDE is STMicroelectronics integrated development environment for STM32 microcontrollers and microprocessors. Keywords: STM32, IDE, Eclipse , QSG Created Date: 11/2/2020 4:57:17 PM

[2]. Ben Jordan, Amit Bahl Rigid - Flex PCB Design a guide book for design, Sierra Proto express, 2013 [3]. STMicroelectronics. STM32 embedded graphic objects/ touchscreen library, 2011. [4]. STMicroelectronics. STM32F10xxx ı2c optimized examples, 2010. [5]. STMicroelectronics. Migratin

How a designer can make the most of STMicroelectronics serial EEPROMs Introduction Electrically Erasable and PROgrammable Memory (EEPROM) devices are standard products used for the non-volatile storage of data parameters, with a fine-granularity. This application note describes most of the internal architecture and related functionality of

– Electrostatic discharge protection Application Reverse battery protection of an electronic control unit Description The VN5R003H-E is a device made using STMicroelectronics VIPower technology. It is intended for providing reverse battery protection to an electronic module. This devic

Application note SPC560Pxx/SPC56APxx HW design guideline Introduction This application note is intended for hardware designers. It gives hardware design references on SPC560Pxx/SPC56APxx microcontroller. Four topics are covered: Voltage Regulator (VREG) Main oscillator Supply pins Reference Reset circuit www.st.com

March 2017 DocID028650 Rev 3 1/7 For further information contact your local STMicroelectronics sales office www.

User manual Discovery kit with STM32L496AG MCU Introduction The 32L496GDISCOVERY Discovery kit is a complete demonstration and development platform for the STMicroelectronics Arm Cortex -M4 core-based STM32L496AGI6 microcontroller. Thanks to the innovative ultra-low-power-oriented features, extended RAM,

the 48-hour working week, which does not specifically exempt library (or academic) workers from the regulations. However, it should be feasib le to devise and negotiate librarian working schedules that would bring Edinburgh into line with other British universities that have already adopted 24-hour opening. Academic Essay Writing for Postgraduates . Independent Study version . 7. Language Box .