AN1543/D Electronic Lamp Ballast Design

AN1543/Dis the preferred solution in the USA with around 80% of theelectronic lamp ballasts using this scheme today (see typicalschematic diagram Figure NE220 VFLUORESCENTTUBEFigure 5. Typical Current Fed, Push Pull ConverterPush Pull TopologyThe main advantage of the current fed push pullconverter, besides the common grounded Emitter structure,is the ruggedness of this topology since it can sustain a shortcircuit of the load without any damage to thesemiconductors (assuming they were sized to cope with thelevel of current and voltage generated during such a faultcondition). This is a direct benefit of the current modebrought by the inductor in series with the VCC line.However, the imbalance in both the power transistors andthe magnetic circuit leads to high voltage spikes that makethis topology difficult to use for line voltage above 120 V.Additionally, it is not practical to dim the fluorescent tubeswhen they are driven from a push pull circuit, the halfbridge, series resonant topology being a far better solution.The push pull converter can be designed with either onesingle transformer, as shown in Figure 6, or by using aseparate core to build the oscillator (see Figure 7).Both of these topologies have their advantages anddrawbacks, the consequence for the associated powertransistors being not at all negligible as shown by Table 1.Table 1.Main Characteristics of the Dual SwitchesTopologiesParametersV(BR)CERInrush Currenttsi windowDriveIntrinsic GalvanicIsolationHalf BridgePush Pull700 V*3 to 4 times Inom**2.60 μs 3.60 μsHigh & Low sideno1100 V to 1600 V*2 to 3 times Inom**1.90 μs 2.30 μsLow side onlyyesNotes:* numbers are typical for operation on a 230 V line.** Inom: current into the transistors in steady VFBNbFigure 6. Basic Single Transformer CircuitFigure 7. Basic Two Transformer CircuitSingle Transformer Basic OperationThe circuit uses the same core to drive the transistors andto supply the power to the load. Operation is based on thesaturation of the core when the magnetic flux exceeds themaximum value the core can sustain. Although this is a verylow cost solution, it is not commonly used for power abovehttp://onsemi.com4

AN1543/Da few tens of watts, because the global efficiency isdowngraded by the dual mode operation of the outputtransformer (i.e., saturable and linear). Figure 6 gives thetypical schematic diagram.R1Q1T2VCCTwo Transformer OperationAt high load currents and high frequency, the transformerrequirements for the dual role of frequency control andefficient transformation of output voltage becomes adifficult problem in the single transformer design. For thisreason, the two transformer design, depicted in Figure 7, ismore advantageous. The operation of this circuit is similarto the one transformer case, except that only the small coreT2 need be saturated. Since the magnetization current of T2is small, high current levels due to transformer saturationmagnetic flux are reduced significantly when compared tothe one transformer design. Of course, the stresses appliedto the power semiconductors are reduced in the same ratio.Another major advantage of the two transformer inverterdesign is that the operating frequency is determined by VFB,a voltage easily regulated to provide a constant frequency todrive the power transformer.NbC1NbR2R3T1NpNpLOADQ2Figure 8. Basic Starting CircuitSinusoidal Output InverterThe basic inverters discussed above have an outputfrequency and voltage directly proportional to the supplyvoltage, the output being a square wave. To get a sinusoidaloutput, or a tightly controlled frequency together with aneasily regulated output voltage, the inverter must bemodified from the basic circuit. A simple but efficient way,is to use a current fed topology, with an inductor connectedbetween the primary of the output transformer and thesupply line as shown in Figure 9. When the circuit is tunedwith the capacitors C1 and C2, then the voltage across theswitches is sinusoidal, yielding minimum switching lossesinto the silicon. Typical waveforms are given in Figure 10.Starting CircuitIn general, the basic circuits depicted in Figures 6 and 7will not oscillate readily, unless some means is provided tobegin oscillation. This is especially true at full load and lowtemperature. A simple, commonly used starting circuit isshown in Figure 8 In this design, resistors R1 and R2 forma simple voltage divider to bias the transistors to conductionbefore the oscillation starts.http://onsemi.com5

AN1543/DLT1Q1C1VCCIC, FULL LOADC2R1LOADQ2R2NbC3NbIC, UNLOADED, TWO TRANSFORMER CONVERTERFigure 9. Typical Current Fed,Sinusoidal Output ConverterV π*VCCVCEICCURRENT FED, RESONANT CIRCUITFigure 10. Typical Push Pull WaveformsQ1R1330 220 VItubeR2D1C122 nFC2100 nF400 VVonCpC3100 nF400 VQ2R3D31N4937D4DIAC 32 VR410 ΩFLUORESCENT TUBEFigure 11. Typical Half Bridge Topologyhttp://onsemi.com6Vtrig

AN1543/DV(BR)EBO of the transistors, otherwise the Base Emitterjunction goes in avalanche and the global efficiency can bedowngraded.Moreover, one must point out that, even if the transistorcan sustain a Base Emitter avalanche (assuming that theassociated energy Ej is within the V(BR)EBO maximumrating), such a continuous mode of operation may make thetransient and long term behavior of the converter moredifficult to predict.However, there is no problem if the Base Emitter junctionis forced into the avalanche mode during start up because,under these conditions, the energy dissipated into thejunction is very low and can be absorbed by the silicon.The VBB voltage is given by another electromagneticequation:Transistor selection criteria: Select the Collector current capability to sustain thepeak value during either the unloaded or short circuitconditions. Select the V(BR)CES to avoid avalanche under the worstcase conditions (i.e., high line, unloaded operation). Define the storage time window to make sure thedevices will be tightly matched, thus minimizing themagnetic imbalance into the output transformer. Make sure the load line never goes outside either theFBSOA or RBSOA maximum ratings of the selectedtransistors.HALF BRIDGE TOPOLOGY ANALYSISBasic CircuitThe basic schematic diagram of the half bridge, selfoscillant topology is given in Figure 11. The two transistorsQ1 & Q2 are the active side of the bridge, capacitors C2 &C3 being the passive arm.dIcV CCLdtThe oscillations are generated by means of the saturabletransformer T1. Since the two transistors are biased in the offstate via the low Base Emitter impedance provided by thesecondaries of transformer T1, this circuit cannot start byitself, unless there is an imbalance between the high side andthe low side of the converter. But, such an imbalance willseverely downgrade the operation once the converterbegins. Therefore, it is preferable to have a pair of matchedtransistors and to start the converter with the network builtaround the Diac D4, capacitor C1 and resistor R1.When the line voltage is applied, capacitor C1 chargesexponentially through resistor R1. When the voltage acrossC1 reaches the trig value of D4, the diac turns on,discharging C1 into the Base Emitter network of Q2. Thistransistor turns on and the change in collector current (dI/dt)through the primary of T1, generates a voltage across eachof the secondaries of T1.By arranging the windings as depicted in Figure 11, thevoltage VBB is negative for the upper switch and positive forthe lower one. This forward biases Q2 and the Collectorcurrent of this transistor keeps rising until the core of T1saturates .From electromagnetic circuit theory, the magnitude of thecurrent in the secondaries of T1 is given by Equation 4:IB IC *Ns(7)Start up SequenceThe start up voltage (Vstrike) is generated by the seriesresonant network built with the inductor L and the capacitorC, the behavior of this network being predictable withEquations 8 to 15 given below.The resonant frequency is:fo 1(8)2 * p * Ǹ(L * C)The Quality Factor Q is given by :Q L*wSR(9)with ΣR sum of the DC resistance in the circuit.This factor can also be expressed by Equation 10:Q 1*SRǸCL(10)Out of resonance, the impedance of the RLC series circuitis given by Equation 11:Z ǸƪR2 )ǒLwǓƫ1 2Cw(11)At resonance, the Lω term equals the 1/Cω and canceleach other:(4)Lw Of course, the value of IB must be large enough to fullysaturate the transistor, even under worst case conditions:IIB w Cbwith β intrinsic current gain of the transistor(6)As a safety rule of thumb, in steady state VBB V(BR)EBO.The load being highly inductive,the Collector current willrise with a slope given by Equation 7:Operation DescriptionNpNsNpVBB VB *1Cw(12)Therefore, the impedance is minimum and equals the DCresistance:(5)Z ΣR(13)At resonance, the current in the circuit is maximum andfollows Ohm’s law:On the other hand, the VBB voltage developed across thesecondaries must be limited to a value lower than thehttp://onsemi.com7

AN1543/DI VCCΣR(14)SRLpItubeAt the same time, the voltage across the capacitor ismaximum as stated by Equation 15:VC VCC*Q(15)VPPThe behavior of an R/L/C resonant circuit is depicted byFigure 12 Depending upon the L/R ratio, the curve is moreor less flattened. This is described as the selectivity of theR/L/C network.Z(Ω)HALFFLUORESCENTBRIDGETUBEVonPout Von*ItubeL lowRFigure 13. Basic Equivalent Circuit in Steady StateThe first step is to define the chopper frequency, sincemost of the critical parameters are dependent upon thiscriteria.The topology being a self oscillant, Half Bridge willpermit the design to make the manufacturing of theelectronic circuit as simple as possible.The selected core used to build the converter must meetthe following specifications:The core must:a. be saturableb. exhibit a BH curve as square as possiblec. be available at the lowest possible costBy re arranging Ampere’s equation, we can compute theoperating frequency for a self oscillant converter based ona saturable core:Z RL highRZ′ R′FfoFigure 12. Typical R/L/C Series Network BehaviorThe value of Q is dictated by the needs of the application,and the associated components must be sized accordingly.Since the inductor L is a direct function of the output powerand operating conditions, the designer has no other choicethan to adjust the values of capacitor C and resistor R to setup the Quality factor, keeping in mind the DC resistance ofthe filaments.F VP * 1044 * NP * BS * Ae(16)With: VP voltage across the Primary windingNP number of turns of the PrimaryBS core saturation flux in TeslaAe Core cross section in cm2F frequency in HerzHALF BRIDGE DESIGNNote: The design proposed herein assumes a 220 V 50 Hzinput line voltage together with a single four foot 55 Wtube. The Von voltage is 100 V, the Vtrig being 800 V.Nominal operating frequency: 35 kHz.Designing a converter for the lamp ballast application isnot very difficult, but there are many steps and iterations thatmust be performed first. Unfortunately, there is no accurateand simple model available, at the time of this publication,to simulate an electronic lamp ballast. However, the simpleequivalent circuit given in Figure 13 is helpful to perform thefirst calculations when designing this kind of circuit.Care must be taken, not to try to cut cost in the base drivenetwork as the dynamic parameters of the power transistorswill likely to not be optimized. In fact, the storage time willprobably be greater than the computed operating chopperfrequency.The graph given in Figure 14 gives the typical storage timevariation, as a function of the bias conditions, for a bipolartransistor. More detailed information is available from thedesigner’s data sheet provided by ON Semiconductor.http://onsemi.com8

AN1543/Db. As the Collector current increases, the operating pointof the transistor moves along its HFE f(IC) curve.5IB1 IB2 160 mALc 200 μHVclamp 300 V4In the meantime, the Base current is limited to theNS/NP ratio, as stated by Equation 4.3tsi ( μs)One must remember that the VBB voltage is afunction of the dIC/dt, the absolute magnitude of theCollector current IC being irrelevant.2When the VBB voltage drops, the available Basedrive decreases and the transistor will rapidly leavethe saturation region. Consequently, the Collectorcurrent decreases and the dIC/dt reverses from apositive going slope to a negative going slope.1001.02.0IC (A)If the transistor is driven from a current transformer,then the same mechanism applies for the availableBase current, as stated by Equation 4.These two points are cumulative and, as soon as theprimary current decreases, the core starts to recover from theflux saturation, the VBB voltage (or the magneticallyinduced Base current) reverses, and the transistor willrapidly switch off the Collector current.The oscillograms given in Figures 15 and 16 show thetypical Base bias for a standard converter using thistechnique. Based on these oscillograms, it’s clear that theturn off mechanism, with typical timing values around 4 μs,is not negligible and must be taken into account during thedesign.Figure 14. Typical Storage Time Variation as aFunction of the Collector CurrentThe turn off mechanism of the transistor is twofold:a. When the current increases in the Primary winding NP,the magnetic flux increases accordingly, and theoperating point of the core moves toward the Bsat.At this point, the core goes into the saturation areaand its relative permeability mr collapses from itsnominal value down to unity.With a typical mr of 6000, this large variation makesthe Primary/Secondary coupling nearly negligibleand, consequently, the VBB voltage starts to drop,yielding less forward bias to the Base network.IB1H 5 μs/DIVV 500 mA/DIVSTORAGE TIMECOLLECTORCURRENTtsiZEROH 5 μs/DIVV 100 mA/DIVIB2Figure 16. Typical IC WaveformFigure 15. Typical Base Current WaveformTherefore, the practical operating frequency will bedependent upon the core used to build the saturabletransformer T1, and the absolute value of the Collectorcurrent storage time (tsi). This is shown by Equation 17:F 1 ) 1T2 * tsiThe factor 2 stands for the half bridge topology used.The design of a saturable transformer is bounded byseveral parameters:a. Magnetic material availabilityb. Core shapes available (Toroids are preferred becausethey have the highest μr and square BH characteristic)c. Manufacturing costs(17)with T period depending upon core T1tsi storage time:http://onsemi.com9

AN1543/Dto saturate the core because, in this case, the current will bemuch higher than the expected one. On the other hand, it’s notvery easy to anticipate all of the tolerance at this point of thedesign; therefore, as a rule of thumb, the first pass can bemade by using IP/2 to compute the oscillator.From the toroid data book provided by LCC, let us try theFT6.3 toroid (external diameter 6.30 mm) with IP halfIC peak:The typical B/H curves given in Figure 17 are provided bythe manufacturers of cores for the different material theymay propose in their portfolio of products. Most of the time,the data sheets show the upper side of the curves, thecharacteristic being absolutely symmetrical on the X axis.On the other hand, the shape of the curve, i.e. the Bsatvalue, can be controlled by using an air gap to increase thereluctance of the core. Of course, this is not possible for thetoroidal cores.BNP IE * HSIPNP 1.60 * 0.400.35NP 1.82 turnUsing the next available toroid, a FT10 (external diameter 10 mm)NON SATURABLE MATERIAL:MAINLY USED TO BUILDOUTPUT TRANSFORMERS.HNP NP 2.85 turnsSATURABLE MATERIAL, WITH ASQUARE B/H CHARACTERISTIC,USEFUL TO BUILD OSCILLATORS.The selection of a core from the ‘off the shelf’ standardproducts (see the preferred models given in Table 2, dependsupon the expected frequency, the cost, and the availability.As an example, let us select the T10 toroid with the A4ferrite material, the μr being higher than 6000. To simplifythe manufacture of this transformer we will make a firstiteration with NP 3 turns, assuming VP 1 V across theprimary.The characteristic curves of this core show that thesaturation flux is 510 mT at room temperature (T 25 C),the cross sectional area being 0.08 cm2.These parameters yield a theoretical operating frequencyof:Note:Drawing is not to scale.Figure 17. Typical B/H CurvesTo build the transformer, one can either use the dataprovided by the manufacturers of the cores, using theB f(H) curves, or pre define the type of core that would bestfit the application.This can be derived from Equation 18, which gives theminimum electromagnetic field needed to saturate a givencore:NP * IPHS IEF (18)Using, as a first analysis, a storage time of 5.5 μs for thepower transistors, as given by the data sheet, the practicalON time (ton) per switch will be:IP current into NPIE effective core perimeter in cm1ton ) 5.5 * 1062 * 20424Since HS must be higher than HO (the intrinsic fieldsustainable by the material as defined by the data sheet), thenone can compute the perimeter of the core, assuming a givennumber of turns, by rearranging Equation 8:NP * IPHS1 * 1044 * 3 * 0.51 * 0.08F 20424 Hzwith HS saturation field in A/cmNP number of turns on the primary:IE 2.50 * 0.400.35ton 29.98 μsyielding a typical operating frequency of:F 1/(2*ton)(18a)F 1/(2*29.98*10 6) 16677 HzOf course, in order to end up with lower cost, it’spreferable to use a standard core and to run several iterationsof the above equation, using NP as a variable.Since the current keeps increasing during the storage timeof the transistor, one cannot use the calculated IC peak valueThis is below the expected operating frequency asspecified above.Performing the same analysis with the FT6.3 toroid yieldsa typical operating frequency of 53 kHz, with NP 2 turns,http://onsemi.com10

AN1543/Da value well within the expected range. This toroid will bethe final choice for this design.For a 220 V nominal line, this yields:V(BR)CEO u 230 * 1.15 * Ǹ2V(BR)CEO 374 VTable 2.Popular Available ToroidsToroidFT6.3FT10FT16Ext. Dia.mm6.3010.0016IEcm1.602.504.00Since such a value is not available as a standard device, itis recommended that the designer use a 400 V ratedtransistor.It is worthwhile to point out that, assuming thefreewheeling diodes are properly selected (fast or ultra fasttype), the voltage across Collector Emitter junction of eachtransistor shall not exceed the VCC supply, limiting theRBSOA(2) operation within this voltage limit.However, a simple low cost converter doesn’t provide awell regulated VCC supply and, under transient conditions,the DC voltage can rise well above the expected maximumvalue. Depending upon the input network

spectrum, the higher efficiency brought by the electronic control of these lamps make them the best choice to save the energy absorbed by the lighting systems. A few years ago, the lack of reliable and efficient power . ballast concepts and gives the design rules to build