Figure 9-1 Block Diagram Of Static RAM Table 9-1 Truth .
Figure 9-1 Block Diagram of Static RAMTable 9-1 Truth Table for Static RAMAddressn2n wordby m bitsstaticRAMCSOEWEmDatainput / outputModeI/O pinsCSOEWEHXXnot selectedhigh-ZLHHoutput disabledhigh-ZLLHreaddata outLXLwritedata inFigure 9-2 Functional Equivalent of a Static RAM CellData InSELWRDGQData Out G 1 Q follows DG 0 data is latched
Figure 9-3 Block Diagram of 6116 Static RAMA10RowDecoderMemory Matrix128 X 128A4I/O 7I/O 0OEWECSInputDataControlColumn I/OColumn DecoderA3 A2 A1 A0
Figure 9-4 Read Cycle Timingt RCAddresst OHDoutt AAprevious data validtOHdata valid(a) with CS 0, OE 0, WE 1CStACStCHZtCLZDoutdata valid(b) with address stable, OE 0, WE 1
Table 9-2 Timing Specifications for Two Static CMOS RAMsParameterSymbolRead Cycle TimeAddress Access TimeChip Select Access TimeChip Selection to Output in Low ZOutput Enable to Output ValidOutput Enable to Output in Low ZChip deselection to Output in high ZChip Disable to Output in High ZOutput Hold from Address ite Cycle TimeChip Selection to End of WriteAddress Valid to End of WriteAddress Set Up TimeWrite Pulse WidthWrite Recovery TimeWrite Enable to Output in High ZData Valid to End of WriteData Hold from End of WriteOutput Active from End of *35010*estimated value, not specified by 1501503*1200––––––10–––
Figure 9-5 WE-controlled Write Cycle Timing (OE 0)tWCAddresstCWtWRCStAWtWPWEtASt WHZtOWDouttDWDintDHvalid dataregion (a)
Figure 9-6 CS-Controlled Write Cycle Timing (OE 0)tWCAddresst ASt CWtWRCSt AWWE(high - Z)Doutt DWDinold data or high - Zt DHnew data
Figure 9-7 Simple Memory Modellibrary IEEE;use IEEE.std logic 1164.all;library BITLIB;use BITLIB.bit pack.all;entity RAM6116 isport(Cs b, We b: in bit;Address: in bit vector(7 downto 0);IO: inout std logic vector(7 downto 0));end RAM6116;architecture simple ram of RAM6116 istype RAMtype is array(0 to 255) of std logic vector(7 downto 0);signal RAM1: RAMtype: (others (others '0'));-- Initialize all bits to '0'beginprocessbeginif Cs b '1' then IO "ZZZZZZZZ";-- chip not selectedelseif We b'event and We b '1' then-- rising-edge of We bRAM1(vec2int(Address'delayed)) IO;-- writewait for 0 ns;-- wait for RAM updateend if;if We b '1' thenIO RAM1(vec2int(Address));-- readelse IO "ZZZZZZZZ";-- drive high-Zend if;end if;wait on We b, Cs b, Address;end process;end simple ram;
Figure 9-8 Block Diagram of RAM SystemData Busld dataDataRegisteren datainc dataWEMemoryControladdressinc addrMARFigure 9-9 SM Chart of RAM SystemS0S2ld dataWEen datainc addrS1inc dataS3addr 8ydonen
Figure 9-10(a) Tester for Simple Memory Modellibrary ieee;use ieee.std logic 1164.all;library bitlib;use bitlib.bit pack.all;entity RAM6116 system isend RAM6116 system;architecture RAMtest of RAM6116 system iscomponent RAM6116 isport(Cs b, We b: in bit;Address: in bit vector(7 downto 0);IO: inout std logic vector(7 downto 0));end component RAM6116;signal state, next state: integer range 0 to 3;signal inc adrs, inc data, ld data, en data, Cs b, clk,signal We b: bit : '1';signal Data: bit vector(7 downto 0);signal Address: bit vector(7 downto 0);signal IO: std logic vector(7 downto 0);done: bit;-- initialize to read mode-- data register-- address register-- I/O busbeginRAM1: RAM6116 port map(Cs b, We b, Address, IO);control: process(state, Address)begin--initialize all control signals (RAM always selected)ld data '0'; inc data '0'; inc adrs '0'; en data '0';done '0'; We b '1'; Cs b '0';
Figure 9-10(b) Tester for Simple Memory Model--start SM chart herecase (state) iswhen 0 ld data '1'; next state 1;when 1 inc data '1'; next state 2;when 2 We b '0'; en data '1'; inc adrs '1';when 3 if (Address "00001000") then done '1';else next state 0;end if;end case;end process control;-- The following process is executed on the rising edge of a clock.register update: processbeginwait until clk '1';state next state;if (inc data '1') then data int2vec(vec2int(data) 1,8); end if;if (ld data '1') then data To bitvector(IO); end if;if (inc adrs '1') thenAddress int2vec(vec2int(Address) 1,8) after 1 ns;-- delay added to allow completion of memory writeend if;end process register update;-- Concurrent statementsclk not clk after 100 ns;IO To StdLogicVector(data) when en data '1' else "ZZZZZZZZ";end RAMtest;
Figure 9-11(a) VHDL Timing Model for 6116 Static CMOS RAM-- memory model with timing (OE b 0)library ieee;use ieee.std logic 1164.all;library bitlib;use bitlib.bit pack.all;entity static RAM isgeneric (constant tAA: time : 120 ns;-- 6116 static CMOS RAMconstant tACS:time : 120 ns;constant tCLZ:time : 10 ns;constant tCHZ:time : 10 ns;constant tOH:time : 10 ns;constant tWC:time : 120 ns;constant tAW:time : 105 ns;constant tWP:time : 70 ns;constant tWHZ:time : 35 ns;constant tDW:time : 35 ns;constant tDH:time : 0 ns;constant tOW:time : 10 ns);port (CS b, WE b, OE b: in bit;Address: in bit vector(7 downto 0);Data: inout std logic vector(7 downto 0) : (others 'Z'));end Static RAM;architecture SRAM of Static RAM istype RAMtype is array(0 to 255) of bit vector(7 downto 0);signal RAM1: RAMtype : (others (others '0'));
Figure 9-11(b) VHDL Timing Model for 6116 Static CMOS RAMbeginRAM: processbeginif (rising edge(WE b) and CS b'delayed '0')or (rising edge(CS b) and WE b'delayed '0') thenRAM1(vec2int(Address'delayed)) to bitvector(Data'delayed); -- writeData transport Data'delayed after tOW;-- read back after write-- Data'delayed is the value of Data just before the rising edgeend if;if falling edge(WE b) and CS b '0' then-- enter write modeData transport "ZZZZZZZZ" after tWHZ;end if;if CS b'event and OE b '0' thenif CS b '1' then-- RAM is deselectedData transport "ZZZZZZZZ" after tCHZ;elsif WE b '1' then-- readData "XXXXXXXX" after tCLZ;Data transport to stdlogicvector(RAM1(vec2int(Address)))after tACS;end if;end if;if Address'event and CS b '0' and OE b '0' and WE b '1' then --readData "XXXXXXXX" after tOH;Data transport to stdlogicvector(RAM1(vec2int(Address)))after tAA;end if;wait on CS b, WE b, Address;end process RAM;
Figure 9-11(c) VHDL Timing Model for 6116 Static CMOS RAMcheck: processbeginif NOW / 0 ns thenif address'event thenassert (address'delayed'stable(tWC)) -- tRC tWC assumedreport "Address cycle time too short" severity WARNING;end if;-- The following code only checks for WE b controlled write:if rising edge(WE b) and CS b'delayed '0' thenassert (address'delayed'stable(tAW))report "Address not valid long enough to end of write"severity WARNING;assert (WE b'delayed'stable(tWP))report "Write pulse too short"severity WARNING;assert (Data'delayed'stable(tDW))report "Data setup time too short"severity WARNING;wait for tDH;assert (Data'last event tDH)report "Data hold time too short"severity WARNING;end if;end if;wait on WE b, address, CS b;end process check;end SRAM;
Figure 9-12(a) VHDL Code for Testing the RAM Timing Modellibrary IEEE;use IEEE.std logic 1164.all;library BITLIB;use BITLIB.bit pack.all;entity RAM timing tester isend RAM timing tester;architecture test1 of RAM timing tester iscomponent static RAM isport (CS b, WE b, OE b: in bit;Address: in bit vector(7 downto 0);Data: inout std logic vector(7 downto 0));end component Static RAM;signal Cs b, We b: bit : '1';-- active low signalssignal Data: std logic vector(7 downto 0) : "ZZZZZZZZ";signal Address: bit vector(7 downto 0);
Figure 9-12(b) VHDL Code for Testing the RAM Timing ModelbeginSRAM1: Static RAM port map(Cs b, We b, '0', Address, Data);processbeginwait for 100 ns;Address "00001000";-- write(2) with CS pulseCs b '0'; We b transport '0' after 20 ns;Data transport "11100011" after 140 ns;Cs b transport '1' after 200 ns;We b transport '1' after 180 ns;Data transport "ZZZZZZZZ" after 220 ns;wait for 200 ns;Address "00011000";wait for 200 ns;-- RAM deselectedAddress "00001000";Cs b '0';wait for 200 ns;Address "00010000";Cs b '1' after 200 ns;wait for 200 ns;-- Read cyclesAddress "00011000";wait for 200 ns;end process;end test1;-- RAM deselected
Figure 9-13 Test Results for RAM Timing Model/address 000000000001100000001000/cs b/we b/data ZZZZZZZZXXXXXXXXZZZZZZZZ11100011ZZZZZZZZ(a) Write cycle/address000100000000100000011000/cs b/we b/dataXXXXXXXX11100011XXXXXXXX(b) Two read cycles00000000
Figure 9-14 Microprocessor Bus morySystem
Figure 9-15 Intel 486 Basic 2-2 Bus CPUREADFROMCPUWRITETOCPUREADFROMCPUWRITE
Figure 9-16 Intel 486 Basic 3-3 Bus DFROM CPUWRITETi
Figure 9-17 Simplified 486 Bus Interface Uniti486 bus interface al w data[31:0]32w data[31:0]dbus[31:0]r data[31:0]32r data[31:0]internal bus interface3232
Figure 9-18 SM Chart for Simplified 486 Bus InterfaceT1Tiabus new addressdbus high-ZAds '0'W/R wrDonedbus high-ZT20br1abus same addressAds '1'0{read}1Rdywr1{write}dbus data from CPU00stddata to CPU dbusRdyDone0br11
Figure 9-19 486 Setup and Hold Time SpecificationsTxTxCLKt16t17t22t23RDYDATATx
Figure 9-20486 Bus Timing Specifications for Address and Data ChangesTxTxCLKt 6 minTxt 6 maxAddress, Ads, W/R VALID nVALID n 1t 10 maxt 10 minData (Write)(successive cycles) VALID nt 10 minData (Write)to High-ZVALIDVALID n 1t 11
Figure 9-21(a) VHDL Model for 486 Bus Interface UnitLIBRARY ieee;use ieee.std logic 1164.all;entity i486 bus isgeneric (-- These specs are for the i486DX 50constant t6 max:time: 12 ns;constant t10 min:time: 3 ns;constant t10 max:time: 12 ns; constant t11 max:time: 18 ns;constant t16 min:time: 5 ns;constant t17 min:time: 3 ns;constant t22 min:time: 5 ns;constant t23 min:time: 3 ns);port (--external interfaceabus: out bit vector(31 downto 0);dbus: inout std logic vector(31 downto 0) : (others 'Z');w rb, ads b: out bit : '1'; rdy b, clk: in bit;--internal interfaceaddress, w data: in bit vector(31 downto 0);r data: out bit vector(31 downto 0); wr, br: in bit; std, done:out bit);end i486 **********************architecture simple 486 bus of i486 bus istype state t is (Ti, T1, T2);signal state, next state:state t: *********************begin-- The following process outputs the control signals and address of the processor during a-- read/write operation. The process also drives or tristates the databus depending on the-- operation type. During the execution of a read/write operation, the done signal is low.-- When the bus is ready to accept a new request, done is high.comb logic: process
Figure 9-21(b) VHDL Model for 486 Bus Interface Unitbeginstd '0';case (state) iswhen Ti done '1';if (br '1') then next state T1;else next state Ti;end if;dbus transport (others 'Z') after t10 min;when T1 done '0';ads b transport '0' after t6 max; w rb transport wr after t6 max;abus transport address after t6 max;dbus transport (others 'Z') after t10 min; next state T2;when T2 ads b transport '1' after t6 max;if (wr '0') then-- readif (rdy b '0') thenr data to bitvector(dbus); std '1'; done '1';if (br '0') then next state Ti;else next state T1;end if;else next state T2;end if;else -- writedbus transport to stdlogicvector(w data) after t10 max;if (rdy b '0') thendone '1';if (br '0') then next state Ti;
Figure 9-21(c) VHDL Model for 486 Bus Interface Unitelse next state T1;end if;else next state T2;end if;end if;end case;wait on state, rdy b, br, dbus;end process comb ************************--The following process updates the current state on every rising clock edgeseq logic: process(clk)beginif (clk '1') then state next state; end if;end process seq ************************--The following process checks that all setup and hold times are met for all incoming control-- signals. Setup and hold times are checked for the data bus during a read only.wave check: process (clk, dbus, rdy b)variable clk last rise:time: 0 ns;beginif (now / 0 ns) thenif clk'event and clk '1' then-- check setup times--The following assert assumes that the setup for RDY-- is equal to or greater than that for dataassert (rdy b / '0') OR (wr / '0') OR(dbus'last event t22 min)report "i486 bus:Data setup too short"
Figure 9-21(d) VHDL Model for 486 Bus Interface Unitseverity WARNING;assert (rdy b'last event t16 min)report "i486 bus:RDY setup too short"severity WARNING;clk last rise : NOW;end if;if (dbus'event) then-- check hold times-- The following assert assumes that the hold for RDY-- is equal to or greater than that for dataassert (rdy b / '0') OR (wr / '0') OR(now - clk last rise t23 min)report "i486 bus:Data hold too short"severity WARNING;end if;if (rdy b'event) thenassert (now - clk last rise t17 min)report "i486 bus: RDY signal hold too short"severity WARNING;end if;end if;end process wave check;end simple 486 bus;
Figure 9-22 486 Bus Interface to Static Ram SystemCPU (or Tester)memory controlleri486 bus interface 2address[31:0]abus[31:0]w data[31:0]32w data[31:0]dbus[31:0]32r data[31:0]WEW/RAdsCSRdyRdybrr data[31:0]clk32CS1abus[31:0]3215address decoder32158158data[31:24] addr[14:0]data[23:16] SWE8data[7:0]Ram1OECSWE15addr[14:0]Ram0OECSWEOE
Figure 9-23 Signal Paths for Memory 1MemoryControllertACStAAMemoryDataout
Figure 9-24 Memory Controller SM Chart for Read Cyclesbus state Ti or T1S0/1Ads01CS10CSS1/ CSS2/CS Rdybus state first T2bus state second T2
Figure 9-25 Chip Select Timing for Write to RAM20nsbus stateT1T212nst 10maxT212nst DWTxt 10min (3ns)VALIDdata to RAMCS (a)4nsCS (b)t cc 4nst cc 3ns
Figure 9-26 SM Chart of Memory Controllerbus state Ti or T1S0/1Ads01bus state second T2S2/wr0CSRdy0bus state first T2S1/CS1CS1
Figure 9-27(a) VHDL Code for Memory Controller-- Memory Controller for fast CMOS SRAM w/ one wait stateentity memory control isport(clk, w rb, ads b, cs1: in bit;rdy b, we b, cs b: out bit : '1');end memory control;architecture behave1 of memory control isconstant delay: time : 5 ns;signal state, nextstate: integer range 0 to 2;signal new we b, new cs b, new rdy b: bit : '1';
Figure 9-27(b) VHDL Code for Memory Controllerbeginprocess(state,ads b,w rb,cs1)beginnew cs b '1'; new rdy b '1'; new we b '1';case state iswhen 0 if ads b '0' and cs1 '1' then nextstate 1;else nextstate 0;end if;when 1 new cs b '0'; nextstate 2;when 2 if w rb '1' then new cs b '1';else new cs b '0';end if;new rdy b '0'; nextstate 0;end case;end process;process(clk)beginif clk '1' then state nextstate; end if;end process;we b not w rb after delay;cs b new cs b after delay;rdy b new rdy b after delay;end behave1;
Figure 9-28(a) VHDL Code for 486 Bus System Test Module-- Tester for Bus modellibrary BITLIB;use BITLIB.bit pack.all;use std.textio.all;entity tester isport ( address, w data: out bit vector(31 downto 0);r data: in bit vector(31 downto 0);clk, wr, br: out bit;std, done: in bit : '0');end tester;architecture test1 of tester isconstant half period: time : 10 ns;-- 20 ns clock periodsignal testclk: bit : '1';begintestclk not testclk after half period;clk testclk after 1 ns;-- Delay bus clockread test file: process(testclk)file test file: text open read mode is "test2.dat";variable buff: line;variable dataint, addrint: integer;variable new wr, new br: bit;
Figure 9-28(b) VHDL Code for 486 Bus System Test Modulebeginif testclk '1' and done '1' thenif std '1' thenassert dataint vec2int(r data)report "Read data doesn't match data file!"severity error;end if;if not endfile(test file) thenreadline(test file, buff);read(buff, new br);read(buff, new wr);read(buff, addrint);read(buff, dataint);br new br;wr new wr;address int2vec(addrint,32);if new wr '1' and new br '1' thenw data int2vec(dataint,32);else w data (others '0');end if;end if;end if;end process read test file;end test1;
Figure 9-29(a) VHDL Code for Complete 486 Bus System with Static RAMlibrary IEEE;use IEEE.std logic 1164.all;entity i486 bus sys isend i486 bus sys;architecture bus sys bhv of i486 bus sys *************************************component i486 busport (--external interfaceabus: out bit vector(31 downto 0); dbus: inout std logic vector(31 downto 0);w rb, ads b: out bit; rdy b, clk: in bit;--internal interfaceaddress, w data: in bit vector(31 downto 0);r data: out bit vector(31 downto 0); wr, br: in bit; std, done:out bit);end component;component static RAMgeneric (constant W: time);port (CS b, WE b, OE b: in bit;Address: in bit vector(7 downto 0); Data: inout std logic vector(7 downto 0));end component;component memory controlport(clk, w rb, ads b, cs1: in bit;rdy b, we b, cs b: out bit);end component;
Figure 9-29(b) VHDL Code for Complete 486 Bus System with Static RAMcomponent testerport (address, w data: out bit vector(31 downto 0);r data: in bit vector(31 downto 0);clk, wr, br: out bit;std, done: in bit);end ******************************constant decode delay: time : 5 ns;constant addr decode: bit vector(31 downto 8) : (others '0');signal cs1: bit;-- signals between tester and bus interface unitsignal address, w data, r data: bit vector(31 downto 0);signal clk, wr, br, std, done: bit;-- external 486 bus signalssignal w rb, ads b, rdy b: bit;signal abus: bit vector(31 downto 0);signal dbus: std logic vector(31 downto 0);-- signals to RAMsignal cs b, we b: ****************
Figure 9-29(c) VHDL Code for Complete 486 Bus System with Static RAMbeginbus1: i486 bus port map (abus, dbus, w rb, ads b, rdy b, clk, address,w data, r data, wr, br, std, done);control1: memory control port map (clk, w rb, ads b, cs1, rdy b, we b, cs b);RAM32: for i in 3 downto 0 generateram: static RAMgeneric map(25 ns,25 ns,3 ns,3 ns,3 ns,25 ns,15 ns,15 ns,10 ns,12 ns,0 ns,0 ns)port map(cs b, we b, '0', abus(7 downto 0), dbus(8*i 7 downto 8*i));end generate RAM32;test: tester port map(address, w data, r data, clk, wr, br, std, **************************-- Address decoder signal sent to memory controllercs1 '1' after decode delay when (abus(31 downto 8) addr decode)else '0' after decode **************************end bus sys bhv
Table 9-3 Test Data for 486 Bus Systembr0111101111wr1110000101addr Data723139 4863255 19283139 4863255 1928359743139 486313989513989524830Bus actionIdleWriteWriteReadReadIdleReadWriteReadBus hang
Figure 9-30. Test results for 486 bus system/clk/address 0/w data 07139255139486319283025559139895/r data 0/br48631928304863/wr/done/std/cs1/w rb/ads b/rdy b/abus 0/dbus Z1392554863Z13919283Z255X4863 Z139X19283 ZX4863 Z895/cs b/we b0100200300400Z
Figure 9-1 Block Diagram of Static RAM Table 9-1 Truth Table for Static RAM Mode I/O pins H X X not selected high-Z L H H output disabled high-Z L L H read data out L X L write data in Figure 9-2 Functional Equivalent of a Static RAM Cell 2n word by m bits static RAM n Address CS
WIRING DIAGRAM DIRECTORY WARNING: Wiring direct to battery not recommended. Install actuator after ignition switch, or master power switch. Diagram 1 Diagram 2 Diagram 3 Diagram 4 Diagram 5 Diagram 6 Diagram 7 Diagram 8 Diagram 9 Diagram 10 Diagram 11 Diagram 12 Diagram 13 Diagram 14 Diagram 15 On/Off, 12VDC, 3-wire/3-pin, SPST On/Off, 12VDC, 3 .
Figure 2: A sequence diagram that has incoming and outgoing messages Notice that in Figure 2 the diagram's label begins with the letters "sd," for Sequence Diagram. When using a frame element to enclose a diagram, the diagram's label needs to follow the format of: Diagram Type Diagram Name UML basics: The sequence diagram Page 3 of 24 http .
the UV lamp and Table 1 shows its specification. Figure 6 shows the circuit diagram for driving the motor. FIGURE 3. Conventional UV illuminator side-view block diagram BCD FIGURE 2. Conventional UV illuminator top-view block diagram B FIGURE 1. The smallest Gel Doc block diagram A FIGURE 4. Proposed UV illu
Snatch Block, Shackle 6:24 Snatch Block, Hook 6:24 Snatch Block, others (page 6:29) 6:25 Tilt Wall Block 6:26 Oilfield Blocks 6:27 - 6:30 Tubing Block 6:27 Manhandler Block 6:28 Derrick Block 6:28 Laydown Block 6:29 Tong Line Block 6:30 Hay Fork Pulley 6:30 Guyline Block 6:30 J-Latches 6:31 T
3.2 Block Diagram Figure 6 and Figure 7 show the block diagrams of the DRV solutions. Figure 6. PGA460 and DRV8870 Bi-Static Block Diagram Figure 7. PGA460 and DRV8870 Mono-Static Block Diagram Considering that the PGA460 is limited to a 30-V supp
Structured analysis Object-oriented analysis System boundary Context diagram Use case diagram Functionality Data flow diagram Activity diagram Interaction diagrams Data Entity-relationship diagram Class diagram Object diagram Control State diagram State diagram Structured methods System as a set of nested processes accessing system data.
Note: The diagram shown above is for reference only. Use the instructions beginning on the next page to draw your Package diagram. Creating a Package Diagram from the Use Case Diagram The package diagram is a type of class diagram and can be created from a use case diagram. 1. Make sure the Use Case diagram c
v luswishi farm block investment profile: zambia figure 5: agricultural growth rates (2004–17) 11 figure 6: planned farm block locations 15 figure 7: luswishi farm block location map 16 figure 8: agroec- olocgazon li es 71 figure 9: luswishi farm block land allocation 18 figure 10: proposed road network 20 figure 11: proposed 66kv and 33kv electricity lines
