Field Programmable Gate Array Testing

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Chapter 12Field Programmable Gate Array Testing1EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 1

What is this chapter about? Field Programmable Gate Arrays (FPGAs) Have become a dominant digital implementationmedia Reconfigurable to implement any digital logicfunction Focus on Testing challenges due to programmability andcomplexity Overview of testing approaches Test and diagnosis of various resources New frontiers in FPGA testing2EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 2

FPGA Testing Overview of FPGAs Architecture, Configuration, & Testing ProblemTesting Approaches BIST of Programmable Resources Logic Resources– Logic Blocks, I/O Cells, & Specialized Cores– Diagnosis Routing ResourcesEmbedded Processor Based Testing Concluding Remarks 3EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 3

Field Programmable Gate ArraysConfigurationMemory ProgrammableLogic Blocks(PLBs) ProgrammableInput/Output Cells ProgrammableInterconnect Typical Complexity 5 million – 1 billion transistors4EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 4

Basic FPGA Operation Writing configurationmemory (configuration) defines system function Input/Output Cells Logic in PLBs Connections betweenPLBs & I/O cellsChanging configurationmemory data(reconfiguration) changes system function Can change at anytime Even while systemfunction is in operation– Dynamic 01010101010101010010010015EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 5

FPGA Architectures Early FPGAs NxN array of unit cells– Unit cell CLB routing Special routing along center axes I/O cells around perimeter Next Generation FPGAs MxN array of unit cells Added small block RAMs at edges PCMore Recent FPGAs Added larger block RAMs in array Added multipliers Added Processor Cores (PC) PCPCLatest FPGAs Added DSP cores w/multipliers I/O cells along columns for BGAEE141System-on-ChipTest ArchitecturesPC6Ch. 12 - FPGA Testing - P. 6

Combinational Logic Functions Gatesare combined tocreate complex circuits Multiplexer example If S 0, Z AIf S 1, Z BCommon digital circuitHeavily used in FPGAs– Select input (S) controlledby configuration memorybitASZBTruth tableSAB Z000 0001 0010 1011 1100 0101 1110 0111 1Logic symbolAB0Z10S17EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 7

Look--up TablesLookUsing multiplexerexample Configurationmemory holdstruth table Input signalsconnect to selectinputs ofmultiplexers toselect outputvalue of truthtable for anygiven input value Multiplexer00A01B01Z1S01110001Z10101100111B0ATruth tableSAB Z000 0001 0010 1011 1100 0101 1110 0111 11S8EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 8

Basic PLB Structure Look-uptable (LUT) for combinational logic Store truth table in LUT (typically 3 to 6 inputs) Some LUTs can also act as RAM/shift register Flip-flopsfor sequential logic Programmable clock enable, set/reset Speciallogic Large logic functions with Shannon expansion Fast carry for adders and counterscarry outInput[1:4]4LUT/RAMControlclock, enable, set/resetEE141System-on-ChipTest Architectures3Carry &ControlLogiccarry inFlip-flop/LatchOutputQ output9Ch. 12 - FPGA Testing - P. 9

Look--up Table Based RAMsLookEE141System-on-ChipTest ArchitecturesAddress DecoderLUT mode Data In en0performs readen1operationsen2 Address decoderIn0en3In1with write enableIn2en4generates loaden5signals to latchesfor write operationsen6en7 Small RAMs butWritecan be combined Enablefor larger RAMsWrite Address Normal00010101110001Z01110011In0In1In2Read Address10Ch. 12 - FPGA Testing - P. 10

Input/Output Cells Bi-directionalbuffers Programmable for input or output signals Tri-state control for bi-directional operation Flip-flops/latches for improved timing– Set-up and hold times– Clock-to-output delay Pull-up/down resistors RoutingresourcesTri-state Controlto/frominternal Output DataroutingresourcesInput Data Connections to core of array ProgrammableBidirectionalPadBufferI/O voltage & current levels11EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 11

Interconnect Network Wiresegments of varying length xN N PLBs in length– Typical values of N 1, 2, 4, 6, 8Wire Aconfigbit Long linesWire B– xH half the array in length– xL full array in length ProgrammableInterconnect Points (PIPs) Transmission gate connects to 2 wire segments– Controlled by configuration memory bit Four basic types of PIPs12EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 12

Programmable Interconnect Points Break-point PIP Connect or isolate 2 wire segments Cross-point PIP 2 nets straight through 1 net turns corner and/or fans out Compound cross-point PIP Collection of 6 break-point PIPs– Can route 2 isolated signal nets Multiplexer PIP Directional and buffered Main routing resource in recent FPGAs Select 1-of-N inputs for output– Decoded MUX PIP – N configuration bits select from 2N inputs– Non-decoded MUX PIP – 1 configuration bit per input13EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 13

Recent Architectural Trends Addition of specialized cores: Memories– Single and dual-port RAMs– FIFO (first-in first-out)– ECC (error correcting codes) Digital signal processors (DSPs)– Multipliers– Accumulators– Arithmetic/logic units (ALUs) Embedded processors– Hard core (dedicated processors) With dedicated program/datamemoriesOtherwise, programmable RAMs inFPGA used for program/datamemories PLBs routing resources special cores I/O cells– Soft core (synthesized from a HDL)14EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 14

FPGA Resources Types and sizes of resources vary with FPGA family Example: LUTs vary from 3-input to 6-input– 4-input LUTs are most common Typical ranges for some commercially available FPGAsFPGA ResourceLogicRoutingSpecializedCoresOtherSmall FPGA Large FPGAPLBs per FPGA25625,920LUTs and flip-flops per PLB18Wire segments per PLB45406PIPs per PLB1393,462Bits per memory core12836,864Memory cores per FPGA16576DSP cores0512Input/output cells621,200Configuration memory bits42,10479,704,832EE141System-on-ChipTest Architectures15Ch. 12 - FPGA Testing - P. 15

Configuration Interfaces Master mode (Serial or Parallel options) FPGA retrieves configuration from ROM at power-up Slave (Serial or Parallel options) FPGA configured by external source (i.e., a µP) Used for dynamic partial reconfiguration Boundary Scan Interface 4-wire IEEE standard serial interface for testingWrite and read access to configuration memoryInterfaces to FPGA core internal routing networkNot available in all FPGAsclockPROM withConfig Datadata outCCLKCCLKFPGA inMaster ModeDinDoutCCLKFPGA inSlave ModeDinDoutFPGA inSlave ModeDinDout16EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 16

FPGA Configuration Memory PLBaddressable Good for partial reconfiguration X-Y coordinates of PLB location to be written– “Z” coordinate identifies whichresources will be configured Frameaddressable Vertical or horizontal frame– Vertical frames most common Access to all PLBs in frame– Only portion of logic and routingresources accessible in a given frame– Many frames required to configure PLBs & routing17EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 17

Configuration Techniques Full configuration & readback Simple configuration interface– Automatic internal calculation of frame address Long download time for large FPGAs Partial reconfiguration & readback Only change portions of configuration memory withrespect to reference design– Reduces download time for reconfiguration Requires a more complicated configuration interface– Command Register (CMR)– Frame Length Register (FLR)– Frame Address Register (FAR)– Frame Data Register (FDR)18EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 18

Configuration Techniques Compressedconfiguration Requires multiple frame write capability– Write identical frames of config data to multiple frameaddresses Extension of partial reconfiguration interfacecapabilities– Frame address is much smaller than frame ofconfiguration data Reduces download time for initial configurationdepending on– Regularity of system function design– % utilization of array Unused portions written with default configuration data19EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 19

FPGA Testing TaxonomyTest Approach AttributeTest pattern application andoutput response analysisInternal (BIST)ExternalSystem-level testingOff-lineOn-lineSystem applicationIndependentDependentLogicRoutingTarget programmable resources ClassificationPLBsI/O cells CoresLocalGlobalOn-line test while system is operational Off-line test while system is out-of-service Application-dependent testing tests only thoseFPGA resources used by intended system function Application-independent testing tests all FPGA resources20EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 20

FPGA Test Configurations More test configurations required for routingresources than for logic resources Data below from publications on actual testconfiguration implementations in commercial FPGAsFPGAVendorNumber of Test amovici 2001][Stroud 2002b]AtmelAT40K/AT94K4563[Sunwoo 2005]CypressDelta39K2041911[Stroud rtan-II1228311[Dhingra 2005]Virtex-415?15[Milton 2006]LatticeXilinxRouting CoresReference[Stroud 2003]21EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 21

A Simple PLB Architecture Two 3-input LUTs Can implement any 4-inputcombinational logic function Can implement full adder– Carry in LUT C– Sum in LUT S 1 flip-flop 22 configurationmemory bitsD2D2-0LUTLUT C8x1D2D2-03C6C5C4C3C2C1C0111 110 101 100 011 010 001 000outCoutSmuxSOmux0 Sout101LUT S8x1 Programmable:– Active levels– Clock edge– Set/resetC7D301CB5CEmuxCB3Clock EnableSRmux01CB4FFSet/ResetClock 8 per LUT– C7-C0 and S7-S0CBCB0CB1CB2 ConfigurationMemory Bit 6 control bits– CB5-CB022EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 22

Test Configurations for Simple PLB All configuration memory bits must be tested for bothlogic values (0 and 1) assuming exhaustive input patterns Output effects for each logic value must be observed Exclusive-OR (XOR) and exclusive-NOR (XNOR)functions are good for testing LUTs Put opposite functions in adjacent LUTs to produce opposite logicvalues at inputs to subsequent logic functions Fault coverage results below are based on collapsedsingle stuck-at gate-level fault model (174 faults total)Configuration Bits Configuration #1 Configuration #2 Configuration #3LUT C (C7 - C0)XNOR (01101001)LUT S (S7 - S0)XOR (10010110)CB0 - CB5000010111110000001Individual FC149/174 85.6%149/174 85.6%108/174 62.1%Cumulative FC85.6%EE141System-on-ChipTest ArchitecturesXOR (10010110)XOR (10010110)XNOR (01101001) XNOR (01101001)97.7%100%23Ch. 12 - FPGA Testing - P. 23

BIST for FPGAs Basicidea: Program some logic resources to act as– Test pattern generators (TPGs)– Output response analyzers (ORAs)– Resources under test Logic resources as blocks under test (BUTs)Routing resources as wires under test (WUTs) Goal: Minimize number of test configurations tominimize download time– Download time dominates total test time24EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 24

TPG and ORA Implementations TPG implementation depends on test algorithm May be implemented in different resources (see table below) Multiple TPGs prevent faulty TPG from escaping detection Lower bound on number of PLBs per TPG, TPLB BIN NFF– BIN number of inputs to BUT– NFF number of FFs/PLB ORAs most efficiently implemented in PLBs Number of PLBs needed for ORAs, OPLB (NBUT BOUT) NFF– BOUT number of outputs from BUT– NBUT number of BUTsResource Under TestTPGsORAsPLBsPLBs or DSP coresPLBsLUT RAMsPLBs or DSP and RAM coresPLBsI/O cellsPLBs or DSP and RAM coresPLBsCores (memories, DSPs, ipTest Architectures25Ch. 12 - FPGA Testing - P. 25

TPG Algorithms Small logic functions (PLBs, IOBs) can be testedwith pseudo-random test patterns LFSRs or counting patterns Large logic functions (RAMs, DSPs) requirespecialized test algorithms for high fault coverage Below are examples of typical RAM test algorithmsAlgorithmMarch Test SequenceMarch Y (w0); (r0, w1,r1); (r1, w0, r0); (r0)March LRw/o BDS (w0); (r0, w1); (r1, w0, r0, r0, w1);March LRwith BDS (r1, w0); (r0, w1, r1, r1, w0); (r0) (w00); (r00, w11); (r11, w00, r00, r00, w11); (r11, w00); (r00, w11, r11, r11, w00); (r00, w01, w10, r10); (r10, w01, r01); (r01)Notation: w0 write 0 (or all 0’s), r1 read 1 (or all 1’s) address up, address down, address either wayEE141System-on-ChipTest Architectures26Ch. 12 - FPGA Testing - P. 26

Output Response Analyzers Comparison-based XOR with OR feedbackfrom flip-flopBUTj outputBUTk outputshift datashift mode– Latches mismatchesobserved due to faults Resultsretrieval ORA with shift registerBUTj outputBUTk output– Requires additional logic Configuration memoryreadback– Read contents of ORAflip-flops Good with partialconfiguration memoryreadback capabilitiesEE141System-on-ChipTest ArchitecturesPass/FailPass/FailBUTj output1BUTk output1BUTj outputnBUTk outputnPass/Fail27Ch. 12 - FPGA Testing - P. 27

Logic Resource BIST Architectures Basiccomparison Multiple TPGs drive alternatingcolumns (rows) of blocks undertest (BUTs) BUTs in center of array observedby 2 sets of ORAs and comparedwith 2 other BUTs BUTs along edges of arrayobserved by only 1 set of ORAs– Some loss of diagnostic resolutionBasic Comparison TPG ORA BUT Originally used to test PLBs– Later used to test specialized cores28EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 28

Logic Resource BIST Architectures CircularComparison Multiple TPGs drive alternatingcolumns (rows) of blocks undertest (BUTs) All BUTs observed by 2 sets ofORAs and compared with 2 otherBUTs– Good diagnostic resolution Originally used to test specializedcoresCircular Comparison TPG ORA BUT– Later used to test PLBs and I/O cells29EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 29

Logic Resource BIST Architectures Expected Results comparisonexpectedresultstestpatterns Multiple TPGs– One set of TPGs drive BUTs– Other set of TPGs produce expectedresults for comparison with outputs ofBUTsExpected Results BUTs observed by 1 set of ORAsand compared with expected resultsfrom TPGs– Simple diagnosis since failing ORAposition indicates faulty BUT Good when expected results can bealgorithmically generated easily TPG ORA BUT– Example: RAM test algorithms Originally used to test RAM coresEE141System-on-ChipTest Architectures30Ch. 12 - FPGA Testing - P. 30

Logic Resource Diagnostic Procedure1.2.3.4.Record ORA results; 1 failure indication.For every set of 2 or more consecutive ORAs with 0s, enter0s for all BUTs observed by these ORAs; the BUTs are faultfree.For every adjacent 0 and 1 followed by an empty space,enter 1 to indicate BUT is faulty; continue while such entriesexist.If an ORA indicates a failure but both BUTs monitored by theORA are fault-free, one of the following conditions exist:A.B.C.5.A fault in routing resources between one of the BUTs and the ORA,ORA is faulty, orThere are more than 2 consecutive BUTs with equivalent faults (forcircular comparison only); reorder circular comparison and repeat testand diagnostic procedure.Remaining BUTs marked as unknown may be faulty; reordercircular comparison or rotate basic comparison architectureby 90 , repeat test and diagnostic procedure.31EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 31

Diagnostic Procedure Examples Note that B4 and B5 have equivalent faults in Example ACircular comparison provides better diagnostic resolution Also indicates when more than 2 consecutive BUTs with equivalentfaults (Example C)Example AExample BExample CBIST rDiagnostic Step1 2 31 2 31 2 31 2 31 2 31 2 300 000 001 100 000 001 100 000 001 100 000 001 Test Architectures00000110 0 011 1 1?0 01 100 000000110110000000111 1 1?1 1 1?010 00 1 1 1 1 1 100 00 00 0 0 0 0 0 000 00 01 0 0 0 0 0 010 00 01 1 1 1 1 1 1 1 1110 01 1 1 0 0 1 0 0 00 010 00 0 0032 0 0Ch. 12 - FPGA Testing - P. 32

Testing Routing Resources Comparison-basedBIST approach Developed for on-line FPGA BISTTPG Testing restricted to routing resourcesWUTsfor 2 rows or 2 columns of PLBs Small Self-Test AReas (STARs) Comparison-based ORAORA Laterapplied to off-line BIST Fill FPGA with STARs Tests run concurrently Diagnostic resolution to STAR EasierBIST development But more BIST configurationsSTART T T T TFPGAO O O O O33EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 33

Testing Routing Resources TPGWUTsparitybitORAOriginal parity-based BIST approach Parity bit routed over fault-free resources– What is fault-free until you’ve tested it? Modified parity-based approach N-bit up-counter with even parity, and N-bit down-counter with odd parity– Gives opposite logic values for Stuck-on PIPs & bridging faults Parity used as test pattern– N 1 wires under test Good for small PLBs– like our simple PLB example Make STARs as small as possible Better diagnostic resolution Easier BIST developmentEE141System-on-ChipTest arC1C0WUTsORA 34Ch. 12 - FPGA Testing - P. 34

Testing Routing Resources Testing typically separated by routing resources Global - interconnects non-adjacent logic resources Local - interconnects adjacent logic resources andconnects logic resources to global routing Additional test configurations swap positions ofTPGs and ORAs to reverse direction of signal flowto test directional, buffered routing resources Multiplexer PIPs are a good example TPG ORAglobal routingEE141System-on-ChipTest Architectureslocal routingPLB feed-throughlocal routingadjacent PLBs35Ch. 12 - FPGA Testing - P. 35

Reducing Test Time Orient BIST architecture to configuration memory Align along rows/columns depending on FPGA structure Downloading BIST configurations Compressed configuration for initial download Partial reconfiguration for subsequent downloads– Reduce number of frames written between configurations Keep routing constant between BIST configurationsOptimize order of BIST configuration applicationRetrieving BIST results Partial configuration memory readback– Eliminates ORA logic for scan chain Allows concurrent testing of more resources– Minimize number of frames to be read Dynamic partial reconfiguration– Read BIST results after a series of BIST configurationsSlight loss in diagnostic resolutionEE141System-on-ChipTest Architectures 36Ch. 12 - FPGA Testing - P. 36

Embedded Processor Based BISTNew area of R&D in FPGA testing Basic idea: Embedded processor core– Hard or soft core Configures FPGA for BIST– Via internal configuration access port (ICAP) Alternative: download initial BIST configuration Executes BIST sequence BUT ORA– May provide TPG functionality Retrieves BIST results– May perform diagnostic procedure Reconfigures FPGA for subsequent BISTconfigurations Soft core requires two test sessions totest area occupied by processor coreduring first test sessionEE141System-on-ChipTest ArchitecturesProcessor core,TPGs and interfaceto ICAP circuitryTest session #1Processor core,TPGs and interfaceto ICAP circuitryTest session #237Ch. 12 - FPGA Testing - P. 37

Embedded Processor BIST Overall reduction in total test time Algorithmic reconfiguration faster than external download– 10 to 25 times faster– Results below from actual implementation in commercial FPGA Can be loaded into processor program memory foron-demand BIST and diagnosis of FPGA Good for fault-tolerant applications where system functionis reconfigured around diagnosed fault(s)ResourceFunctionDownloadExecutionTotal timeDownloadRoutingExecutionBISTTotal timeTotal Test TimeEE141System-on-ChipTest ArchitecturesPLBBISTExternal7.680 sec0.016 sec7.696 sec20.064 sec0.026 sec20.090 sec27.786 secProcessorSpeed-up0.101 sec76.00.085 sec0.20.186 sec41.40.110 sec182.40.343 sec0.0750.453 sec44.30.639 sec43.5 38Ch. 12 - FPGA Testing - P. 38

Concluding RemarksGrowing use of FPGAs in systems and SOCs FPGA testing is necessary but difficult due to ProgrammabilityComplex programmable interconnect networkConstantly growing size and changing architecturesIncorporation of new and different specialized coresTest & diagnosis allows fault-tolerant applications New FPGA capabilities assist in testing solutions Dynamic partial reconfiguration and readback Configuration/reconfiguration by embedded processorcores39EE141System-on-ChipTest ArchitecturesCh. 12 - FPGA Testing - P. 39

FPGA Resource Small FPGA Large FPGA Logic PLBs per FPGA 256 25,920 LUTs and flip -flops per PLB 1 8 System-on-Chip Test ArchitecturesEE141 Ch. 12 - FPGA Testing - P. 15 15 Routing Wire segments per PLB 45 406 PIPs per PLB 139 3,462 Specialized Cores Bits per memory core 128 36,864 Memory cores per FP

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