ISO 17987/LIN 2.x/SAE J2602 Transceiver

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TJA1027ISO 17987/LIN 2.x/SAE J2602 transceiverRev. 3 — 18 December 2018Product data sheet1. General descriptionThe TJA1027 is the interface between the Local Interconnect Network (LIN) master/slaveprotocol controller and the physical bus in a LIN network. It is primarily intended forin-vehicle sub-networks using baud rates up to 20 kBd and is compliant with LIN 2.0,LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 and ISO 17987-4:2016 (12 V). The TJA1027 ispin-compatible with the TJA1020, TJA1021, TJA1022, TJA1029 and MC33662(B).The transmit data stream generated by the protocol controller is converted by theTJA1027 into an optimized bus signal shaped to minimize ElectroMagnetic Emissions(EME). The LIN bus output pin is pulled HIGH via an internal termination resistor. For amaster application, an external resistor in series with a diode should be connectedbetween pin VBAT and pin LIN. The receiver detects a receive data stream on the LIN businput pin and transfers it via pin RXD to the microcontroller.Power consumption is very low in Sleep mode. However, the TJA1027 can still be wokenup via pins LIN and SLP N.2. Features and benefits2.1 GeneralLIN 2.x/ISO 17987-4:2016 (12 V)/SAE J2602 compliantBaud rate up to 20 kBdVery low ElectroMagnetic Emissions (EME)Very low current consumption in Sleep mode with remote LIN wake-upInput levels compatible with 3.3 V and 5 V devicesIntegrated termination resistor for LIN slave applicationsPassive behavior in unpowered stateOperational during cranking pulse: full operation from 5 V upwardsUndervoltage detectionK-line compatibleAvailable in SO8 and HVSON8 packagesLeadless HVSON8 package (3.0 mm 3.0 mm) with low thermal resistancesupporting Automated Optical Inspection (AOI) capability Dark green product (halogen free and Restriction of Hazardous Substances (RoHS)compliant) Pin-compatible subset of the TJA1020, TJA1021, TJA1022 and MC33662(B) Pin- and footprint-compatible with the TJA1029

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver2.2 Protection Very high ElectoMagnetic Immunity (EMI) Very high ESD robustness: 8 kV according to IEC 61000-4-2 for pins LIN and VBAT Bus terminal and battery pin protected against transients in the automotiveenvironment (ISO 7637) Bus terminal short-circuit proof to battery and ground Thermally protected Initial transmit data (TXD) dominant check3. Quick reference dataTable 1.Quick reference dataSymbol ParameterVBATIBATConditionsbattery supply voltagebattery supply currentMinTypMaxUnitlimiting values 0.3- 42Voperating range5-18VSleep mode; VLIN VBAT; VSLP N 0 V2.5710 AStandby mode; VLIN VBAT; VSLP N 0 V2.5710 ANormal mode; VLIN VBAT; VSLP N 5 V;VTXD 5 V2008001600 AVLINvoltage on pin LINlimiting value with respect to GND andVBAT 42- 42VVESDelectrostatic discharge voltageon pin LIN; according to IEC 61000-4-2 8- 8kVTvjvirtual junction temperaturelimiting value 40- 150 C4. Ordering informationTable 2.Ordering informationType lastic small outline package; 8 leads; body width 3.9 mmSOT96-1TJA1027TK/20HVSON8plastic thermal enhanced very thin small outline package; no leads;8 terminals; body 3 3 0.85 mmSOT782-1TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.2 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver5. Block diagramTJA1027POWER-ON RESET &UNDERVOLTAGE DETECTIONRXD7VBAT1BUSTIMER6SLP Fig 1.TJA1027Product data sheetBlock diagramAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.3 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver6. Pinning information6.1 PinningTJA1027TRXDSLP N8172n.c.VBATn.c.36LINTXD45GNDa. TJA1027T/20: SO8 packageRXD18n.c.SLP N27VBATn.c.36LINTXD45GND015aaa214015aaa213Fig 2.TJA1027TKterminal 1index areaTransparent top viewb. TJA1027TK/20: HVSON8 packagePin configuration diagrams6.2 Pin descriptionTable 3.SymbolProduct data sheetPinDescriptionRXD1receive data output (open-drain); active LOW after a wake-up eventSLP N2sleep control input (active LOW); resets wake-up request on RXDn.c.3not connectedTXD4transmit data inputGND5[1]groundLIN6LIN bus line input/outputVBAT7battery supplyn.c.8not connected[1]TJA1027Pin descriptionFor enhanced thermal and electrical performance, solder the exposed center pad of the HVSON8 packageto board ground.All information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.4 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver7. Functional descriptionThe TJA1027 is the interface between the LIN master/slave protocol controller and thephysical bus in a LIN network. According to the Open System Interconnect (OSI) model,this is the LIN physical layer.The LIN transceiver is optimized for, but not limited to, automotive applications withexcellent ElectroMagnetic Compatibility (EMC) performance.7.1 LIN 2.x/ISO 17987-4:2016 (12 V)/SAE J2602 compliantThe TJA1027 is fully LIN 2.0, LIN 2.1, LIN 2.2, LIN 2.2A, SAE J2602 andISO 17987-4:2016 (12 V) compliant. The LIN physical layer is independent of higher OSImodel layers (e.g. the LIN protocol). Consequently, nodes containing anISO 17987-4:2016 (12 V) compliant physical layer can be combined, without restriction,with LIN physical layer nodes that comply with earlier revisions (LIN 1.0, LIN 1.1, LIN 1.2,LIN 1.3, LIN 2.0, LIN 2.1, LIN 2.2 and LIN 2.2A).7.2 Operating modesThe TJA1027 supports modes for normal operation (Normal mode) and very-low-poweroperation (Sleep mode). An intermediate wake-up mode between Sleep and Normalmodes is also supported (Standby mode). The state diagram is shown in Figure 3.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.5 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiverfalling VBAT Vth(POR)LResetRXD: floatingTransmitter: offNormalRXD: data outputTransmitter: on(1)rising VBAT Vth(POR)Ht(SLP N 1) tgotonormt(SLP N 1) tgotonormt(SLP N 0) tgotosleepSleepStandbyRXD: floatingTransmitter: offRXD: lowTransmitter: offt(LIN 0 1; after LIN 0) twake(dom)LIN015aaa215(1) A positive edge on SLP N triggers a transition to Normal mode; the transmitter is enabled onceTXD goes HIGH; in the event of thermal shut down, the transmitter is disabled.Fig 3.Table 4.SLP NRXDTransmitterDescriptionResetxfloatingoffall inputs ignored; all outputsdrivers offSleep[1]0floatingoffno wake-up request detected0LOW[3]offNormal[1]Product data sheetOperating modesModeStandby[2]TJA1027State diagram1HIGH: recessive state NormalLOW: dominant statewake-up request detectedmode[4]bus signal shaping enabledThe TJA1027 enters Sleep mode after a power-on reset (e.g. after switching on VBAT).[2]The TJA1027 will switch automatically to Standby mode if a LIN wake-up event occurs during Sleep mode.[3]The wake-up interrupt (on pin RXD) is released after a positive edge on pin SLP N.[4]A positive edge on SLP N will trigger a transition to Normal mode The transmitter will be off if TXD is LOWand will be enabled as soon as TXD goes HIGH.All information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.6 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver7.2.1 Reset modeWhen the TJA1027 is in Reset mode, it ignores all input signals and all output drivers areoff. The TJA1027 switches to Reset mode when the voltage on VBAT drops below theLOW-level power-on reset threshold, Vth(POR)L. When the voltage on VBAT rises above theHIGH-level power-on reset threshold, Vth(POR)H, the TJA1027 switches to Sleep mode.7.2.2 Sleep modeThe TJA1027 consumes significantly less power in Sleep mode than in any other mode.Even though current consumption is extremely low in Sleep mode, the TJA1027 can stillbe woken up remotely via pin LIN or activated directly via pin SLP N. Filters on thereceiver input (LIN) and on pin SLP N prevent unwanted wake-up events occurring due toautomotive transients or radio frequency interference. All wake-up events must bemaintained for a specific period of time (twake(dom)LIN or tgotonorm).Sleep mode is initiated by a falling edge on pin SLP N in Normal mode. The LIN transmitpath is immediately disabled when pin SLP N goes LOW. In order to ensure the TJA1027switches successfully to Sleep mode, the sleep command (pin SLP N LOW) must bemaintained for at least tgotosleep.Sleep mode activation is independent of the levels on pins LIN or TXD. So the lowestpossible power consumption can be guaranteed, even when there is a continuousdominant level on pins LIN and TXD.7.2.3 Standby modeStandby mode is activated automatically when a local or remote wake-up event occurswhile the TJA1027 is in Sleep mode. In Standby mode, pin RXD is held LOW to providean interrupt flag for the microcontroller.7.2.4 Normal modeIn Normal mode, the TJA1027 can transmit and receive data via the LIN bus.The receiver detects the data stream on the LIN bus input pin and transfers it via pin RXDto the microcontroller (see Figure 6): HIGH for a recessive level and LOW for a dominantlevel on the bus. The receiver has a supply-voltage related threshold with hysteresis andan integrated filter to suppress bus line noise.The transmit data stream from the protocol controller is detected on pin TXD and isconverted by the transmitter into an optimized bus signal shaped to minimize EME. TheLIN bus output pin is pulled HIGH via an internal slave termination resistor. For a masterapplication, an external resistor in series with a diode should be connected between pinVBAT and pin LIN (see Figure 6).If pin SLP N is pulled HIGH while the TJA1027 is in Sleep or Standby mode, the LINtransceiver switches to Normal mode after tgotonorm.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.7 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver7.3 Transceiver wake-up7.3.1 Remote wake-up via the LIN busA falling edge on pin LIN followed by a LOW level maintained for twake(dom)LIN followed bya rising edge on pin LIN triggers a remote wake-up (see Figure 4). It should be noted thatthe time period twake(dom)LIN is measured either in Normal mode while TXD is HIGH, or inSleep mode irrespective of the status of pin TXD./,1 UHFHVVLYH9%86UHF9%86GRP9/,1WZDNH GRP /,1/,1 GRPLQDQWJURXQG6OHHS PRGH6WDQGE\ PRGH DDD Fig 4.Remote wake-up behavior7.3.2 Wake-up via pin SLP NIf SLP N is held HIGH for tgotonorm, the TJA1027 will switch from Sleep mode to Normalmode.7.4 Operation during automotive cranking pulsesTJA1027 remains fully operational during automotive cranking pulses because the LINtransceiver is fully specified down to VBAT 5 V.7.5 Operation when supply voltage is outside specified operating rangeIf VBAT 18 V or VBAT 5 V, the TJA1027 may remain operational, but parameter valuescannot be guaranteed to remain within the operation ranges specified in Table 7 andTable 8.In Normal mode: If the input level on pin TXD is HIGH, the LIN transmitter output on pin LIN will berecessive. If the input level on pin LIN is recessive, the receiver output on pin RXD will be HIGH. If the voltage on pin VBAT rises to 27 V (e.g. during an automotive jump start), the totalLIN network pull-up resistance should be greater than 680 and the total LIN networkcapacitance should be less than 6.8 nF to ensure reliable LIN data transfer. If the voltage on pin VBAT drops below the LOW-level VBAT LOW threshold, Vth(VBATL)L,the LIN transmit path is interrupted and the LIN output remains recessive. The LINtransmit path is switched on again when VBAT rises above Vth(VBATL)H and the input topin TXD is recessive.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.8 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiverIf the voltage on pin VBAT drops below the LOW-level power-on reset threshold, Vth(POR)L,the TJA1027 switches to Reset mode (i.e. all output drivers are disabled and all inputs areignored). The TJA1027 switches to Sleep mode if VBAT Vth(POR)H.7.6 Fail-safe featuresPin TXD provides a pull-down to GND in order to force a predefined level on the transmitdata input if the pin is disconnected.Pin SLP N provides a pull-down to GND in order to force the transceiver into Sleep modeif pin SLP N is disconnected.Pin RXD is set floating if VBAT is disconnected.The current in the transmitter output stage is limited in order to protect the transmitteragainst short circuits to pins VBAT or GND.A loss of power (pins VBAT and GND) has no impact on the bus line or on themicrocontroller. No reverse currents flow from the bus into pin LIN. The current path fromVBAT to LIN via the integrated LIN slave termination resistor remains. The LIN transceivercan be disconnected from the power supply without influencing the LIN bus.The output driver on pin LIN is protected against overtemperature conditions. If thejunction temperature exceeds the shutdown junction temperature, Tj(sd), the thermalprotection circuit disables the output driver. The driver is enabled again when the junctiontemperature falls below Tj(sd) and pin TXD is recessive.The initial TXD dominant check prevents the bus line from being driven to a permanentdominant state (blocking all network communications) if pin TXD is forced permanentlyLOW by a hardware and/or software application failure. The TXD input level is checkedafter a transition to Normal mode. If TXD is LOW, the transmit path will remain disabledand will only be enabled when TXD goes HIGH.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.9 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver8. Limiting valuesTable 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to pin GND, unlessotherwise specified. Positive currents flow into the IC.SymbolParameterMinMaxUnitVBATbattery supply voltageConditions 0.3 42VVTXDvoltage on pin TXD 0.3 7VVRXDvoltage on pin RXD 0.3 7VVSLP Nvoltage on pin SLP NVLINvoltage on pin LINVESDelectrostatic discharge voltagewith respect to GND and VBATaccording to IEC 61000-4-2human body modelcharge device modelmachine modelTvjvirtual junction temperatureTstgstorage temperature[1] 0.3 7V 42 42Von pins LIN and VBAT[1] 8 8kVon pins LIN and VBAT[2] 8 8kVon pins TXD, RXD and SLP N[2] 2 2kV 750 750V[3] 200 200V[4] 40 150 C 55 150 Call pinsall pinsEquivalent to discharging a 150 pF capacitor through a 330 resistor.[2]Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor.[3]Equivalent to discharging a 200 pF capacitor through a 10 resistor and a 0.75 H coil.[4]Junction temperature in accordance with IEC 60747-1. An alternative definition is: Tj Tamb P Rth(j-a), where Rth(j-a) is a fixed value.The rating for Tvj limits the allowable combinations of power dissipation (P) and ambient temperature (Tamb).9. Thermal characteristicsTable 6.Thermal characteristicsAccording to IEC ermal resistance from junction to ambientSO8 package; in free air145K/WHVSON8 package; in free air50K/WTJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.10 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver10. Static characteristicsTable 7.Static characteristicsVBAT 5 V to 18 V; Tvj 40 C to 150 C; RL(LIN-VBAT) 500 ; all voltages are referenced to pin GND; positive currentsflow into the IC; typical values are given at VBAT 12 V; unless otherwise t5-18VSleep mode; bus recessive;VLIN VBAT; VSLP N 0 V2.5710 ASleep mode; bus dominant;VLIN 0 V; VBAT 12 V;VSLP N 0 V1504001200 AStandby mode; bus recessive;VLIN VBAT; VSLP N 0 V2.5710 A1003001000 ANormal mode; bus recessive;VLIN VBAT; VSLP N 5 V;VTXD 5 V2008001600 ANormal mode; bus dominant;VTXD 0 V; VSLP N 5 V;VBAT 12 V124mASupplyVBATbattery supply voltageIBATbattery supply currentStandby mode; bus dominant;VLIN 0 V; VBAT 12 V;VSLP N 0 V[2]Undervoltage resetVth(POR)LLOW-level power-on reset power-on resetthreshold voltage1.63.13.9VVth(POR)HHIGH-level power-on resetthreshold voltage2.33.44.3VVhys(POR)power-on reset hysteresisvoltage0.050.31VVth(VBATL)LLOW-level VBAT LOWthreshold voltage3.94.44.7VVth(VBATL)HHIGH-level VBAT LOWthreshold voltage4.24.74.9VVhys(VBATL)VBAT LOW hysteresisvoltage0.150.30.6V2-7V 0.3- 0.8V50200400mVon TXD50125325k on SLP N100250650k 2--mA 5- 5 A[2][2]Pins TXD and SLP NVIHHIGH-level input voltageVILLOW-level input voltageVhyshysteresis voltageRpdpull-down resistance[2]Pin RXD (open-drain)IOLILHLOW-level output currentVRXD 0.4 V[2]HIGH-level leakagecurrentTJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.11 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiverTable 7.Static characteristics continuedVBAT 5 V to 18 V; Tvj 40 C to 150 C; RL(LIN-VBAT) 500 ; all voltages are referenced to pin GND; positive currentsflow into the IC; typical values are given at VBAT 12 V; unless otherwise t40-100mAPin LINIBUS LIMcurrent limitation for driver VBAT 18 V; VLIN 18 V;dominant stateVTXD 0 VIBUS PAS domreceiver dominant inputleakage current includingpull-up resistorVBAT 12 V; VLIN 0 V;VTXD 5 V[2] 600-- AIBUS PAS recreceiver recessive inputleakage currentVBAT 5 V; VLIN 18 V;VTXD 5 V[2]-01 AIBUS NO GNDloss-of-ground bus current VBAT 18 V; VLIN 0 V[2] 750- 10 AIBUS NO BATloss-of-battery bus current VBAT 0 V; VLIN 18 V[2]--1 Areceiver dominant state[2]--0.4VBATVVBUSrecreceiver recessive state[2]0.6VBAT--VVBUS CNTreceiver center voltageVHYSreceiver hysteresis voltage VHYS VBUSrec VBUSdomVSerDiodevoltage drop at the serialdiodeVO(dom)dominant output voltageVBUSdomRslaveCLINVBUS CNT (VBUSdom VBUSrec) / 20.475VBAT 0.5VBAT0.525VBAT V[2]--0.175VBAT Vin pull-up path with Rslave;ISerDiode 0.9 mA[2]0.4-1.0VNormal mode; VTXD 0 V;VBAT 7.0 V[2]--1.4VNormal mode; VTXD 0 V;VBAT 18 V[2]--2.0V203060k with respect to GND[2]--20pF[2]150-200 Cslave resistancecapacitance on pin LINThermal shutdownTj(sd)shutdown junctiontemperature[1]All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions tocover the specified temperature and power supply voltage range.[2]Not tested in production; guaranteed by design.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.12 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver11. Dynamic characteristicsTable 8.Dynamic characteristicsVBAT 5 V to 18 V; Tvj 40 C to 150 C; RL(LIN-VBAT) 500 ; all voltages are referenced to pin GND; positive currentsflow into the IC; typical values are given at VBAT 12 V, unless otherwise y cycle 1Vth(rec)(max) 0.744 VBAT;Vth(dom)(max) 0.581 VBAT;tbit 50 s; VBAT 7 V to 18 V[2][4][5]0.396 --Vth(rec)(max) 0.768 VBAT;Vth(dom)(max) 0.6 VBAT;tbit 50 s; VBAT 5 V to 7 V[2][4][5]0.396 --Vth(rec)(min) 0.422 VBAT;Vth(dom)(min) 0.284 VBAT;tbit 50 s; VBAT 7.6 V to 18 V[3][4][5]--0.581Vth(rec)(min) 0.405 VBAT;Vth(dom)(min) 0.271 VBAT;tbit 50 s; VBAT 5.6 V to 7.6 V[3][4][5]--0.581Vth(rec)(max) 0.778 VBAT;Vth(dom)(max) 0.616 VBAT;tbit 96 s; VBAT 7 V to 18 V[2][4][5]0.417 --Vth(rec)(max) 0.805 VBAT;Vth(dom)(max) 0.637 VBAT;tbit 96 s; VBAT 5 V to 7 V[2][4][5]0.417 --Vth(rec)(min) 0.389 VBAT;Vth(dom)(min) 0.251 VBAT;tbit 96 s; VBAT 7.6 V to 18 V[3][4][5]--0.590Vth(rec)(min) 0.372 VBATVth(dom)(min) 0.238 VBATtbit 96 s; VBAT 5.6 V to 7.6 V[3][4][5]--0.590UnitDuty cycles 1 2duty cycle 2 3duty cycle 3 4duty cycle 4Timing characteristicstrx pdreceiver propagationdelayrising and falling;CRXD 20 pF; RRXD 2.4 k [5]--6 strx symreceiver propagationdelay symmetryCRXD 20 pF; RRXD 2.4 k ;rising edge with respect to falling edge[5] 2- 2 stwake(dom)LINLIN dominant wake-uptimeSleep mode3080150 stgotonormgo to normal timetime period for mode change fromSleep or Standby mode to Normalmode2610 stinit(norm)normal modeinitialization time7-20 stgotosleepgo to sleep time2610 s[1][2]time period for mode change fromNormal to Sleep modeAll parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions tocover the specified temperature and power supply voltage ranges.t bus rec min . Variable tbus(rec)(min) is illustrated in the LIN timing diagram in Figure 5. 1 3 ------------------------------2 t bitTJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.13 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver[3]t bus rec max 2 4 ------------------------------- . Variable tbus(rec)(max) is illustrated in the LIN timing diagram in Figure 5.2 t bit[4]Bus load conditions: CBUS 1 nF and RBUS 1 k ; CBUS 6.8 nF and RBUS 660 ; CBUS 10 nF and RBUS 500 .[5]See timing diagram in Figure (max)Vth(dom)(max)VBATLIN BUSsignaltbus(dom)(min)thresholds ofreceiving node 1tbus(rec)(max)Vth(rec)(min)Vth(dom)(min)trx pdrtrx pdfthresholds ofreceiving node 2trx pdfVRXDreceivingnode 1trx pdfreceivingnode 2trx pdrtrx pdfVRXD015aaa237Fig 5.Timing diagram of LIN transceiver duty cycleTJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.14 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver12. Application information12.1 Application diagramVECULIN BUSLINEBATTERY 3 V/ 5 Vonly formaster nodeVBATVDDRX0MICROTX0CONTROLLERGNDPx.xRXDTXDSLP N1 kΩ714TJA1027256LIN(1)015aaa238(1) Typically specified by car manufacturer, e.g. master: C 1 nF; slave: C 220 pF.Fig 6.Application diagram12.2 ESD robustness according to LIN EMC test specificationESD robustness (IEC 61000-4-2) has been tested by an external test house according tothe LIN EMC test specification (part of Conformance Test Specification Package forLIN 2.1, October 10th, 2008). The test report is available on request.Table 9.ESD robustness (IEC 61000-4-2) according to LIN EMC test specificationPinTest configurationValueUnitLINno capacitor connected to LIN pin 13kV220 pF capacitor connected to LIN pin 12kV100 nF capacitor connected to VBAT pin 15 kVVBAT12.3 Hardware requirements for LIN interfaces in automotive applicationsThe TJA1027 satisfies the "Hardware Requirements for LIN, CAN and FlexRay Interfacesin Automotive Applications", Version 1.1, December 2009.13. Test information13.1 Quality informationThis product has been qualified in accordance with the Automotive Electronics Council(AEC) standard Q100 Rev-G - Failure mechanism based stress test qualification forintegrated circuits, and is suitable for use in automotive applications.TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.15 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver14. Package outline62 SODVWLF VPDOO RXWOLQH SDFNDJH OHDGV ERG\ ZLGWK PP 627 ' ( ; F \ ( Y 0 4 SLQ LQGH[ ș / S / H GHWDLO ; Z 0 E S PP VFDOH ',0(16,216 LQFK GLPHQVLRQV DUH GHULYHG IURP WKH RULJLQDO PP GLPHQVLRQV 81,7 PD[ E S F ' ( H ( / / S 4 Y Z \ PP LQFKHV ș R R 1RWHV 3ODVWLF RU PHWDO SURWUXVLRQV RI PP LQFK PD[LPXP SHU VLGH DUH QRW LQFOXGHG 3ODVWLF RU PHWDO SURWUXVLRQV RI PP LQFK PD[LPXP SHU VLGH DUH QRW LQFOXGHG Fig 7. 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7 (8523( 1 352-(&7,21 ,668( ' 7( Package outline SOT96-1 (SO8)TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.16 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver 9621 SODVWLF WKHUPDO HQKDQFHG YHU\ WKLQ VPDOO RXWOLQH SDFNDJH QR OHDGV WHUPLQDOV ERG\ [ [ PP627 ;%' ( FGHWDLO ;WHUPLQDO LQGH[ DUHDH WHUPLQDO LQGH[ DUHDH && %&YZE\ &\/.(K 'K 'LPHQVLRQV8QLW PP PPVFDOH EFPD[ QRP PLQ ''K((KHH ./Y Z\ \ 1RWH 3ODVWLF RU PHWDO SURWUXVLRQV RI PD[LPXP SHU VLGH DUH QRW LQFOXGHG Fig 8.5HIHUHQFHV2XWOLQH YHUVLRQ,(&-('(&-(,7 627 02 VRW BSR(XURSHDQ SURMHFWLRQ,VVXH GDWH Package outline SOT782-1 (HVSON8)TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.17 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver15. Handling informationAll input and output pins are protected against ElectroStatic Discharge (ESD) undernormal handling. When handling ensure that the appropriate precautions are taken asdescribed in JESD625-A or equivalent standards.16. Soldering of SMD packagesThis text provides a very brief insight into a complex technology. A more in-depth accountof soldering ICs can be found in Application Note AN10365 “Surface mount reflowsoldering description”.16.1 Introduction to solderingSoldering is one of the most common methods through which packages are attached toPrinted Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides boththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole andSurface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.16.2 Wave and reflow solderingWave soldering is a joining technology in which the joints are made by solder coming froma standing wave of liquid solder. The wave soldering process is suitable for the following: Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit boardNot all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,leaded SMDs with leads having a pitch smaller than 0.6 mm cannot be wave soldered,due to an increased probability of bridging.The reflow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature profile. Leaded packages,packages with solder balls, and leadless packages are all reflow solderable.Key characteristics in both wave and reflow soldering are: Board specifications, including the board finish, solder masks and viasPackage footprints, including solder thieves and orientationThe moisture sensitivity level of the packagesPackage placementInspection and repairLead-free soldering versus SnPb soldering16.3 Wave solderingKey characteristics in wave soldering are:TJA1027Product data sheetAll information provided in this document is subject to legal disclaimers.Rev. 3 — 18 December 2018 NXP B.V. 2018. All rights reserved.18 of 24

TJA1027NXP SemiconductorsISO 17987/LIN 2.x/SAE J2602 transceiver Process issues, such as application of adhesive and flux, clinching of leads, boardtransport, the solder wave parameters, and the time during which components areexposed to the wave Solder bath specifications, including temperature and impurities16.4 Reflow solderingKey characteristics in reflow soldering are: Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads tohigher minimum peak temperatures (see Figure 9) than a SnPb process, thusreducing the process window Solder paste printing issues including smearing, release, and adjusting the processwindow for a mix of large and small components on one board Reflow temperature profile; this profile includes preheat, reflow (in which the board isheated to the peak temperature) and cooling down. It is imperative that the peaktemperature is high enough for the solder to make reliable solder joints (a solder pastecharacteristic). In addition, the peak temperature must be low enough that thepackage

ISO 17987-4:2016 (12 V) compliant. The LIN physical layer is independent of higher OSI model layers (e.g. the LIN protocol). Consequently, nodes containing an ISO 17987-4:2016 (12 V) compliant physical layer can be combined, without restriction, with LIN physical layer nodes that

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