AMBA AXI And ACE Protocol Specification AXI3, AXI4, And .

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AMBA AXI and ACE ProtocolSpecification AXI3 , AXI4 , and AXI4-LiteACE and ACE-Lite Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.ARM IHI 0022D (ID102711)

AMBA AXI and ACE Protocol SpecificationAXI3, AXI4, and AXI4-LiteACE and ACE-LiteCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Release InformationThe following changes have been made to this specification.Change historyDateIssueConfidentialityChange16 June 2003ANon-ConfidentialFirst release19 March 2004BNon-ConfidentialFirst release of AXI specification v1.003 March 2010CNon-ConfidentialFirst release of AXI specification v2.003 June 2011D-2cNon-ConfidentialPublic beta draft of AMBA AXI and ACE Protocol Specification28 October 2011DNon-ConfidentialFirst release of AMBA AXI and ACE Protocol SpecificationIssues B and C of this document included an AXI specification version, v1.0 and v2.0. These version number have beendiscontinued, to remove confusion with the AXI versions, AXI3 and AXI4.Proprietary NoticeWords and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except asotherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of theirrespective owners.Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted orreproduced in any material form except with the prior written permission of the copyright holder.The product described in this document is subject to continuous developments and improvements. All particulars of the productand its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, includingbut not limited to implied warranties of merchantability, or fitness for purpose, are excluded.This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arisingfrom the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.ARM AMBA SPECIFICATION LICENCETHIS END USER LICENCE AGREEMENT (“LICENCE”) IS A LEGAL AGREEMENT BETWEEN YOU (EITHER ASINGLE INDIVIDUAL, OR SINGLE LEGAL ENTITY) AND ARM LIMITED (“ARM”) FOR THE USE OF THE RELEVANTAMBA SPECIFICATION ACCOMPANYING THIS LICENCE. ARM IS ONLY WILLING TO LICENSE THE RELEVANTAMBA SPECIFICATION TO YOU ON CONDITION THAT YOU ACCEPT ALL OF THE TERMS IN THIS LICENCE. BYCLICKING “I AGREE” OR OTHERWISE USING OR COPYING THE RELEVANT AMBA SPECIFICATION YOUINDICATE THAT YOU AGREE TO BE BOUND BY ALL THE TERMS OF THIS LICENCE. IF YOU DO NOT AGREE TOTHE TERMS OF THIS LICENCE, ARM IS UNWILLING TO LICENSE THE RELEVANT AMBA SPECIFICATION TO YOUAND YOU MAY NOT USE OR COPY THE RELEVANT AMBA SPECIFICATION AND YOU SHOULD PROMPTLYRETURN THE RELEVANT AMBA SPECIFICATION TO ARM.“LICENSEE” means You and your Subsidiaries.“Subsidiary” means, if You are a single entity, any company the majority of whose voting shares is now or hereafter owned orcontrolled, directly or indirectly, by You. A company shall be a Subsidiary only for the period during which such control exists.1. Subject to the provisions of Clauses 2, 3 and 4, ARM hereby grants to LICENSEE a perpetual, non-exclusive, non-transferable,royalty free, worldwide licence to:(i) use and copy the relevant AMBA Specification for the purpose of developing and having developed products that comply withthe relevant AMBA Specification;iiCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

(ii) manufacture and have manufactured products which either: (a) have been created by or for LICENSEE under the licencegranted in Clause 1(i); or (b) incorporate a product(s) which has been created by a third party(s) under a licence granted by ARMin Clause 1(i) of such third party’s ARM AMBA Specification Licence; and(iii) offer to sell, sell, supply or otherwise distribute products which have either been (a) created by or for LICENSEE under thelicence granted in Clause 1(i); or (b) manufactured by or for LICENSEE under the licence granted in Clause 1(ii).2. LICENSEE hereby agrees that the licence granted in Clause 1 is subject to the following restrictions:(i) where a product created under Clause 1(i) is an integrated circuit which includes a CPU then either: (a) such CPU shall onlybe manufactured under licence from ARM; or (b) such CPU is neither substantially compliant with nor marketed as beingcompliant with the ARM instruction sets licensed by ARM from time to time;(ii) the licences granted in Clause 1(iii) shall not extend to any portion or function of a product that is not itself compliant withpart of the relevant AMBA Specification; and(iii) no right is granted to LICENSEE to sublicense the rights granted to LICENSEE under this Agreement.3. Except as specifically licensed in accordance with Clause 1, LICENSEE acquires no right, title or interest in any ARMtechnology or any intellectual property embodied therein. In no event shall the licences granted in accordance with Clause 1 beconstrued as granting LICENSEE, expressly or by implication, estoppel or otherwise, a licence to use any ARM technology exceptthe relevant AMBA Specification.4. THE RELEVANT AMBA SPECIFICATION IS PROVIDED “AS IS” WITH NO WARRANTIES EXPRESS, IMPLIED ORSTATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY OF SATISFACTORY QUALITY,MERCHANTABILITY, NONINFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE.5. No licence, express, implied or otherwise, is granted to LICENSEE, under the provisions of Clause 1, to use the ARMtradename, or AMBA trademark in connection with the relevant AMBA Specification or any products based thereon. Nothing inClause 1 shall be construed as authority for LICENSEE to make any representations on behalf of ARM in respect of the relevantAMBA Specification.6. This Licence shall remain in force until terminated by you or by ARM. Without prejudice to any of its other rights if LICENSEEis in breach of any of the terms and conditions of this Licence then ARM may terminate this Licence immediately upon givingwritten notice to You. You may terminate this Licence at any time. Upon expiry or termination of this Licence by You or by ARMLICENSEE shall stop using the relevant AMBA Specification and destroy all copies of the relevant AMBA Specification in yourpossession together with all documentation and related materials. Upon expiry or termination of this Licence, the provisions ofclauses 6 and 7 shall survive.7. The validity, construction and performance of this Agreement shall be governed by English Law.ARM contract references: LEC-PRE-00490-V4.0 ARM AMBA Specification Licence.Confidentiality StatusThis document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions inaccordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.Product StatusThe information in this document is final, that is for a developed product.Web Addresshttp://www.arm.comARM IHI 0022DID102711Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-Confidentialiii

ivCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

ContentsAMBA AXI and ACE Protocol Specification AXI3,AXI4, and AXI4-Lite ACE and ACE-LitePrefaceAbout this specification . xUsing this specification . xiConventions . xiiiAdditional reading . xvFeedback . xviPart AChapter A1AMBA AXI3 and AXI4 Protocol SpecificationIntroductionA1.1A1.2A1.3A1.4Chapter A2A1-20A1-21A1-22A1-25Signal DescriptionsA2.1A2.2A2.3A2.4A2.5A2.6A2.7ARM IHI 0022DID102711About the AXI protocol .AXI revisions .AXI Architecture .Terminology .Global signals .Write address channel signals .Write data channel signals .Write response channel signals .Read address channel signals .Read data channel signals .Low-power interface signals .Copyright 2003, 2004, 2010, 2011 ARM. All rights A2-33A2-34v

ContentsChapter A3Single Interface RequirementsA3.1A3.2A3.3A3.4Chapter A4Clock and reset .Basic read and write transactions .Relationships between the channels .Transaction structure .Transaction ter A5Transaction types and attributes .AXI3 memory attribute signaling .AXI4 changes to memory attribute signaling .Memory types .Mismatched memory attributes .Transaction buffering .Access permissions .Legacy considerations .Usage examples .AXI transaction identifiers .Transaction ID .Transaction ordering .Removal of write interleaving support .Definition of the ordering model .Master ordering .Interconnect ordering .Slave ordering .Response before final destination .Single-copy atomicity size .Exclusive accesses .Locked accesses .Atomic access signaling .QoS signaling . A8-98Multiple region signaling . A8-99User-defined signaling . A8-100Low-power InterfaceA9.1A9.2Chapter A10About the low-power interface . A9-102Low-power clock control . A9-103Default Signaling and InteroperabilityA10.1A10.2A10.3Part BChapter B1Interoperability principles . A10-110Major interface categories . A10-111Default signal values . A10-112AMBA AXI4-Lite Interface SpecificationAMBA AXI4-LiteB1.1B1.2B1.3viA7-90A7-92A7-95A7-96AXI4 Additional SignalingA8.1A8.2A8.3Chapter A9A6-84A6-85A6-86A6-87A6-88Atomic AccessesA7.1A7.2A7.3A7.4Chapter A8A5-76A5-77A5-78A5-81AXI4 Ordering ModelA6.1A6.2A6.3A6.4A6.5Chapter tiple TransactionsA5.1A5.2A5.3A5.4Chapter A6A3-36A3-37A3-40A3-44Definition of AXI4-Lite . B1-122Interoperability . B1-124Defined conversion mechanism . B1-125Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

ContentsB1.4Part CChapter C1Conversion, protection, and detection . B1-127ACE Protocol SpecificationAbout ACEC1.1C1.2C1.3C1.4C1.5C1.6C1.7Chapter C2Coherency overview . C1-132Protocol overview . C1-134Channel overview . C1-137Transaction overview . C1-142Transaction processing . C1-146Concepts required for the ACE specification . C1-147Protocol errors . C1-150Signal DescriptionsC2.1C2.2C2.3Chapter C3Changes to existing AXI4 channels . C2-152Additional channels defined by ACE . C2-153Additional response signals and signaling requirements defined by ACE . C2-155Channel er C4Read and write address channel signaling . C3-158Read data channel signaling . C3-167Read acknowledge signaling . C3-170Write response channel signaling . C3-171Write Acknowledge signaling . C3-172Snoop address channel signaling . C3-173Snoop response channel signaling . C3-176Snoop data channel signaling . C3-180Snoop channel dependencies . C3-182Coherency Transactions on the Read Address and Write 9C4.10Chapter C5Snoop TransactionsC5.1C5.2C5.3Chapter C6Mapping coherency operations to snoop operations . C5-210General requirements for snoop transactions . C5-213Snoop transactions . C5-219Interconnect RequirementsC6.1C6.2C6.3C6.4C6.5C6.6C6.7ARM IHI 0022DID102711About an initiating master . C4-184About snoop filtering . C4-187State changes on different transactions . C4-188State change descriptions . C4-190Read transactions . C4-191Clean transactions . C4-197Make transactions . C4-200Write transactions . C4-202Evict transactions . C4-206Handling overlapping write transactions . C4-207About the interconnect requirements . C6-226Sequencing transactions . C6-227Issuing snoop transactions . C6-229Transaction responses from the interconnect . C6-232Interactions with main memory . C6-234Other requirements . C6-237Interoperability considerations . C6-239Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-Confidentialvii

ContentsChapter C7Cache MaintenanceC7.1C7.2Chapter C8ARCACHE and ARDOMAIN requirements . C7-242Other cache maintenance considerations . C7-243Barrier TransactionsC8.1C8.2C8.3C8.4Chapter C9About barrier transactions .Barrier transaction signaling .Barrier responses and domain boundaries .Barrier requirements .Exclusive AccessesC9.1C9.2C9.3C9.4C9.5C9.6Chapter C10About Exclusive accesses .Role of the master .Role of the interconnect .Multiple Exclusive Threads .Exclusive Accesses from AXI components .Transaction requirements .Appendix AAbout DVM transactions .Synchronization message .DVM transaction process and rules .Physical and virtual address space size .DVM transactions format .DVM transaction restrictions .DVM Operations Interface ControlC13.1Part DAbout ACE-Lite . C11-276ACE-Lite signal requirements . C11-277Distributed Virtual Memory pter C13About external snoop filtering . C10-270Master requirements to support snoop filters . C10-272External snoop filter requirements . C10-273ACE-LiteC11.1C11.2Chapter C12C9-260C9-261C9-263C9-266C9-267C9-268Optional External Snoop FilteringC10.1C10.2C10.3Chapter C11C8-248C8-249C8-251C8-254About the interface control signals . C13-296AppendicesRevisionsGlossaryviiiCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

PrefaceThis preface introduces the AMBA AXI and ACE Protocol Specification. It contains the following sections: About this specification on page x Using this specification on page xi Conventions on page xiii Additional reading on page xv Feedback on page xvi.ARM IHI 0022DID102711Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-Confidentialix

PrefaceAbout this specificationAbout this specificationThis specification describes: the AMBA 3 AXI protocol release referred to as AXI3 the AMBA 4 AXI protocol releases referred to as AXI4 and AXI4-Lite the AMBA 4 protocol releases referred to as ACE and ACE-Lite.Intended audienceThis specification is written for hardware and software engineers who want to become familiar with the AdvancedMicrocontroller Bus Architecture (AMBA) and design systems and modules that are compatible with the AdvancedeXtensible Interface (AXI) protocol.xCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

PrefaceUsing this specificationUsing this specificationThe information in this specification is organized into parts, as described in this section.Part A, AMBA AXI3 and AXI4 Protocol SpecificationPart A describes the AXI3 and AXI4 releases of the AMBA AXI Protocol Specification. It contains the followingchapters:Chapter A1 IntroductionRead this for an introduction to the AXI architecture, and to the terminology used in thisspecification.Chapter A2 Signal DescriptionsRead this for a description of the signals that are used by the AXI3 and AXI4 protocols.Chapter A3 Single Interface RequirementsRead this for a description of the basic AXI protocol transaction requirements between a master andslave.Chapter A4 Transaction AttributesRead this for a description of the AXI protocol and signaling that supports system topology andsystem level caches.Chapter A5 Multiple TransactionsRead this for a description of the AXI protocol and signaling that supports out-of-order transactioncompletion and the issuing of multiple outstanding addresses.Chapter A6 AXI4 Ordering ModelRead this for a description of the AXI4 ordering model.Chapter A7 Atomic AccessesRead this for a description of the mechanisms that support atomic accesses.Chapter A8 AXI4 Additional SignalingRead this for a description of the additional signaling introduced in AXI4 to extend the applicationof the AXI interface.Chapter A9 Low-power InterfaceRead this for a description of the control interface that supports low-power operation.Chapter A10 Default Signaling and InteroperabilityRead this for a description of the interoperability of interfaces that use reduced AXI signal sets.Part B, AMBA AXI4-Lite Interface SpecificationPart B describes AMBA AXI4-Lite. It contains the following chapter:Chapter B1 AMBA AXI4-LiteRead this for a description of AXI4-Lite that provides a simpler control register-style interface forsystems that do not require the full functionality of AXI4.ARM IHI 0022DID102711Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-Confidentialxi

PrefaceUsing this specificationPart C, ACE Protocol SpecificationPart C describes the ACE protocol. It contains the following chapters:Chapter C1 About ACEThis chapter gives an overview of system level coherency and the architecture of the AXI CoherencyExtensions (ACE) protocol.Chapter C2 Signal DescriptionsThis chapter introduces the additional ACE interface signals.Chapter C3 Channel SignalingThis chapter describes the basic channel signaling requirements on an ACE interface.Chapter C4 Coherency Transactions on the Read Address and Write Address ChannelsThis chapter describes the transactions issued on the read address and write address channels.Chapter C5 Snoop TransactionsThis chapter describes the snoop transactions seen on the snoop address channel.Chapter C6 Interconnect RequirementsThis chapter describes the ACE interconnect requirements.Chapter C7 Cache MaintenanceThis chapter describes the ACE cache maintenance operations.Chapter C8 Barrier TransactionsThis chapter describes the ACE memory and synchronization barrier transactions.Chapter C9 Exclusive AccessesThis chapter describes the ACE Exclusive Accesses to shareable memory.Chapter C10 Optional External Snoop FilteringThis chapter describes using an external snoop filter in an ACE system.Chapter C11 ACE-LiteThis chapter describes the ACE-Lite interface.Chapter C12 Distributed Virtual Memory TransactionsThis chapter describes Distributed Virtual Memory (DVM) transactions.Chapter C13 Interface ControlThis chapter describes the optional signals that can be used to configure the ACE interface.Part D, AppendicesThis specification contains the following appendices:Appendix A RevisionsRead this for a description of the technical changes between released issues of this specification.xiiCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

PrefaceConventionsConventionsThe following sections describe conventions that this specification can use: Typographic conventions Timing diagrams Signals on page xiv Numbers on page xivTypographic conventionsThe typographical conventions are:italicHighlights important notes, introduces special terminology, and denotes internalcross-references and citations.boldDenotes signal names, and is used for terms in descriptive lists, where appropriate.monospaceUsed for assembler syntax descriptions, pseudocode, and source code examples.Also used in the main text for instruction mnemonics and for references to other itemsappearing in assembler syntax descriptions, pseudocode, and source code examples.SMALL CAPITALSUsed for a few terms that have specific technical meanings.Timing diagramsThe figure named Key to timing diagram conventions explains the components used in timing diagrams. Variations,when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at thattime. The actual level is unimportant and does not affect normal operation.ClockHIGH to LOWTransientHIGH/LOW to HIGHBus stableBus to high impedanceBus changeHigh impedance to stable busKey to timing diagram conventionsTiming diagrams sometimes show single-bit signals as HIGH and LOW at the same time and they look similar tothe bus change shown in Key to timing diagram conventions. If a timing diagram shows a single-bit signal in thisway then its value does not affect the accompanying description.ARM IHI 0022DID102711Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-Confidentialxiii

PrefaceConventionsSignalsThe signal conventions are:Signal levelThe level of an asserted signal depends on whether the signal is active-HIGH oractive-LOW. Asserted means: HIGH for active-HIGH signals LOW for active-LOW signals.Lower-case nAt the start or end of a signal name denotes an active-LOW signal.NumbersNumbers are normally written in decimal. Binary numbers are preceded by 0b, and hexadecimal numbers by 0x.Both are written in a monospace font.xivCopyright 2003, 2004, 2010, 2011 ARM. All rights reserved.Non-ConfidentialARM IHI 0022DID102711

Contents ARM IHI 0022D Copyright 2003, 2004, 2010, 2011 ARM. All rights reserved. vii ID102711 Non-Confidentia

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