LogiREF-ZGPU-ZED
logiREF-ZGPU-ZEDXylon logicBRICKSTM Graphics Processing Unit(GPU) Reference Design for Xilinx Zynq -7000 AllProgrammable SoC based ZedBoard from AvnetElectronics MarketingUser’s ManualVersion: 2.02.alogiREF-ZGPU-ZED v2 02 a.docx
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.aAll rights reserved. This manual may not be reproduced or utilized without the prior written permissionissued by Xylon.Copyright Xylon d.o.o. logicBRICKSTM is a registered Xylon trademark.All other trademarks and registered trademarks are the property of their respective owners.This publication has been carefully checked for accuracy. However, Xylon does not assume anyresponsibility for the contents or use of any product described herein. Xylon reserves the right tomake any changes to product without further notice. Our customers should ensure to take appropriateaction so that their use of our products does not infringe upon any patents.Copyright Xylon d.o.o. 2015 All Rights ReservedPage 2 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 20151Version: v2.02.aINTRODUCTION .51.1DESIGN DELIVERABLES.61.1.1 Hardware Design Files .61.1.2 Software .61.1.3 Binaries .71.2USAGE MODES.71.2.1 Quick Evaluation with no HW and/or SW Changes .71.2.2 Develop Standalone and Linux Software, no HW Changes .71.2.3 Full GPU Customization, HW and SW Changes .71.3XILINX DEVELOPMENT SOFTWARE .81.4GRAPHICS DEMO PREVIEW .82LOGICBRICKS IP CORES .92.1ABOUT LOGICBRICKS IP LIBRARY .92.2EVALUATION LOGICBRICKS IP CORES . 102.3LOGICBRICKS IP CORES USED IN THIS DESIGN . 112.3.1 logiCVC-ML Compact Multilayer Video Controller . 112.3.2 logiBITBLT Block Transfer 2D Graphics Accelerator. 122.3.3 logi3D Scalable 3D Graphics Accelerator . 122.3.4 logiCLK Programmable Clock Generator . 132.4LOGICBRICKS IP CORES FOR VIDEO PROCESSING . 143GET AND INSTALL THE REFERENCE DESIGN . 153.1REGISTRATION PROCESS. 153.2INSTALLATION PROCESS . 173.2.1 Filesystem Permissions of the Installed Directory (Windows 7). 193.3DIRECTORY STRUCTURE. 194GETTING LOGICBRICKS EVALUATION LICENSES . 225LOGIREF-ZGPU-ZED DESIGN . 255.1DESIGN CUSTOMIZATION . 265.2MEMORY LAYOUT . 285.3RESTORING FULL SOC DESIGN FROM XYLON DELIVERABLES . 296VIDEO OUTPUT CLOCKING . 306.1LOGICVC-ML – STANDARD DISPLAY RESOLUTIONS AND PIXEL CLOCK . 306.2UTILITY CLOCK MODULE . 316.3LINUX FRAME BUFFER – CHANGING DISPLAY RESOLUTIONS . 327QUICK START. 347.1REQUIRED HARDWARE . 347.2SET UP THE ZEDBOARD FOR USE WITH PRECOMPILED LINUX DEMOS FROM THE SD CARD . 347.3RUNNING PRECOMPILED DEMOS FROM THE SD CARD IMAGE . 367.3.1 BootUp Menu. 367.3.2 Running 3D Demo Apps . 377.3.3 Running QT Demo Apps . 377.4CHANGE THE DEMO APPLICATIONS OR DESIGN NEW APPLICATIONS FROM SCRATCH . 387.4.1 Xilinx Development Software . 387.4.2 Set Up Linux System Software Development Tools . 387.4.3 Set Up git Tools . 388SOFTWARE DOCUMENTATION . 39Copyright Xylon d.o.o. 2015 All Rights ReservedPage 3 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a8.1SOFTWARE INSTRUCTIONS – STANDALONE SOFTWARE . 398.2SOFTWARE INSTRUCTIONS – LINUX SOFTWARE. 399REVISION HISTORY . 40Copyright Xylon d.o.o. 2015 All Rights ReservedPage 4 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a1 INTRODUCTIONXylon’s logicBRICKS library of IP cores optimized for Xilinx All Programmable devices includesseveral graphics logicBRICKS IP cores for full range implementation of 2D and 3D GraphicsProcessing Units (GPU) on Xilinx Zynq-7000 All Programmable SoC and FPGAs. This user’s manualdescribes Xylon’s logiREF-ZGPU-ZED 2D and 3D GPU reference design for the ZedBoard, acommunity oriented development kit from Avnet Electronics Marketing. The ZedBoard is an idealstarter platform for designers and students who are interested in exploring and prototyping theirapplication ideas for the new Zynq-7000 All Programmable SoC.Figure 1: The ZedBoard Development Kit Running Xylon’s 3D Graphics Demo(Video clip: x)This free and pre-verified logicBRICKS reference design includes evaluation logicBRICKS IP coresand hardware design files prepared for Xilinx Vivado Design Suite. It also includes the completeLinux OS image, software drivers, demo applications and documentation.The offered evaluation hardware design is customizable. logicBRICKS IP cores can be setupthrough Vivado IP Integrator (IPI) to support only required graphics features required by theCopyright Xylon d.o.o. 2015 All Rights ReservedPage 5 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.aapplication; from small and efficient display control that uses just a fraction of programmable logic inthe smallest Z-7010 Zynq-7000 AP SoC device, up to the full 3D accelerated graphics engine.The provided software drivers and libraries include standard Linux Framebuffer driver, Qtapplication framework and OpenGL ES 1.11 API.Standard software drivers enable software developers to work fast and efficiently with populargraphics libraries, widget toolkits and familiar development tools. Xylon also supplies bare-metalsoftware drivers for non-OS use.Aside from the logicBRICKS software support for the Linux OS, Xylon also provides softwaredrivers for other popular operating systems running on the Zynq-7000 AP SoC: Android , QNX andMicrosoft Windows Embedded Compact. A number of Xilinx partners who provide BSPs (BoardSupport Package) for different operating systems support Xylon logicBRICKS IP cores for graphics.To learn more about the available software support, please ence-logicBRICKS-Design/OS-IP-CoreSupport.aspx.1.1 Design Deliverables1.1.1 Hardware Design Files Configuration bitstream file for the programmable logic and the SDK export of the referencedesign that allows for an immediate start and software changesZedBoard reference design prepared Vivado Design SuiteXylon evaluation logicBRICKS IP cores: logiCVC-ML Compact Multilayer Video Controller logiBITBLT Bit Block Transfer 2D Graphics Accelerator logi3D Scalable 3D Graphics Accelerator logiCLK Programmable Clock Generator1.1.2 Software logicBRICKS standalone (bare-metal drivers) with driver examplesZynq FSBL sources and the Xilinx SDK project – custom version for standalone applicationsLinux Framebuffer driver for the logiCVC-ML IP core (display controller IP core)Qt5 XylonQPA plugin for 2D hardware acceleration (logiBITBLT 2D graphics accelerator IPcore)HMI demo application that uses Qt application framework for GUI capabilitieslogi3D example sources and binaries (OpenGL ES 1.11 library for the logi3D IP core may beprovided on request)1Product is based on a published Khronos specification, and is expected to pass the Khronos ConformanceTesting Process. Current conformance status can be found at www.khronos.org/conformance.Copyright Xylon d.o.o. 2015 All Rights ReservedPage 6 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a1.1.3 Binaries Precompiled SD Card image for the fastest demo startupFirst Stage Bootloader (FSBL)standalone logiCVC-ML and logiBITBLT examplesLinux binaries: uboot, devicetree (dtb), root file system (uramdisk) uImage – kernel with the Framebuffer driver for the logiCVC-ML IP core OpenGL ES 1.1 simple example and Xylon 3D demo1.2 Usage ModesThe logiREF-ZGPU-ZED reference design can be used in different ways, which are listed in thisparagraph and thoroughly explained throughout this document.1.2.1 Quick Evaluation with no HW and/or SW Changes Download and install the logiREF-ZGPU-ZED reference design (see chapter 3 GET ANDINSTALL THE REFERENCE DESIGN)Setup the demo hardware and use the provided SD card image to run precompiled demoapplications (paragraph 7.2 Set Up the ZedBoard for Use with Precompiled Linux DemosFrom the SD Card)1.2.2 Develop Standalone and Linux Software, no HW Changes Download and install the logiREF-ZGPU-ZED reference design (chapter 3 GET AND INSTALLTHE REFERENCE DESIGN)Setup the demo hardware (paragraph 7.2 Set Up the ZedBoard for Use with PrecompiledLinux Demos From the SD Card)Use the provided Zynq-7000 AP SoC as it is (binaries)Follow instructions for working with logicBRICKS stand-alone (bare-metal) or Linux drivers(please get the full instructions in the start.html file from your installation root directory)Develop software applications prior to the availability of the actual target system1.2.3 Full GPU Customization, HW and SW Changes Download and install the logiREF-ZGPU-ZED reference design (chapter 3 GET AND INSTALLTHE REFERENCE DESIGN)Setup the demo hardware (paragraph 7.2 Set Up the ZedBoard for Use with PrecompiledLinux Demos From the SD Card)Obtain logicBRICKS evaluation licenses from Xylon (chapter 4 GETTING LOGICBRICKSEVALUATION LICENSES)Use the provided Zynq-7000 AP SoC to add or remove more logicBRICKS IP cores and/orthird-party IP cores, or to change logicBRICKS IP settings through the GUIImplement new Zynq-7000 AP SoC designCopyright Xylon d.o.o. 2015 All Rights ReservedPage 7 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015 Version: v2.02.aDevelop software by following instructions listed in the start.html file from your installation rootdirectory1.3 Xilinx Development SoftwareThe logiREF-ZGPU-ZED reference design and Xylon logicBRICKS IP cores are fully compatiblewith Vivado Design Suite 2014.4. Future design releases shall be synchronized with the newest Xilinxdevelopment tools.Licensed users of the Xilinx tools can use their existing software installation for the logiREF-ZGPUZED evaluation.1.4 Graphics Demo PreviewThe logiREF-ZGPU-ZED reference design is functionally identical to the logiREF-ZGPU-ZC702reference design prepared for Xilinx Zynq-7000 All Programmable SoC ZC702 Development Kit.Please check Xylon’s Video Gallery web pages eo-Clip.aspx) to preview the graphicsdemo applications provided with the logiREF-ZGPU-ZED installation for your ZedBoard developmentkit.Figure 2: Screenshots from Some Demos Provided with the Reference DesignCopyright Xylon d.o.o. 2015 All Rights ReservedPage 8 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a2 LOGICBRICKS IP CORES2.1 About logicBRICKS IP LibraryXylon’s logicBRICKS IP core library provides IP cores optimized for Xilinx FPGA and Zynq-7000 AllProgrammable SoC. logicBRICKS IP cores shorten development time and enable fast design ofcomplex embedded systems based on Xilinx All Programmable devices.The key features of the logicBRICKS IP cores are: Compatibility with the Xilinx Vivado and ISE Design Suites – logicBRICKS can be used insame ways as Xilinx IP cores and require no skills beyond general tools knowledge.logicBRICKS users can setup IP core feature sets and programmable logic utilization throughXilinx implementation tools’ Graphical User Interface (GUI). Each logicBRICKS IP core comes with the extensive documentation, reference designexamples and can be evaluated on reference hardware platforms. Xylon provides evaluationlogicBRICKS IP cores to enable risk-free evaluation prior to purchase. Broad software support – from bare-metal software drivers to standard software drivers fordifferent operating systems (OS). Standard software support allows graphics designers andsoftware developers to use logicBRICKS in a familiar and comfortable way. Xylon assures skilled technical support.Figure 3: logicBRICKS IP Cores Imported into the Vivado CatalogCopyright Xylon d.o.o. 2015 All Rights ReservedPage 9 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a* Some of the latest logicBRICKS IP cores are provided in the Vivado compatible version only. Please visit our web site, orcontact Xylon to learn more about the tools compatibility of the specific logicBRICKS IP core.The Figure 3 shows imported logicBRICKS IP cores into Vivado Design Suite, while the Figure 4shows a typical logicBRICKS IP core’s configuration GUI.Figure 4: Example of logicBRICKS IP Configuration GUIClick on the Documentation icon in the GUI opens the User’s Manual of the logicBRICKS IP core!2.2 Evaluation logicBRICKS IP CoresXylon offers free evaluation logicBRICKS IP cores which enable full hardware evaluation: Import into the Xilinx ISE Platform Studio (XPS) and Vivado Design SuiteIP parameterization through the tool GUI interfaceBitstream generationIf you need to simulate logicBRICKS IP cores, please contact XylonThe logicBRICKS evaluation IP cores are run-time limited and cease to function after some time.Proper operation can be restored by reloading the bitstream. Besides this run-time limitation, thereare no other functional differences between the evaluation and fully licensed logicBRICKS IP cores.Evaluation logicBRICKS IP cores are distributed as parts of the Xylon reference erence-logicBRICKS-Design.aspx.Copyright Xylon d.o.o. 2015 All Rights ReservedPage 10 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.aSpecific IP cores can be downloaded from Xylon’s web aspx.2.3 logicBRICKS IP Cores Used in This Design2.3.1 logiCVC-ML Compact Multilayer Video ControllerThe logiCVC-ML IP core is an advanced display graphics controller for LCDand CRT displays, which enables an easy video and graphics integration intoembedded systems with Xilinx Zynq-7000 All Programmable SoC and FPGAs.This IP core is the cornerstone of all 2D and 3D GPUs. Though its mainfunction is to provide flexible display control, it also includes hardwareacceleration functions: three types of alpha blending, panning, buffering ofmultiple frames, etc. Supports all Xilinx FPGA familiesSupports LCD and CRT displays (easily tailored for special display types)64x1 to 2048x2048 display resolutionsAvailable SW drivers for: Linux, Android, QNX and Microsoft Windows Embedded CompactOSSupport for higher display resolutions available on requestSupports up to 5 layers; the last one configurable as a background layerConfigurable layers’ size, position and offsetAlpha blending and Color keyed transparencyPixel, layer, or Color Lookup Table (CLUT) alpha blending mode can be independently set foreach layerPacked pixel layer memory organization:o RGB – 8bpp, 8bpp using CLUT, 16bpp Hi-color RGB 565 and True-color 24bppo YCbCr – 16bpp (4:2:2) and 24bpp (4:4:4)Configurable CoreConnectTM PLBv4.6, Xylon XMB or ARM AMBA AXI4 memory interfacedata width (32, 64 or 128)Programmable layer memory base address and strideSimple programming due to small number of control registersSupport for multiple output formats: Parallel display data bus (RGB): 12x2-bit, 15-bit, 16-bit, 18-bit or 24-bit YCbCr 4:4:4 or 4:2:2 output format Digital Video ITU-656: PAL and NTSC LVDS output format: 3 or 4 data pairs plus clock Camera link output format: 4 data pairs plus clock DVI output formatSupports synchronization to external parallel inputVersatile and programmable sync signals timingDouble/triple buffering enables flicker-free reproductionDisplay power-on sequencing control signalsParametrical VHDL design that allows tuning of slice consumption and features setCopyright Xylon d.o.o. 2015 All Rights ReservedPage 11 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015 Version: v2.02.aAvailable for Xilinx Vivado Design Suite and ISE XPS implementation toolsMore info: xDatasheet: s/IP/logiCVC-ML hds.pdf2.3.2 logiBITBLT Block Transfer 2D Graphics AcceleratorThis 2D graphics accelerator speeds up the most common GUI operationsand off-loads the processor. The logiBITBLT transfers graphics objects fromone to another part of system’s on-screen or off-screen video memory, andperforms different operations during transfers, such as ROP2 rasteroperations, bitmap scaling (stretching) and flipping, Porter & Duff compositingrules or transparency. Supports Xilinx Zynq-7000 AP SoC and all Xilinx FPGA familiesAvailable SW drivers for Linux and Microsoft Windows Embedded Compact OSSupports move operations, in positive and negative directionSupports 16 different ROP2 operationsIntegrated bitmap flipping and optional up/down scalingPorter-Duff composition with/without global alphaColor-keyed transparency, source and destinationAnti-aliased 8-bit font expansionPattern fill with 8x8 pixels patternsSolid fill with any of the supported color formatsSupported color formats: RGB8, ARGB8, RGB16, ARGB16, RGB24, and ARGB24Control of pixel alpha blending factorsARM AMBA AXI4 and AXI4-Lite bus compliantMemory layout configurable for big or little endiannessAvailable for Xilinx Vivado Design Suitre and ISE XPS implementation toolsMore info: xDatasheet: s/IP/logiBITBLT hds.pdf2.3.3 logi3D Scalable 3D Graphics AcceleratorThe logi3D Scalable 3D Graphics Accelerator IP core is a 3D GraphicsProcessing Unit (GPU) IP core developed for embedded systems based on theXilinx Zynq-7000 All Programmable SoC.The IP is designed to support the OpenGL ES 1.1 API specifications – aroyalty-free, cross-platform API for full-function 2D and 3D graphics onembedded systems – including consoles, phones, appliances and vehicles. Graphics Accelerator IP designed to support the OpenGL ES 1.1 API (Common Profile)Conformant to the AMBA AXI4 bus specifications from ARMCompatible with popular operating systems: Linux, Android and Microsoft Windows EmbeddedCompactFPGA resource-effective 3D accelerationCopyright Xylon d.o.o. 2015 All Rights ReservedPage 12 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015 Version: v2.02.aARM CortexTM -A9 CPU Core with NEONTM runs the geometry engine and optimizes the IP’ssizeThe logi3D can be used with different CPUsHardware implemented 3D graphics algorithms: Occlusion culling Gouraud shading MIP-MAP level of the texture per pixel Texture filtering: point sampling, bilinear filtering and trilinear filtering Fog function per vertex Alpha Blending Full Screen Anti-aliasingParametrical VHDL design that allows tuning of slice consumption and features setAvailable for Xilinx Vivado Design Suite and ISE XPS implementation toolsMore info: asheet: s/IP/logi3D hds.pdf2.3.4 logiCLK Programmable Clock GeneratorThe logiCLK is a programmable clock generator IP core featuring twelveindependent and fully configurable clock outputs. While six clock outputs canbe fixed by generic parameters prior to the implementation, the other six clockoutputs can be either fixed by generics or dynamically reconfigured in aworking device. The Dynamic Reconfiguration Port (DRP) interface givessystem designers the ability to change the clock frequency and other clockparameters while the design is running by mean of a set of PLL registers. Supports Xilinx Zynq-7000 All Programmable SoC, 7 series and Spartan -6 FPGAsProvides 12 independent clock outputs that can be configured by generic parameters:o 6 outputs can be dynamically configured through the DRP interfaceo 6 outputs can be configured by generics onlyInput clock frequency range (depends on the used device’s speed grade):o Spartan-6: 19 – 540 MHzo 7 series: 19 – 1066 MHzOutput clocks frequency range:o Spartan-6: 3.125 – 400 MHzo 7 series: 6.25 – 741 MHzConfigurable ARM AMBA AXI4-Lite and CoreConnect PLBv46 compliant registers interfaceSoftware support for Linux and Microsoft Windows Embedded Compact operating systemsAvailable for Xilinx Vivado Design Suite and ISE XPS implementation toolsMore info: tasheet: s/IP/logiCLK hds.pdfCopyright Xylon d.o.o. 2015 All Rights ReservedPage 13 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a2.4 logicBRICKS IP Cores for Video ProcessingXylon offers several logicBRICKS IP cores for video processing on Xilinx Zynq-7000 AllProgrammable SoC and FPGA programmable devices, which can be used as extensions to Xylon 2Dand 3D graphics engines, or as key IP cores for video-only embedded applications.All logicBRICKS IP cores support ARM AMBA AXI4 on-chip bus and can be easily mixed together,or with Xilinx and third-party IP cores.logiVIEW Perspective Transformation and Lens Correction Image ProcessorRemoves fish-eye lens distortions and executes programmable transformations onmultiple video inputs in a real time. Programmable homographic transformationenables: cropping, resizing, rotating, transiting and arbitrary combinations. Arbitrarynon-homographic transformations are supported by programmable Memory LookUp Tables (MLUT).More info: atasheet: s/IP/logiVIEW hds.pdflogiWIN Versatile Video InputEnables easy implementation of video frame grabbers. Input video can be decoded,real-time scaled, de-interlaced, cropped, anti-aliased, positioned on the screen, More info: tasheet: s/IP/logiWIN hds.pdflogiISP Image Signal Processing (ISP) PipelineThe logiISP Image Signal Processing Pipeline IP core is a full high-definition ISPpipeline designed for digital processing and image quality enhancements of aninput video stream in Smarter Vision embedded designs based on Xilinx Zynq-7000All Programmable SoC and 7 Series FPGA devices.More info: tasheet: s/IP/logiISP hds.pdfCopyright Xylon d.o.o. 2015 All Rights ReservedPage 14 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.a3 GET AND INSTALL THE REFERENCE DESIGNXylon offers several logicBRICKS reference designs for different hardware platforms. Shortdescriptions of all Xylon logicBRICKS reference designs can be found e-logicBRICKS-Design.aspx.A quick access to specific reference design is also possible through the main downloads signs-Navigation-Page.aspx.Only registered logicBRICKS users can download logicBRICKS reference designs. Unregisteredusers will be re-directed to the User Login page. The download link is automatically sent by an e-mail,which means that the registration process requires access to the e-mail account. Xylon referencelogicBRICKS designs can be downloaded as cross-platform Java JAR self-extracting installers.3.1 Registration ProcessRegistration is very quick and simple. If you experience any trouble during the registration process,please contact Xylon Technical Support Service – support@logicbricks.com.Copyright Xylon d.o.o. 2015 All Rights ReservedPage 15 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.aStep 1If you are the registered logicBRICKS user,please type-in your Username andPassword. Unregistered users should clickon the Register button, which will open theregistration form.Figure 5: Registration Process – Step 1Step 2Unregistered users should fill-in theregistration form from the Figure 6 . Pleasetake care on required form’s fields. YourUsername is an actual e-mail account usedfor communication with Xylon logicBRICKS.Xylon accepts only valid company e-mailaccounts.Figure 6: Registration Process – Step 2Step 3Figure 7: Registration Process – Step 3Copyright Xylon d.o.o. 2015 All Rights ReservedAs soon as your registration form getsaccepted by Xylon, you get a confirmationmessage. Please check your e-mail to find alink that activates your logicBRICKS account.If you do not get the confirmation message inseveral minutes, please check your SpamFilter or Junk Mail directory. If you have notreceived the confirmation message, pleasecontact Xylon support.Page 16 of 40
logiREF-ZGPU-ZED GPUReference DesignUser’s ManualApril 8th, 2015Version: v2.02.aStep 4Click on the logicBRICKS web accountactivation link in the received e-mail, and youwill get the confirmation status message.Please login to proceed.Figure 8: Registration Process – Step 4Step 5As soon as you select an appropriatelogicBRICKS reference design and installerfor your operating system from theDownloads Navigation Page (link bellow),you will get an e-mail with the download linkfor the selected reference design installation.Figure 9: Registration Process – Step on-Page.aspx3.2 Installation ProcessInstallation process is quick and easy. Each logicBRICKS reference design can be downloaded as across-platform Java JAR self-extracting installer. Please make sure that you have a copy of the JRE(Java Runtime Environment) version 6 or higher on your system to run Java applications and applets.Double-click on the installer’s icon to run the self-installing executable to unpack and install thereference design on your PC.At the beginning, you will be requested to accept the reference design evaluation license – Figure10. For installation in Linux OS, please follow gns-Linux-Installation.aspx.If you agree with the conditions from the evaluation licens
From the SD Card) 1.2.2 Develop Standalone and Linux Software, no HW Changes Download and install the logiREF-ZGPU-ZED reference design (chapter 3 GET AND INSTALL THE REFERENCE DESIGN) Setup the demo hardware (paragraph 7.2 Set Up the ZedBoard for Use with P
From the SD Card) 1.2.2 Develop Standalone and Linux Software, no HW Changes Download and install the logiREF-MEDIA-ZED reference design (chapter 4 GET AND INSTALL THE REFERENCE DESIGN) Setup the demo hardware (paragraph 8.2 Set Up the ZedBoard for Use with P
Key is Programmed or Not Show VIN, Mileage & Key Number for Original BMW Remote Keys & Non-Remote Keys JMA TRS5000 AD900 PRO RW4 Bianchi 883 Zed-QX (AD90) The following is a list comparing the features of the Zed-Bull against other Transponder Cloning Tools. COMPARISON Transponder Reading & Identifying Transponder Cloning Zed Bull Zed-BULL X X .
Spark happiness is our promise to elevate your lifestyle, up to the standard of each and every one of our projects. Zed Strip is our latest addition to our model of perfection, where complementing a lifestyle is a commitment and a purpose. ZED STRIP. 03 LOCATION ZED STRIP. d d d 3
ZED Master Trainers, Assessors and Consultants will play a pivotal role in ZED assessment & . Balanced Score Card, Periodic Management Best Business Review, Cross Functional Practices for NPD, Waste Reduction
zed-qx version: 1.0.5 vehicle transponder zed-qx transponder type can zed-qx copy it? which transponder you should use 3.5rl 1997 meg 13 yes t5 nova cl&tl 1999
Arachni & OWASP Zed Attack Proxy Course: Sicurezza delle reti e dei sistemi software AA: 2016/2017. 2 2 1 Arachni . ZAP is a fork of Paros Proxy. 1 5 2 1 OWASP Zed Attack Proxy Functionally
thored three books: Peasant Revolution in Ethiopia: Tigray People’s Liberation Front, 1975–1991 (Cambridge University Press, 1998); The Fate of Sudan: Origins and Consequences of a Flawed Peace Process (Zed Books, 2012); and South Sudan’s Civil War: Violence, Insurgency and Failed Peacemaking (Zed Books, 2019); as well as 35 articles and book chapters on conflict, armed groups, and peace .
Nutrition is an integral aspect of animal husbandry and the pet food trade now makes up a substantial proportion of the animal care industry. Providing animals with the appropriate feeds in the correct quantities, taking into account factors such as species, breed, activity level and age, requires an understanding of the fundamentals of animal nutrition. A balanced diet is vital to the .
