TUSB73x0 Board Design And Layout Guidelines (Rev. E)
TUSB73x0 Board Design and Layout GuidelinesUser's GuideLiterature Number: SLLU149EJune 2011 – Revised February 2016
ContentsPreface . 61Typical System Implementation . 71.12Power . 82.12.22.32.42.52.63102Package Drawing.Routing Between Pads .Pads .Land Pattern Recommendation .Solder Stencil .161719192121222223. 24Internal Chip Trace Length Mismatch .Transmit and Receive Links .PCI-Express Reference Clock Input .PCI Express Reset .PCI Express WAKE/CLKREQ .7.5.1 Leakage Current on Pins WAKE# and CLKREQ# .7.5.2 Recommendations .Wake from S38.19Overview.Internal Chip Trace Length Mismatch .High-Speed Differential Routing .SuperSpeed Differential Routing .PCI Express Connection7.17.27.37.47.5812131315Package and Breakout . 216.16.26.36.46.57Printed Circuit Board Stackup (FR-4 Example) .Return Current and Plane References .Split Planes – What to Avoid .Avoiding Crosstalk .USB Connection . 165.15.25.35.46Overview. 11General High Speed Layout Guidelines . 124.14.24.34.45Overview . 8Digital Supplies . 9Analog Supplies . 9Ground Terminal . 9Capacitor Selection Recommendations . 10USB VBUS . 10Device Reset . 113.14Overview . 724252727272727. 29Overview. 29. 309.1Overview. 30JTAG Interface . 3110.1 Overview. 31Device Input ClockContentsSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
www.ti.com.11.1 Overview.12SuperSpeed Redriver .12.1 Overview.13SMI Pin Implementation .13.1 Overview.14Schematics .14.1 Overview.14.2 TUSB7320 DEMO EVM REVB Schematics .14.3 TUSB7340 DEMO EVM REVB Schematics .Revision History .Revision History .Revision History .Revision History .Revision History .11Differential Pair ESD ProtectionSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments 3
www.ti.comList of Figures41-1.Typical Application . 72-1.TUSB7320 Power Consumption . 82-2.TUSB7340 Power Consumption . 82-3.Board Ground Connection . 93-1.1.1-V Regulator . 114-1.Nominal 4-Layer PCB Stackup . 124-2.PCB Layer Configuration Suggestions . 134-3.Overlapping Analog and Digital Planes4-4.Incorrect Routing . 144-5.Proper Routing. 154-6.Ways to Avoid Crosstalk5-1.USB3 and USB2 Signals from the USB Connector to the Device . 185-2.Length Matching . 185-3.Differential Routing . 206-1.Routing Between Pads . 216-2.Pads . 226-3.Solder Mask . 236-4.Thermal Pad Stencil Thickness7-1.PCIe TX and RX Signals from the Edge Connector to the Device . 247-2.Length Matching at the Device . 257-3.Connection of WAKE# . 289-1.Dual Crystal/Oscillator Footprint. 3011-1.TPD2EUSB30 ESD Protection . 3212-1.Typical Application of SuperSpeed RedriverList of Figures.14152333SLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
www.ti.comList of Tables5-1.Length Mismatch . 177-1.Internal Chip Trace Length Mismatch . 247-2.Transmit and Receive Terminals . 26SLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedList of Tables5
PrefaceSLLU149E – June 2011 – Revised February 2016TUSB73x0 Board Design and Layout GuidelinesThese guidelines are intended to provide developers with the resources needed to properly layout theTUSB7320/TUSB7340. They are intended as a follow-on document to the USB 2.0 Board Design andLayout Guidelines (SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0differential pair (DP/DM). A layout for the TUSB7340 will seamlessly accommodate the TUSB7320.This document is focused on the layout and routing of the USB 3.0 SuperSpeed USB and PCI Express. Itis intended for developers familiar with high-speed PCB design and layout. Knowledge of the USB 3.0 andPCI Express specifications and protocols are required as well.TrademarksRelated DocumentationTI Customer DEMO EVM Reference Schematic and Layout filesPCB Design and Layout Guidelines for the USB 2.0 Differential Pair (SPRAAR7)PCI Express Card Electromechanical 2.0 /pciexpress/base2USB 3.0 Specification: http://www.usb.org/developers/docsPCI Express Base Specification 2.1: SB73x0 Board Design and Layout GuidelinesSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Chapter 1SLLU149E – June 2011 – Revised February 2016Typical System Implementation1.1OverviewThe TUSB73x0 is an xHCI SuperSpeed USB host controller that interfaces to the PC host system via aPCIe x1 Gen 2 or PCIe Gen 1 interface, providing SuperSpeed, High-speed, Full-speed, or Low-speedconnections on the downstream USB ports. The TUSB7340 supports up to four downstream ports, andthe TUSB7320 supports up to two downstream ports.SS USB DeviceOrHS/FS/LS USBDeviceSS USB DeviceOrTUSB73x0HS/FS/LS USBDevicePCIePCToUSB 3.0Host ControllerSS USB DeviceOrHS/FS/LS USBDeviceSS USB DeviceOrHS/FS/LS USBDeviceFigure 1-1. Typical ApplicationSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedTypical System Implementation7
Chapter 2SLLU149E – June 2011 – Revised February 2016Power2.1OverviewSee Achieving Lowest Power with TUSB73X0.pdf for more information on the settings used to get theselow power numbers.TUSB7320 Power ConsumptionASPM 1/P3 ENABLE 1VCore1.052 SuperSpeed Devices Connected (ACTIVE)2 SuperSpeed Devices Connected (IDLE)1 SuperSpeed Device Connected (ACTIVE)1 SuperSpeed Device Connected (IDLE)PCI D0 - No Device Connected (IDLE)PCI D3 - No Device ConnectedHibernate (ACPI S5) - No Device 0V 1.20717.15295.8070.3570.35Figure 2-1. TUSB7320 Power ConsumptionTUSB7340 Power ConsumptionASPM 1/P3 ENABLE 1VCore1.054 SuperSpeed Devices Connected (ACTIVE)4 SuperSpeed Devices Connected (IDLE)3 SuperSpeed Devices Connected (ACTIVE)3 SuperSpeed Devices Connected (IDLE)2 SuperSpeed Devices Connected (ACTIVE)2 SuperSpeed Devices Connected (IDLE)1 SuperSpeed Device Connected (ACTIVE)1 SuperSpeed Device Connected (IDLE)PCI D0 - No Device Connected (IDLE)PCI D3 - No Device ConnectedHibernate (ACPI S5) - No Device ConnectedmA8807907406585975184203761686363V .401006.35923.40820.50774.30315.0079.3579.35Figure 2-2. TUSB7340 Power Consumption8PowerSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Digital Supplieswww.ti.com2.2Digital SuppliesBoth VDD1P1 and VDD3P3 supplies must have 0.1-µF bypass capacitors to VSS (ground) in order forproper operation. The recommendation is one capacitor for each power terminal. Place the capacitor asclose as possible to the terminal on the device and keep the traces as short and wide as possible to thevias that are used to connect to the power planes. Smaller value capacitors like 0.01 µF are alsorecommended on the digital supply terminals.When placing and connecting all bypass capacitors, high-speed board design rules must be followed.2.3Analog SuppliesSince circuit noise on the analog power terminals must be minimized, an appropriate LC type filter isrecommended for each supply. For EMI concerns, appropriate ferrite beads should be used instead ofinductors in the LC filter circuit.Analog power terminals should have a 0.1-µF bypass capacitor connected to VSS (ground) in order forproper operation. Place the capacitor as close as possible to the terminal on the device and keep thetraces as short and wide as possible to the vias that are used to connect to the power planes. Smallervalue capacitors like 0.01 µF are also recommended on the analog supply terminals.Analog power terminals should have a 0.1-µF bypass capacitor connected to VSS (ground) in order forproper operation. Place the capacitor as close as possible to the terminal on the device and keep thetraces as short and wide as possible to the vias that are used to connect to the power planes. Smallervalue capacitors like 0.01 µF are also recommended on the analog supply terminals.2.4Ground TerminalThe thermal pad is also the board ground connection. Care should be taken to make sure any traces orvias under the device are far enough away from the thermal pad to prevent shorts. As shown in Figure 23, it is recommended to have at least 16 vias connecting the thermal pad to the board ground plane.Figure 2-3. Board Ground ConnectionSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedPower9
Capacitor Selection Recommendations2.5www.ti.comCapacitor Selection RecommendationsWhen selecting bypass capacitors, X7R-type capacitors are recommended. The frequency versusimpedance curves, quality, stability, and cost of these capacitors make them a logical choice for mostcomputer systems.The selection of bulk capacitors with low-ESR specifications is recommended to minimize low frequencypower supply noise. Today, the best low-ESR bulk capacitors are radial leaded aluminum electrolyticcapacitors. These capacitors typically have ESR specifications that are less than 0.01 Ω at 100 kHz. Also,several manufacturers sell “D” size surface mount specialty polymer solid aluminum electrolytic capacitorswith ESR specifications slightly higher than 0.01 Ω at 100 kHz. Both of these bulk capacitor optionssignificantly reduce low-frequency power supply noise and ripple.2.6USB VBUSThe TPS2560 is a dual channel power distribution switch that can handle high capacitive loads and shortcircuit conditions. The output current for each channel can be adjusted up to 2.8 A, making it ideal for SSUSB ports.Each channel can be seamlessly and independently controlled by the TUSB73x0. The TPS2560 alsoprovides a seamless, per port fault indication. Refer to the datasheet for more information regarding thisdevice.More information can be found at: 0.html10PowerSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Chapter 3SLLU149E – June 2011 – Revised February 2016Device Reset3.1OverviewThere is no GRST# timing constraint with respect to the power supplies, other than it should not bedeasserted until the power supplies are stable.However, extreme care must be taken if a passive reset is used, such as using the internal GRST# pull upor an external RC circuit, to ensure that the GRST# does not deassert until the 3.3-V and 1.1-V rails arewithin 10% of nominal. If the 3.3-V power ramps before the 1.1-V supply, and GRST# is deasserted, thedevice I/O is in an undefined state before the core logic is active. This allows the potential for the GRST#I/O cell to incorrectly configure as an output and drive the GRST# signal high until the core logic ispowered on and correctly configures the cell.It is highly recommended that the GRST# input be connected to a power good output from a power supplyto ensure that it does not deassert until both the 3.3-V and 1.1-V power rails are within 10% of theirnominal value. The recommended sequence is to have the 3.3-V feed a 1.1-V regulator and then use the1.1-V Power Good signal to drive GRST# as outlined below.BOARD 1P1VB O ARD 3P3VB O ARD 3P3VR 3110K04025%U5R 324.7K04025%EN 1P 11011BIAS0.01uFSS1P1SSTPS74401RGW TR 3433004025%C 72O UTO UTO UTO UTENC 7115PGFBNCNCNCNCNCNCG NDPADC 6910uFININININ9G RSTZ1201918C 8516FB 1P T1V2341314171221LED3VD5LED G reen 08055678N O PO PR 331.87K04021%0.1uFC 7022uFR 354.99K04021%Figure 3-1. 1.1-V RegulatorSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedDevice Reset11
Chapter 4SLLU149E – June 2011 – Revised February 2016General High Speed Layout Guidelines4.1Printed Circuit Board Stackup (FR-4 Example)Figure 4-1. Nominal 4-Layer PCB Stackup12General High Speed Layout GuidelinesSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Return Current and Plane Referenceswww.ti.comPCB layer configuration suggestions for stackup symmetry and signal integrity.Figure 4-2. PCB Layer Configuration Suggestions4.2Return Current and Plane ReferencesHigh frequency return signal/current is defined as the path that a signal follows back to its original sourceas all signals flow in a closed loop. Minimizing the loop area of the closed loop is beneficial for both EMI(Electro-Magnetic Interference) reduction and signal integrity.The best way to minimize loop area is to always have a signal reference their nearest solid ground orpower plane. Obstructions to the return signal will cause signal integrity problems like reflections,crosstalk, undershoot and overshoot.Signals can reference either power or ground planes, but ground is preferred. Without solid planereferences, single ended and differential impedance control is very hard to accomplish; crosstalk to othersignals may happen as the return signals will have no other path. This type of crosstalk is difficult totroubleshoot.Symmetric pairing of solid planes in the layer stackup can significantly reduce warping of the PCB duringthe manufacturing process. Warping of the PCB is crucial to minimize on boards that utilize BGAcomponents.4.3Split Planes – What to AvoidNever route signals over splits in their perspective reference planes.SLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackGeneral High Speed Layout GuidelinesCopyright 2011–2016, Texas Instruments Incorporated13
Split Planes – What to Avoidwww.ti.comFigure 4-3. Overlapping Analog and Digital PlanesFigure 4-4. Incorrect Routing14General High Speed Layout GuidelinesSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Avoiding Crosstalkwww.ti.comFigure 4-5. Proper Routing4.4Avoiding CrosstalkCrosstalk is defined as interference from one trace to another by either or both inductive and capacitivecoupling. Best ways to avoid crosstalk are: Provide stable reference planes for all high speed signals (as noted in previous sections). Use the 3W rule (3 times the width of trace for separation) where applicable on all signals, butabsolutely use on clock signals. Use ground traces/guards around either “victim” or “aggressor” signals prone to crosstalk. When constrained and space limited on areas of the PCB to route parallel buses, series and/or endtermination resistors can be used to route traces closer than what is normally recommended. However,calculations and simulations must be done to validate the use of series or end termination resistors toeliminate crosstalk.Figure 4-6. Ways to Avoid CrosstalkSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackGeneral High Speed Layout GuidelinesCopyright 2011–2016, Texas Instruments Incorporated15
Chapter 5SLLU149E – June 2011 – Revised February 2016USB Connection5.1OverviewThere are three sets of differential pairs associated with each SuperSpeed USB port. One set for HighSpeed and two sets for SuperSpeed.WARNINGDo not connect the USB2 and SS USB connections on one USB3connector to two different host chips. For instance, do not use theSS USB TX/RX from the TUSB73x0 and the USB2 DP/DM fromanother USB2 host.Doing this may cause USB compliance failures and xHCI driverissues.16USB ConnectionSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
Internal Chip Trace Length Mismatchwww.ti.com5.2Internal Chip Trace Length MismatchRouting of the differential pair on the PCB will need to account for length mismatch in the package. This isdue to offset pin and the associated bond wire mismatch.Table 5-1. Length MismatchNetNameBondwire Length (mil)USB SSTXN DN196USB SSTXP DN1116USB SSRXN DN191USB SSRXP DN1111USB DM DN183USB DP DN1105USB SSTXP DN2104USB SSTXN DN273USB SSRXP DN267USB SSRXN DN294USB DM DN2127USB DP DN293USB SSTXP DN373USB SSTXN DN3103USB SSRXP DN382USB SSRXN DN3113USB DP DN3104USB DM DN3138USB SSTXP DN458USB SSTXN DN482USB SSRXP DN458USB SSRXN DN480USB DM DN486USB DP DN460SLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedDifference (mil)202022312734303134242226USB Connection17
Internal Chip Trace Length Mismatchwww.ti.comFigure 5-1. USB3 and USB2 Signals from the USB Connector to the DeviceFigure 5-2 shows length matching at the device. Length matching must be done at the device side, not atthe connector.Figure 5-2. Length Matching18USB ConnectionSLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments Incorporated
High-Speed Differential Routingwww.ti.com5.3High-Speed Differential RoutingThe high-speed differential pair (USB DM and USB DP) is connected to a type A USB connecter. Thedifferential pair traces should be routed with 90 Ω 15% differential impedance. The high-speed signal pairshould be trace length matched. Max trace length mismatch between high speed USB signal pairs shouldbe no greater than 150 mils. Keep total trace length to a minimum, if routing longer than eight inchescontact TI to address signal integrity concerns.Route differential traces first. Route the differential pairs on the top or bottom layers with the minimumamount of vias possible. No termination or coupling caps are required. If a common mode choke isrequired then place the choke as close as possible to the USB connector signal pins. Likewise ESDclamps should also be placed as close as possible to the USB connector signal pins (closer than thechoke).For more detailed information, you may also see the USB 2.0 Board Design and Layout Guidelines(SPRAAR7) which describes general PCB design and layout guidelines for the USB 2.0 differential pair(DP/DM).5.4SuperSpeed Differential RoutingSuperSpeed consists of two differential routing pairs, a transmit pair (USB SSTXM and USB SSTXP) anda receive pair (USB SSRXM and USB SSRXP). Each differential pair traces should be routed with 90 Ω 15% differential impedance. The high-speed signal pair should be trace length matched. Maximum tracelength mismatch between SuperSpeed USB signal pairs should be no greater than 5 mils. The total lengthfor each differential pair can be no longer than eight inches, this is based on the SS USB compliancechannel spec, and should be avoided if at all possible. TI recommends that the SS diff pairs be as shortas possible.The transmit differential pair does not have to be the same length as the receive differential pair. Keeptotal trace length to a minimum. Route differential traces first. Route the differential pairs on the top orbottom layers with the minimum amount of vias possible. The transmitter differential pair requires 0.1-µFcoupling capacitors for proper operation. The package/case size of these capacitors should be no biggerthan 0402. C-packs are not allowed. The capacitors should be placed symmetrically as close as possibleto the USB connector signal pins.If a common mode choke is required, then place the choke as close as possible to the USB connectorsignal pins (closer than the transmitter capacitors). Likewise, ESD clamps should also be placed as closeas possible to the USB connector signal pins (closer than the choke and transmitter capacitors).It is permissible to swap the plus and minus on either or both of the SuperSpeed differential pairs. Thismay be necessary to prevent the differential traces from crossing over one another. However it is notpermissible to swap the transmitter differential pair with the receive differential pair.It is recommended to use a 2010 pad for the inside pins provided no pad is used for adjacent pins.Instead use a pad on one of the inside pins then for the next pad route the trace between the outer pins toa via.There is enough space to route a 3.78-mil trace between the outside pads while leaving 5-mil spacingbetween the trace and pad, it is then possible to increase the trace width to 4 mils after the breakout. InFigure 5-3 the red pads are USB SS RXP/USB SS RXN and the blue pads areUSB SS TXP/USB SS TXN.SLLU149E – June 2011 – Revised February 2016Submit Documentation FeedbackCopyright 2011–2016, Texas Instruments IncorporatedUSB Connection19
SuperSpeed Differential Routingwww.ti.comFigure 5-3. Differential RoutingIn order to minimize cross-talk on the SS USB differential signal pair, it is recommended that the spacingbetween the TX and RX signal pairs for each interface be five times the width of the trace (5W rule). Forinstance, if the SS USB TX differential pair trace width is 5 mils, then there should be 25 mils of spacebetween the TX and RX differential pairs.If this 5W rule cannot be implemented, then the space between the TX and RX differential pairs should bemaximized as much as possible and ground-fill should be placed between the two. In this case, it is betterto route each differential pair on op
TUSB73x0 Board Design and Layout Guidelines These guidelines are intended to provide developers with the resources needed to properly layout the TUSB7320/TUSB7340. They are intended as a follow-on document to the USB 2.0 Board Design and Layout Guidelines (SPRAAR7) which describes general PCB design
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