Semiconductor Manufacturing Technology

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SemiconductorManufacturing TechnologyMichael Quirk & Julian Serda October 2001 by Prentice HallChapter 9IC Fabrication ProcessOverviewSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda1/41

ObjectivesAfter studying the material in this chapter, you will be able to:1. Draw a diagram showing how a typical wafer flows in asub-micron CMOS IC fab.2. Give an overview of the six major process areas and thesort/test area in the wafer fab.3. For each of the 14 CMOS manufacturing steps, describe itsprimary purpose.4. Discuss the key process and equipment used in each CMOSmanufacturing step.Semiconductor Manufacturing Technologyby Michael Quirk and Julian Serda2/41

Major Fabrication Steps in MOS Process FlowUV n dioxideoxideSilicon atingAlignment and ExposurerrwweePPooRRFFrwePoRFrwePoRFIonized CF4 gasphotoresistoxideDopant gasIonized oxygen gasoxideoxygengate idation(Gate oxide)Ionized CCl4 gasSilane on(Field oxide)oxidePolysiliconMask and EtchScanningion beamresistsilicon nitrideGoxSDIonImplantationContactholestop nitrideSGDActiveRegionsSG DNitrideDepositionS G DContactEtchUsed with permission from Advanced Micro DevicesSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1MetalcontactsG DdrainSMetalDeposition andEtch3/41

CMOS Process Flow Overview of Areas in a Wafer Ion ImplantThin FilmsPolish CMOS Manufacturing Steps Parametric Testing 6 8 weeks involve 350-stepSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda4/41

Model of Typical Wafer Flowin a Sub-Micron CMOS IC FabWafer Fabrication (front-end)Wafer StartUnpatternedWaferCompleted WaferDiffusionTest/SortThin FilmsPolishPhotoEtchImplant6 major production areasSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.25/41

Diffusion: Simplified Schematic of HighTemperature erGas flowcontrollerProcess gasQuartz tubeHeater 1Temperaturesetting voltagesHeater 2Three-zoneHeatingElementsHeater 3PressurecontrollerExhaustCan do : oxidation, diffusion, deposition, anneals, and alloySemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.36/41

Photolithography Bay in a Sub-micronWafer FabYellow fluorescent: do not affect photoresistSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.17/41

Simplified Schematic of aPhotolithography Processing ModuleLoad StationWaferCassettesVaporPrimeResistCoatDevelop- Edge-BeadRinseRemoval Transfer StationWafer Stepper(Alignment/Exposure System)Wafer Transfer SystemSoftBakeCoolPlateCoolPlateHardBakeNote: wafers flow from photolithography into only two other areas: etch and ion implantSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.48/41

Simplified Schematic of Dry Plasma EtcherEtchant gas enteringgas inletGas distribution baffleHigh-frequency energyAnode electrodeRF coax cablePhotonElectromagnetic fielde-e-Free electronλGlow discharge(plasma)Vacuum gaugee-Ion sheathWaferCathode electrode Chamber wallPositive ionRRadicalchemicalVacuum lineSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.5Flow of byproducts andprocess gasesExhaust tovacuum pump9/41

Simplified Schematic of Ion ImplanterGas cabinetIon sourceFilamentMass resolving slitPlasmaExtraction assemblyAnalyzing magnetAcceleration columnBeamline tubeIon beamLighter ionsProcess chamberHeavyionsGraphiteSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.6Scanningdisk10/41

Thin Film Metallization BayPhoto courtesy of Advanced Micro DevicesSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.211/41

Simplified Schematics of CVD Processing SystemGas inletCapacitivecoupled RF inputProcess chamberChemical vapor depositionWaferSusceptorExhaustHeat lampsCVD cluster toolSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.712/41

Polish Bay in a Sub-micron Wafer FabPhoto courtesy of Advanced Micro DevicesSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.313/41

CMOS Manufacturing Steps1. Twin-well Implants14Passivation layer2. Shallow Trench IsolationBonding pad metalILD-63. Gate Structure4.ILD-5Lightly Doped Drain ImplantsM-4135. Sidewall SpacerILD-4M-36. Source/Drain ImplantsILD-3127. Contact FormationM-2118. Local InterconnectM-19. Interlayer Dielectric to Via-1Via10. First Metal Layer11. Second ILD to Via-212. Second Metal Layer to Via-313. Metal-3 to Pad Etch14. Parametric TestingSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaILD-2ILD-19Poly gate8LI metaln 27103p 5LI oxidep STI4n-welln n p 6p-well1p-Epitaxial layerp Silicon substrate14/41

n-well Formation Epitaxial layer : improved quality and fewer defect In step 2, initial oxide: (1) protects epi layer fromcontamination, (2) prevents excessive damage toion/implantation, (3) control the depth of the dopant duringimplantation In step 5, anneal: (1) drive-in, (2) repair damage, (3)activationPhosphorus otoEtch4Oxide4n-well5 5 um1Implantp- Epitaxial layerp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.8(Dia 200 mm, 2 mm thick)15/41

p-well FormationBoron EtchOxiden-well22p-well3p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.916/41

STI Trench EtchSTI: shallow trench isolation1.2.3.4.Barrier oxide: a new oxideNitride: (1) protect active region, (2) stop layer during CMP3rd maskSTI etchingSelective etching opens isolation regions in the epi layer. ist2Nitride1Oxiden-well4p-wellSTI trenchp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1017/41

STI Oxide Fill1.2.Liner oxide to improve the interface between the silicon and trench CVD oxideCVD oxide depositionTrench fill by chemical vapor depositionOxide2ThinFilms2PolishTrench CVD oxideNitride1DiffusionPhotoEtch1p-welln-wellLiner oxidep- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1118/41

STI Formation1.2.Trench oxide polish (CMP): nitride as the CMP stop layer since nitride is harder than oxideNitride strip: hot phosphoric acidPlanarization by chemical-mechanical polishing11ThinFilmsPolishPhotoEtchSTI oxide after polish2Nitride strip2Diffusionp-welln-wellLiner oxidep- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1219/41

Poly Gate Structure Process1.2.3.4.Oxide thickness 1.5 5.0 nm is thermal grownPoly-Si 300 nm is doped and deposited in LPCVD using SiH4Need Antireflective coating (ARC), very criticalThe most critical etching step in dry ondeposition1PhotoresistARC24Poly gate etchGate oxideEtchp-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1320/41

n LDD Implant1.2.3.LDD: lightly doped drain to reduce S/D leakageLarge mass implant (BF2, instead of B, As instead of P) and amorphoussurface helps maintain a shallow junction5th mask2ThinFilmsPolishPhotoEtch1Arsenic n- LDD implantPhotoresist mask1Diffusionn-n-welln-p-welln-2p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1421/41

p LDD Implant1.2.6th maskIn modern device, high doped drain is used to reduce seriesresistance. It called S/D extension2ThinFilmsPolishPhotoEtchBF2 p- LDD implant1Photoresist llp-2p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1522/41

Side Wall Spacer FormationSpacer is used to prevent higher S/D implant from penetrating too close to the channel21ThinFilmsSpacer etchback by anisotropic plasma etcherPolish1 IonsSpacer oxideSide wall - Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1623/41

n Source/Drain Implant1.2.Energy is high than LDD I/I, the junction is deep7th mask2ThinFilmsPolishPhotoEtch1Arsenic n S/D implantPhotoresist mask1Diffusionn n-welln p-welln 2p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1724/41

p Source/Drain Implant1.2.8th maskUsing rapid thermal anneal (RTA) to prevent dopantspreading and to control diffusion of dopant2ThinFilmsPolishPhotoEtchBoron p S/D implant1Photoresist Maskmask1Photoresist1Diffusion3n p n-wellp n p-welln p 2p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1825/41

Contact Formation1.Titanium (Ti) is a good choice for metal contact due to lowresistivity and good adhesionNo mask needed, called self-alignUsing Ar to sputtering metalAnneal to form TiSi2, tisilicideChemical etching to remove unreact Ti, leaving TiSi2, calledselective etching2.3.4.5.1123ThinFilmsPolishTitanium depostion2Titanium etchTisilicide contact formation (anneal)3DiffusionPhotoEtchn p n-wellp n p-welln p p- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.1926/41

LI Oxide as a Dielectric for Inlaid LI Metal(Damascene)Damascene: a name doped of year ago from a practice that began thousands ago by artist in Damascus, SyriaLI metalLI oxideLI: local interconnectionSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2027/41

LI Oxide Dielectric Formation1.2.3.4.Nitride: protect active regionDoped oxideOxide polish9th mask2 Doped oxide CVD321ThinFilms1 Nitride CVD3 Oxide polish4 LI oxide etchPolishLI oxide4DiffusionPhotoEtchp-wellp-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2128/41

LI Metal FormationTi/TiN is used: Ti for adhesion and TiN for diffusion barrierTungsten (W) is preferred over Aluminum (Al) for LI metaldue to its ability to fill holes without leaving voids1Diffusion234ThinFilmsPolishPhotoEtchTi/TiN2 deposition3 Tungstendeposition4 LI tungsten polishLI oxide1Ti depositionp-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2229/41

Via-1 Formation1.2.3.Interlayer dielectric (ILD): insulator between metalVia: electrical pathway from one metal layer to adjacent metal layer10 th mask1 ILD-1 oxidedeposition2 Oxide polish21ThinFilmsILD-1 oxide etch3 (Via-1 formation)ILD-1PolishLI oxide3DiffusionPhotoEtchp-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2330/41

Plug-1 Formation1.2.3.4.Ti layer as a glue layer to hold WTiN layer as the diffusion barrierTungsten (W) as the viaCMP W-polishTi/TiN2 deposition1Diffusion234ThinFilmsPolishPhotoEtch3 Tungstendeposition1Ti dep.4 Tungsten polish (Plug-1)ILD-1LI oxidep-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2431/41

SEM Micrographs of Polysilicon,Tungsten LI and Tungsten PlugsTungsten LIPolysiliconTungstenplugMag. 17,000 XMicrograph courtesy of Integrated Circuit EngineeringSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.432/41

Metal-1 Interconnect Formation1. Metal stack: Ti/Al (or Cu)/TiN is used2. Al(99%) Cu (1%) is used to improve reliability3. 11th maskTi Deposition112TiN3 depositionAl Cu (1%)2 deposition34 Metal-1 etchILD-1ThinFilmsPolishLI oxide4DiffusionPhotoEtchp-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2533/41

SEM Micrographs of First Metal Layerover First Set of Tungsten ViasTiN metal capMetal 1, AlTungstenplugMag. 17,000 XMicrograph courtesy of Integrated Circuit EngineeringSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.534/41

Via-2 Formation1.2.3.4.Gap fill: fill the gap between metalOxide depositionOxide polish12 th mask2ILD-2 oxidedepositionILD-2 oxide etch4 (Via-2 formation)3 Oxide polish1 ILD-2 gap fill1 2ThinFilms3ILD-1PolishLI oxide4DiffusionPhotoEtchp-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2635/41

Plug-2 Formation1.2.Ti/TiN/WCMP W polishTi/TiN2 deposition1 Ti gstendeposition 3(Plug-2)Tungsten4 polishILD-2ILD-1LI oxidep-welln-wellp- Epitaxial layerImplantp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2736/41

Metal-2 Interconnect Formation1.2.3.4.5.Metal 2: Ti/Al/TiNILD-3 gap fillingILD-3ILD-polishVia-3 etch and via deposition, Ti/TiN/WILD-3 oxide3 polishMetal-2 deposition1 to etch2 Gap fill4 Via-3/Plug-3 formationILD-3ILD-2ILD-1LI oxidep-welln-wellp- Epitaxial layerp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2837/41

Full 0.18 µm CMOS Cross SectionPassivation layerBonding pad metalILD-6ILD-51.2.Passivation layer ofnitride is used toprotect from moisture,scratched, andcontaminationILD-6 : oxideM-4ILD-4M-3ILD-3M-2ILD-2M-1ViaILD-1Poly gateLI oxideLI metaln p p STIn-welln n p p-wellp- Epitaxial layerp Silicon substrateSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaFigure 9.2938/41

SEM Micrograph of Cross-section of AMDMicroprocessorMag. 18,250 XMicrograph courtesy of Integrated Circuit EngineeringSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.639/41

Wafer Electrical Test using a Micromanipulator Prober(Parametric Testing)1.2.3.After metal-1 etch,wafer is tested, andafter passivation testagainAutomatically test onwafer, sort good die (XY position, previousmarked with an redink)Before package, waferis backgrind to athinner thickness foreasier slice and heatdissipationPhoto courtesy of Advanced Micro DevicesSemiconductor Manufacturing Technologyby Michael Quirk and Julian SerdaPhoto 9.740/41

Chapter 9 Review SummaryKey TermsReview QuestionsSMT Web SiteReferencesSemiconductor Manufacturing Technologyby Michael Quirk and Julian Serda22222322322441/41

Semiconductor Manufacturing Technology 2/41 by Michael Quirk and JulianSerda Objectives After studying the material in this chapter, you will be able to: 1. Draw a diagram showing how a typical wafer flows in a sub-micron CMOS IC fab. 2. Give an overview of the six major process areas and the sort/test area in the wafer fab. 3.

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