VLSI & E-CAD

VLSI & E-CADIV YEAR I SEMANURAG COLLEGE OF ENGINEERINGAUSHAPUR (V), GHATKESAR (M), MEDCHAL (D)DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERINGDigital System Design Labs1

Digital System DesignLabsDeveloped ByEASI TeamEntuple TechnologiesDigital System Design Labs2

l flow Digital Simulation flow procedure ----------------------------------- 3 Digital Synthesis flow procedure ----------------------------------- 12HDL Code to realize all the logic gates -------------------------------------16Design and simulation of adder, serial binary adder -------------------- 18Design and simulation of carry lookahead adder ------------------------ 22Design of 2 to 4 decoder ---- 25Design of 8 to 3 encoder ---- 26Design of 8 to 1 multiplexer -------------------------------------------------- 28Design of 4 bit binary to gray converter------------------------------------- 30Design of Demultiplexer, Comparator ------------------------------------- 32Design of Full adder using 3 modeling styles------------------------------ 36Design of flip flops: SR, D, JK, T -------------------------------------------- 39Design 4-bit binary counter -------------------------------------------------- 43Design a N-bit Register of SISO, SIPO ------------------------------------ 45Design a N-bit Register of PISO, PIPO ------------------------------------ 48Design of sequence detector (Finite State Machine) -------------------52Design of 4-Bit Multiplier, Divider ------------------------------------------- 54Design of ALU perform- ADD, SUB, AND,OR,1’s & 2’s compliment, -- 57Multiplication, DivisionDigital System Design Labs3

1. Digital Simulation flowCreate a folder in any location. To create a folder right click and select theCreate Folder option.Note: Do not use space in folder name or filename.It will create a folder like below and rename it to your requirement.After creating the folder enter into the location and create a Verilog filespecified below or copy the file to the location.This creates a file shown belowName the file as gates.vDigital System Design Labs4

Double click on gates.v file ( or open it with gedit) and type your Verilog codespecified belowFollow similar procedure to create testbench fileDigital System Design Labs5

Save the files and they should look like below windowRight click in the same folder and give open in terminalRe check the location using “pwd “ command.Now invoke the Cadence tools using below commands from the terminalcshsource /cad/cshrcNow a welcome note appears on the terminal (if the commands are properlyexecuted).Now we will launch the Incisive tool for performing Simulation. Use the belowcommand to invoke the tool.nclaunch -newDigital System Design Labs6

It will invoke the nclaunch window for functional simulation we can compile,elaborate and simulate the design using Multistep option.Create the cds.lib and hdl.var files for to Compile, elaborate and simulate thedesign and test bench, Click on Create cds.lib File option as shown below.CLICKDigital System Design Labs7

CLICKClick save optionSelect OKSelect okDigital System Design Labs8

You can see the below window after giving okLeft side you can see the HDL files, Right side of the window has worklib andsnapshots directories listed.Worklib is the directory where all the compiled codes are stored while Snapshotwill have output of elaboration which in turn goes for simulationCompilation:Digital System Design Labs9

left side select the file and in Tools : launch verilog compiler with current selectionwill get enable. Click it to compile the codeAfter compilation it will come under worklib you can see in right side window.Select the test bench and compile it. It will come under worklib. Under Worklibyou can see the module and testbench. Next is to elaborate the design.Digital System Design Labs10

Elaboration:select the testbench file under worklib and in Tools : launch elaborator withcurrent selection will get enable. select the elaborator to elaborate the design.Choose the test bench and elaborate the designAfter elaboration the file will come under snapshots.Simulatiuon:Select the testbench file under snapshot and in Tools : Launch simulator withcurrent selection will get enable.select simulator to simulate the design. After simulation you will get the twowindows like below image.Digital System Design Labs11

you will get the two windows Design Browser and Simvision .In design browseryou can see the test bench in left side window.Digital System Design Labs12

select the test bench for the gates and Right click it. Select the send to waveformwindow or select the waveform iconyou can see the waveform window after that click the run tool to see thefunctional simulation for the gatesSynthesis Flow:Synthesis will be done using RTL Compiler. It is a script language called ToolCommand Language( TCL)Digital System Design Labs13

Inside the run.tcl file we have to mention the commands like below image.Path for the LibraryFile NameScript file explained below Give the path of the library w.r.t to the directory you are in using thecommand: set attribute lib search path Give the path of the RTL files with respect to the directory you are in usingthe below command: set attribute hdl search path Read the library from the directory specified in giving the path for thelibrary files in First line using the command: set attribute library(slow.lib) is the name of the library file in the directory --library. Read the RTL files from the directory specified in the second line. The RTLfiles are in the directory name : read hdl gates.v Now Elaborate the design using : elaborate command. Synthesize the circuit using the command: synthesize -to mapped -effortmedium.Digital System Design Labs14

Timing could be check using : report timing. Similarly for Gates : reportgates. Check area using : report area. Check Power dissipation using : report power. It will generate the reports Write the hdl code in terms of library components for the synthesized circuitusing the command: write hdl gates netlist.vInvoke RTL Compiler by typing below command on your terminal window. Thebelow picture can be seen after typing the above commandrc -f rc script.tcl -guiNow open gates timing.rep file to observe the timing informationgates power.rep file to observe the powergates area.rep file to observe the area information.Digital System Design Labs15

Double clickThis will show the RTL schematic of the netlist generated.Digital System Design Labs16

2. HDL Code to realize all the logic gatesVerilog Design: timescale 1ns/1psmodule gates (input a,b,output c,d,e,f,g,h,i);assign c a; //NOT gateassign d a b; //OR gateassign e a&b; //AND gateassign f a b; // EX-OR gateassign g (a b); //NOR gateassign h (a&b); // NAND gateassign i (a b); // EX-NOR gateendmoduleVerilog Testbench: timescale 1ns/1psmodule tb();reg a,b;wire c,d,e,f,g,h,i;gates uut i(i));initial begina 0;b 0;#100;a 0;b 1;#100;a 1;b 0;#100;a 1;b 1;#100;a 0;b 0;#100;endendmoduleSimulation Results:Digital System Design Labs17

Synthesis tcl Script:set attr lib search path /cad/FOUNDRY/digital/90nm/libset attr library slow.libset attr hdl search path ./read hdl gates.velaboratesynthesize -to mapped -effort mediumwrite hdl gates netlist.vgui showreport timing gates timing.repreport power gates power.repreport area gates area.repDigital System Design Labs18

3. Design and simulation of adder, serial binary adderVerilog Design:Adder: timescale 1ns/1psmodulefull adder 4bit(input cin,input [3:0]in a,input [3:0]in b,output [3:0]sum,output cout);assign{cout,sum} in a in b cin;endmoduleSerial binary adder: timescale 1ns/1psmodule serial adder(input clk,reset, //clock and resetinput a,b,cin, //note that cin is used for only firstiteration.output reg s,cout //note that s comes out at every clockcycle and cout is valid only for last clock cycle.);reg c,flag;always@(posedge clk or posedge reset)beginif(reset 1) begin //active high resets 0;cout c;flag 0;end else beginif(flag 0) beginc cin; //on first iteration after rst assign cin to c.flag 1; //then make flag 1, so that this if statementisnt executed any more.endcout 0;s a b c; //SUMc (a & b) (c & b) (a & c); //CARRYendendendmoduleDigital System Design Labs19

Verilog Testbench:Adder Testbench: timescale 1ns/1psmoduleadder tb ();reg cin;reg [3:0]in a;reg [3:0]in b;wire [3:0]sum;wire cout;full adder 4bit uut (.cin(cin),.in a(in a),.in b(in b),.sum(sum),.cout(cout));initial beginin a 4'h0;in b 4'h0;cin 1;#100;in a 4'h3;in b 4'h4;cin 1;#100;in a 4'h7;in b 4'h8;cin 0;#100;in a 4'h9;in b 4'h9;cin 0;#100;in a 4'hA;in b 4'hB;cin 1;#100;endendmoduleDigital System Design Labs20

Serial binary adder testbench: timescale 1ns/1psmodule tb;// Inputsreg clk;reg reset;reg a;reg b;reg cin;// Outputswire s;wire cout;// Instantiate the Unit Under Test (UUT)serial adder uut s),.cout(cout));//generate clock with 10 ns clock period.initial beginclk 0;forever #5 clk clk;endinitial begin// Initialize Inputsreset 0;a 0;b 0;cin 0;reset 1;#100;reset 0;//add two 4 bit numbers, 1111 1101 11101a 1; b 1; cin 1;#10;a 1; b 0; cin 0; #10;a 1; b 1; cin 0; #10;a 1; b 1; cin 0; #10;reset 1;#100;reset 0;Digital System Design Labs21

//add two 5 bit numbers, 11011 10001 101101a 1; b 1; cin 1;#10;a 1; b 0; cin 0; #10;a 0; b 0; cin 0; #10;a 1; b 0; cin 0; #10;a 1; b 1; cin 0; #10;reset 1;#50 finish;endendmoduleSimulation Results:Adder results:Serial binary adder results:Digital System Design Labs22

Synthesis tcl Script:Adder tcl:set attr lib search path /cad/FOUNDRY/digital/90nm/libset attr library slow.libset attr hdl search path ./read hdl adder.velaboratesynthesize -to mapped -effort mediumwrite hdl adder netlist.vgui showreport timing adder timing.repreport power adder power.repreport area adder area.repSerial binary adder tcl:set attr lib search path /cad/FOUNDRY/digital/90nm/libset attr library slow.libset attr hdl search path ./read hdl serial adder.velaboratesynthesize -to mapped -effort mediumwrite hdl serial adder netlist.vgui showreport timing serial adder timing.repreport power serial adder power.repreport area serial adder area.rep4. Design of Carry lookahead adderVerilog Design: timescale 1ns/1psmodule CLA Adder(a,b,cin,sum,cout);input[3:0] a,b;input cin;output [3:0] sum;output cout;wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;assign p0 (a[0] b[0]),p1 (a[1] b[1]),Digital System Design Labs23

p2 (a[2] b[2]),p3 (a[3] b[3]);assign g0 (a[0]&b[0]),g1 (a[1]&b[1]),g2 (a[2]&b[2]),g3 (a[3]&b[3]);assign c0 cin,c1 g0 (p0&cin),c2 g1 (p1&g0) (p1&p0&cin),c3 g2 (p2&g1) (p2&p1&g0) (p1&p1&p0&cin),c4 g3 (p3&g2) (p3&p2&g1) (p3&p2&p1&g0) (p3&p2&p1&p0&cin);assign sum[0] p0 c0,sum[1] p1 c1,sum[2] p2 c2,sum[3] p3 c3;assign cout c4;endmoduleVerilog Testbench: timescale 1ns/1psmodule TestModule;// Inputsreg [3:0] a;reg [3:0] b;reg cin;// Outputswire [3:0] sum;wire cout;// Instantiate the Unit Under Test (UUT)CLA Adder uut ial begin// Initialize Inputsa 0;b 0;cin 0;// Wait 100 ns for global reset to finish#100;Digital System Design Labs24

a 5;b 6;cin 1;#100;a 7;b 8;cin 1;// Wait 100 ns for global reset to finish#100 finish;endendmoduleSimulation Results:Synthesis tcl Script:set attr lib search path /cad/FOUNDRY/digital/90nm/libset attr library slow.libset attr hdl search path ./read hdl cl adder.velaboratesynthesize -to mapped -effort mediumwrite hdl cl adder netlist.vgui showreport timing cl adder timing.repreport power cl adder power.repreport area cl adder area.repDigital System Design Labs25

5. Design of 2 to 4 DecoderVerilog Design: timescale 1ns/1psmodule decode(input [1:0]I,output reg[3:0] Y);always @ (I)case (I)2'b00 : Y 4'h1;2'b01 : Y 4'h2;2'b10 : Y 4'h4;2'b11 : Y 4'h8;default : Y 4'h0;endcaseendmoduleVerilog Testbench: timescale 1ns/1psmodule decode tb;// Inputsreg [1:0] I;// Outputswire [3:0] Y;// Instantiate the Unit Under Test (UUT)decode uut (.I(I),.Y(Y) );initial begin// Initialize InputsI 2'b00;// Wait 100 ns for global reset to finish#100; I 2'b01;#100; I 2'b10;#100; I 2'b11;#100 finish;EndendmoduleDigital System Design Labs26