CMOS Digital Circuits

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CMOS Digital Circuits Types of Digital CircuitsCombinationalThe value of the outputs at any time t depends only onthe combination of the values applied at the inputs attime t (the system has no memory)SequentialThe value of the outputs at any time t depends notonly on the values applied at the inputs at time t, butalso on the past sequence of inputs that have beenapplied (the system has memory)1

Logic values and noise marginsVOHVOLVIHnoiseVILVOHVIHVILVOL2

MOS Transistors Four terminals: gate, source, drain, body ( bulk)3

Silicon Lattice Transistors are built on a silicon substrate Silicon is a semiconductor (Group IV material) Forms crystal lattice with bonds to four neighbors4

Dopant atoms Pure silicon has no free carriers and conducts poorly. Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)SiSi- SiSiSi -SiAsSiSiBSiSiSiSiSiSiSiSi5

Types of Transistor Bipolar Junction Transistor (BJT)–NPN and PNP transistors–Small current into very thin base layer controls largecurrent between emitter and collector–Base currents limit integration densityMOS Field Effect Transistor (MOSFET)–NMOS and PMOS FETs–Voltage applied to insulated gate controls current betweensource and drain–Low power allows very high integration6

MOS Transistor symbols7

N-MOSFET operation (1) Body is commonly tied to ground (0 V) When the gate is at a “low” voltage:– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFFSourceGateDrainPolysiliconSiO20n n Spbulk SiD8

N-MOSFET operation (2) When the gate is at a “high” voltage:– Positive charge on gate of MOS capacitor– Negative charge attracted to body– channel under gate gets “inverted” to n-type– Now current can flow through n-type silicon fromsource through channel to drain, transistor is ONSourceGateDrainPolysiliconSiO21n n Spbulk SiD9

P-MOSFET operation Similar BUT doping and voltages are reversed Body tied to “high” voltage (VDD) Gate “low”: transistor ON Gate “high”: transistor OFF Bubble indicates inverted behaviorSourceGateDrainPolysiliconSiO2p p nbulk Si10

What does high and low voltagereally means ? Power Supply Voltage:– GND 0 V– In 1980’s, VDD 5V– VDD has decreased in modern processes– High VDD would damage modern tiny transistors– Lower VDD saves power– VDD 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, 11

MOSFETs as SWITCHES We can model MOS transistors as controlled switches Voltage at gate controls current path from source todrain12

CMOS Inverter ( NOT gate)13

CMOS Technology CMOS technology uses both nMOS and pMOStransistors The transistors are arranged in a structure formed bytwo complementary networks–Pull-up network is complement of pull-down network–Parallel Series–Series Parallel14

CMOS Logic NAND15

CMOS Logic NOR16

CMOS logic gates (a.k.a. Static CMOS) Pull-up network is complementof pull-downParallel SeriesSeries Parallel17

Compound gatesVDDExample: ( A B C ) D AA B C DY01-1100001-0–10111DBCY18

Compound gates19

How good is the output signal ? Strength of signal–How close the signal approximate ideal voltage source VDD and GND rails are the strongest 1 and 0 nMOS and pMOS are not ideal switches –pMOS passes strong 1 , but degraded (weak) 0–nMOS passes strong 0. but degraded (weak) 1THUS:–nMOS are best for the pull-down network–pMOS are best for the pull-up network20

The Pass Transistor Transistors used as switches21

The Transmission Gate Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well22

Static CMOS gates are fullyrestoring In static CMOS, the nMOS transistors only need to pass0’s and the pMOS only pass 1’s, so the output is alwaysstrongly driven and the levels are never degraded This is called a fully restoring logic gate23

Static CMOS is inherently inverting CMOS single stage gates must be inverting For building non inverting functions we need multiplestages24

Tristate Buffer A tristate buffer produce Z when not enabledAEN Y00Z01010Z11125

Non restoring tristate Transmission gate acts as tristate buffer–It takes only 2 transistors–BUT is nonrestoringA is passed to Y as it is(thus, Y is not always a strong 0 or 1)26

Tristate inverter Tristate inverter produces restored output For a non inverting tristate add an inverter in front27

Designing a 2:1 muxD0D1SY0-001-01-010-11128

2:1 mux - gate level approachY D0 S D1 SD1SD0D1SD0 Y424242Y2How many transistors are needed ?Too Many !!! (20 transistors)29

2:1 mux –TG approach We need only 4 transistors (6 to be honest)BUT it is non restoring andit has another issue calledcharge sharingS 1 0LOWHIGHCap(charged)30

inverting muxVDDD0D131

D Latch When CLK 1, latch is transparent– When CLK 0, the latch is opaque– D flows through to Q like a bufferQ holds its old value independent of Da.k.a. transparent latch or level-sensitive latch32

D Latch Design and OperationMultiplexer chooses D orhold Q33

D Flip Flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop34

D Flip Flop Design and Operation Built from master and slave D Laches35

CMOS Digital Circuits Types of Digital Circuits Combinational . – Parallel Series – Series Parallel. 15 CMOS Logic NAND. 16 CMOS Logic NOR. 17 CMOS logic gates (a.k.a. Static CMOS) . nMOS and pMOS are not ideal switches – pMOS passes strong 1 , but degraded (weak) 0

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