Hierarchical Modeling Of Spatial Variability With A 45nm .

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Hierarchical Modeling of Spatial Variability with a 45nm ExampleKun Qian, Borivoje Nikolić and Costas J. SpanosDept. of EECS, University of California, 550 Cory Hall, Berkeley, CA USA 94720ABSTRACTIn previous publications we have proposed a hierarchical variability model and verified it with 90nm test data. Thismodel is now validated with a new set of 45nm test chips. A mixed sampling scheme with both sparse and exhaustivemeasurements is designed to capture both wafer level and chip level variations. Statistical analysis shows that the acrosswafer systematic function can be sufficiently described as parabolic, while the within-die systematic variation is nowvery small, with no discernible systematic component. Analysis of pattern dependent effects on leakage current showsthat systematic pattern-to-pattern LEFF variation is almost eliminated by optical proximity correction (OPC), but stressrelated variation is not. Intentionally introduced gate length offset between two wafers in our dataset provides insight todevice parameter variability and sheds additional light on the underlying sources of process variation.Keywords: circuit variability, across-wafer variation, 45nm, ring oscillator, pattern dependent effect.1. INTRODUCTIONWhile pure random fluctuations impact all devices in modern ICs, significant spatial components across-die and acrosswafers play a key role in the overall performance, leading to a hierarchical process variability model [1]. Used inconjunction with 90nm test data, this model has been shown to successfully address both local variability and variationsacross significant distances. Systematic chip-to-chip and within-chip variations are sufficiently described bydeterministic spatial functions across-wafer and across-die. The residuals of these functions were shown to beidentically, independently, normally distributed (IIND), rendering the concept of “spatial correlation” unnecessary.To verify our model for state-of-the-art technology nodes, we applied it to a new, comprehensive 45nm data set. The testchip was designed by L.T. Pang [6] and manufactured on a state–of-the-art production line. On-chip test structuresinclude arrays of ring-oscillators (RO) replicated with various layout styles, off-state transistors, and an SRAM array,each individually addressable. This allows for accurate and flexible estimation of the hierarchical components of thevariability model.Akrng wafer axisFig. 1: Hierarchical process variability: (a) wafer-to-wafer (b) across-wafer (c) die-to-die (d) across-die (e) patterndependent (f) local random noise [1]This model is originally intended for modeling device parameters such as gate length (LEFF), oxide thickness (TOX), andthreshold voltage (VTH). However, many of these device parameters cannot be directly measured, because of the cost ofthe direct measurement when measuring large, statistically significant samples. Nonetheless, when the variation ofdevice parameters is reasonably small, circuit performance metrics such as frequency may still be treated in the samefashion. However, due to the non-linear dependence on device parameters like LEFF and VTH, new assumptions areneeded. For instance, wafer-to-wafer and pattern-to-pattern variation may no longer be modeled as simple additiveDesign for Manufacturability through Design-Process Integration III, edited by Vivek K. Singh, Michael L. Rieger,Proc. of SPIE Vol. 7275, 727505 · 2009 SPIE · CCC code: 0277-786X/09/ 18 · doi: 10.1117/12.814226Proc. of SPIE Vol. 7275 727505-1

terms, and interactions can occur between wafer-to-wafer variability and all the other components, especially whenwafers are processed under different process conditions.2. TEST CHIP AND PROCESS TECHNOLOGY OVERVIEWThe test chips are fabricated using a 45nm low power CMOS process [7], [8], [9]. The die photo is shown in Fig. 2b.Each die contains a ring oscillator (RO) array with 18 x 16 identical tiles. Each tile consists of 17 ROs and 17 pairs ofoff-state NMOS and PMOS transistors for leakage measurements, each with the same device size embedded in adifferent pattern as shown in Fig. 2a. It should be noted that the pre-OPC patterns depicted in Fig. 2b are subject to OPCtreatment prior to fabrication, and the specifics of this OPC treatment are not known to us. Measurement circuitry isadopted from the design of 90nm test chip [11]. RO frequency and corresponding off-state NMOS/PMOS transistorleakage currents are measured in our laboratory after the wafers have been diced and the chips packaged.All transistor channels are oriented in the 100 direction, which enhances PMOS mobility and makes it insensitive tostress[13]. There are two major sources of stress in this process: strain caused by contact-etch stop layer (CESL) and theshallow trench isolation (STI) stress. Sub-atmospheric chemical vapor deposition oxide (SACVD) largely reducesusually strong compressive STI stress and turns it into a weak tensile one. CESL is formed by intentionally depositing anitride layer on top of NMOS transistors, which introduces strong horizontal tensile strain that greatly enhances theelectron mobility.Another important feature of the new 45nm test chip fabrication is the different gate trimming treatment for the twowafers we have, aiming at a nominal 4nm reduction in gate CD from the slower wafer (#1) to the faster wafer (#2).Other minor changes in process may also exist. This allows us to more precisely identify the link between circuitperformance and device parameters, and enables further investigation into the process variability.nJi5LL81E1I SPILl1ETflnilSP211PSSP3M1(jLxLxrço' diffasion(a)tnznI4NS1ISUUtLi zniflfl8t484Mr assPoly-SiI [EM-C MeasurementADCContactEQ & [EM-C MnayDiffusion16 x 16 8Iesvi(b)(C)(d)Fig. 2: (a) 16 pre-OPC layout configurations, all arranged horizontally. An additional configuration P1 is arranged verticallyand not shown here; (b) 45nm test-chip die photo; (c) Horizontal arrangement; (d) Vertical arrangement [6]3. MEASUREMENT SAMPLING SCHEMETo capture the wafer-level systematic variation we select chips aiming at wide spatial coverage across the wafer, but weonly measure a small subset of the available samples on each of those chips. For instance, on each of the 45nm testwafers, half of the 90 chips on the wafer are sampled, and for each chip we only measured 8 of the available 288 tiles forRO frequency, reducing the overall measurement cost by a factor of 72. Statistical analysis shows that this sparsesampling scheme is reasonably good at capturing the average characteristics of a chip.Proc. of SPIE Vol. 7275 727505-2

Given the total measurement cost, there are various choices of chip selection in order to capture the across-wafersystematic nature of the variability. The most straightforward method would be a checkerboard sampling, as shown inFig. 3a. This method, however, does not take advantage of the spatial property of the wafer-level process variation. Asprocess conditions near the center of the wafer are usually better controlled than closer to the wafer edge, chips near theperiphery of the wafer contribute more to the process variation, requiring a denser spatial pattern. On the other hand,chips near the center of the wafer are likely to be more uniform. An optimized sampling scheme taking into account ofthese effects is shown in Fig. 3b.For within-die variability characterization, however, complete coverage over the die area is desired. Therefore, a smallnumber (5 6) of chips from each wafer are exhaustively sampled by measuring all 288 tiles .xL4aflC2331EE3435 as fl 53as'1IIasa,as646566676363. E mE 'E226!2283247173772687737171/63Fig. 3: (a) Checkerboard sampling scheme (b) weighted sampling scheme. Heavily shaded chips are measured exhaustively.4. DEFINITION OF SYMBOLSMeasured RO frequency and leakage currents can be uniquely labeled as f 0 T ,D,W,P , I LEAKN,0 T ,D,W,P , andI LEAKP,0 T ,D,W,P . To effectively compare the measurement data, RO frequency is normalized to SPICE simulations at anominal LEFF as per pattern using the corner model corresponding to the slower wafer in order to eliminate the impact ofthe difference of parasitic capacitance. Leakage current measurements are subjected to a log transformation prior to thisanalysis, followed by normalization to the average performance measured on pattern P1 of wafer #1. Similar practice isapplied to SPICE simulations as well. The detailed definitions are listed in Table 1.Table 1: Example definitions of symbols of measurement and simulationf 0 T ,D,W,PRaw measurement of RO frequency of tile T, die D, wafer W, and pattern Pfs0 W,P,L EFFSimulated RO frequency using corner corresponding to wafer W, pattern P, andeffective gate length LEFFfs0 W1,P,48Simulated RO frequency for wafer #1, pattern P, at nominal gate length 48nmf T ,D,W,PMeasured RO frequency normalized to SPICE simulation fs0 W1,P,48f 0 T ,D,W,PProc. of SPIE Vol. 7275 727505-3

fs W,P,L EFFSimulated RO frequency normalized to SPICE simulationfs0 W,P,L EFFfs0 W1,P,48f ,D,W,Pf T ,D,W,P averaged over all tiles in die D on wafer W, with pattern P.f ,D,W, f T ,D,W,P averaged over all tiles and all patterns in die D on wafer W.f ,D,W,PAWFitted systematic across-wafer component of RO frequency of die D on wafer Wwith pattern P.I LEAKN,0 T ,D,W,PRaw measurement of NMOS leakage of tile T, die D, wafer W, and pattern PIsLEAKN ,0 W,L EFFSimulated NMOS leakage using compact SPICE model1 corresponding to waferW and effective gate length LEFFlog(I LEAKP,0 ) , ,W1,P1log(I LEAKP,0 ) T ,D,W,P averaged over all devices with pattern P1 on wafer #1.log(I LEAKN ) T ,D,W,Plog(I LEAKP ) T ,D,W,PNormalized NMOS leakage measurement:Normalized PMOS leakage measurement:log(I LEAKN ,0 ) T ,D,W,Plog(I LEAKP,0 ) , ,W1,P1log(I LEAKP,0 ) T ,D,W,Plog(I LEAKP,0 ) , ,W1,P15. WAFER LEVEL VARIATIONSpatial process variation causes device and circuit performance to vary as a function of position within the wafer.According to our hierarchical variation model, the wafer level spatial variation can be decomposed into two parts: thesystematic or deterministic across-wafer function and the random die-to-die variation. Depending on the performancemetric we look at, the systematic variation has shown a dome or bowl shaped signature in various processes [1][12]. Forthe 90nm test data we used a fitted 2nd order polynomial function to capture the across-wafer shape. This methodologyproves valid for the 45nm test chips. As we explain below, however, in the 45nm case the wafer-to-wafer and pattern-topattern variability components now interact with the shape of the across-wafer systematic function.5.1 Across-wafer variationTo extract the across-wafer variation component, we first calculate the chip averages for each pattern style on bothwafers. By taking the mean frequency of all devices with the same pattern on one chip, we obtain one data point for eachmeasured chip on the wafer. Since leakage current changes exponentially with threshold voltage, log(ILEAK) reallyresponds mostly to threshold voltage variation, and not so much to linear factors such as mobility enhancement.Measured frequency and leakage current maps across the wafer for pattern P2 on wafer #2 are shown in Fig. 4.There is a strong correlation among the across-wafer function of frequency, NMOS leakage and PMOS leakage, asshown in Fig. 5. All three types of across-wafer variations can be approximated by a dome-shaped deterministicfunction. This can be explained by a systematic bowl-shape gate length variation across the wafer, and the correspondingthreshold voltage roll-off: RO frequency increases when LEFF gets shorter, and both NMOS and PMOS thresholdvoltages are likely to drop in magnitude due to short-channel effects. Thus log(ILEAKN) and log(ILEAKP) are correlated bythe fact that NMOS and PMOS share the same gate length, while the RO frequency is determined by both NMOS andPMOS threshold voltage and the inverse proportional dependence on gate length.1Since the two wafers in our experiment were produced as different process “splits”, each is modeled with a differentcompact SPICE model, as suggested by the manufacturer.Proc. of SPIE Vol. 7275 727505-4

I09(ILP waler 2. LayouI P2U-IO9(IsN waler 2. LayouI P2EEEIC E.C.EJflII! IIEE iuiuiuiU EEiuiLiAiJJmLIJiJIII IIIIiITIT1UIUIUF1UI 1111liii iiI IIL]ILJIL ILlIIM1II III I IIAlIII!III MI MI 11 MI IIEl I ITTtITITTITTELIE 4E5-0.99-0996COloffloCSIumn(Fig. 4: Wafer maps of (a) f ,D,W 2,P2 (b) log I LEAKN) ,D,W 2,P2()(c) log I LEAKP ,D,W 2,P2 . Symbols indicate dataaveraging across each measured chip. (Note that both leakage plot numbers are in the negative regime)Past analysis of 90nm data shows that the across-wafer systematic variation can be approximated by a 2nd orderpolynomial function of the chip coordinates f(x,y). This is still true for the new 45nm test chips. The fitted across-waferfunctions of RO frequency and leakage currents are shown in Fig. 6. Comparisons of fitted functions to measurementdata are shown in Fig. 7.Modeling freq by NMOS/PMOS leakageDie-to-die variation: NMOS vs. PMOS leak1.3 1.25- Rsquare 51.25kl*Iog(I LEAKN) k2*Iog(I LEAKP)II-0.98 -0.96 -0.94 -0.92 -0 9-1Iog(I LEAKP)Fig. 5: (a) log(I LEAKN ) ,D,W 2,P2 vs. log(I LEAKP ) ,D,W 2,P2 (b) Modeling f ,D,W2,P2 by log(I LEAKN ) ,D,W 2,P2and log(I LEAKP ) ,D,W 2,P2 . Symbols indicate data averaging across each measured chip.Fitted across-wafer frequency mapFitted across-wafer Iog(ILEAKN) map1.3Fitted across-wafer Iog(ILEAKP) map-0.8-0.8-0.85-0.85 --0.9-0.9-x wafer 1, Layout P1o wafer 1, Layout P2o wafer 2, Layout P1 wafer 2, Layout P21.251.21.15z1.1n 1.05000.950.9x wafer 1, Layout P1o wafer 1, Layout P2wafer 2, Layout P1wafer 2, Layout P20.850.80123456-0.95 --0.95x wafer 1, Layout P1o wafer 1, Layout P2wafer 2, Layout P1wafer 2, Layout P2-1.0578position along wafer x-axls910012345678910Fig. 6: Fitted across-wafer functions along the central x-axis: (a) f ,D,W,P(c) log(I LEAKP ) ,D,W ,P0position along wafer x-axisProc. of SPIE Vol. 7275 727505-52345578109position along wafer x-axisAW, (b) log(I LEAKN ) ,D,W ,P. Symbols indicate data averaging across each measured chip.AW1,AW

Fitting: freq of wafer2, layout P2Fitting: Iog(ILEAKN) of wafer2, layout P2Fitting: Iog(ILEAKP) of wafer2, layout 5-0.95fitted Iog(ILEAKN)P .0001 RSq 0.92 RMSE 0.01171.25-0.92-1.00-0.96fitted Iog(ILEAKP)P .0001 RSq 0.88 RMSE 0.0111.00fitted freqP .0001 RSq 0.87 RMSE 0.0409Fig. 7: Fitting across-wafer function for (a) f ,D,W2,P2 , (b) log(I LEAKN ) ,D,W 2,P2 and (c) log(I LEAKP ) ,D,W 2,P2 .Symbols indicate data averaging across each measured chip.5.2 Pattern dependent effectsIn our previous work with 90nm data, the pattern dependent effect was modeled as a simple additive component. Thismeans that the shape of the across-wafer and the across die functions were identical for all measured layout patterns.This assumption still holds true within each chip for the 45nm data, and if we normalize these constants to their chipaverage, the numbers are fairly consistent from chip to chip as shown in Fig. 8. This, however, is no longer true acrossthe wafer. As shown in Fig. 9, the within-die pattern-to-pattern variation range is approximately proportional to the dieaverage for frequency and NMOS leakage measurements. Meanwhile the two are almost uncorrelated for the PMOSleakage current measurement. This implies that for RO frequency and NMOS leakage current, layout effects nowinteract with the shape of the across-wafer systematic variability function. It is noteworthy that due to the apparenteffectiveness of the OPC treatment the PMOS leakage current has little pattern to pattern variation and can still bemodeled as an additive component.Fig. 8 helps explain this behavior. Within-die pattern-to-pattern variation is first normalized to the die average so that theimpact of die-to-die or wafer-to-wafer variation is excluded, then averaged over all the dies on the same wafer.Systematic pattern dependency is observed. Indeed, since PMOS leakage current does not vary much from one pattern tothe next, we must conclude that the OPC algorithm was successful in removing most of the patterning related effects onLEFF. This means that the pattern dependent variation observed in the NMOS leakage current and in RO frequency islikely to be the result of stress related effects on the NMOS devices. (Recall that PMOS current is insensitive to thoseeffects in our configuration). This is further reinforced by the fact that log(ILEAKN) correlates strongly with ROfrequency, but the trend of log(ILEAKP) does not. If LEFF was the underlying reason, one would expect similar behaviorfrom the frequency and both leakage currents.Layout-to-layout Frequency VariationLayout-to-layout Iog(ILEAKN) variationLayout-to-layout Iog(ILEAKP) -0.98--0.98z . 1.02 -0-1-00.98-I-1-1.020.96--1.04-1.060.94012345678910 1214012345678910 1216Fig.8:0 WaferlMeanYpattern-to-patternhere fL D,W,P 012345678910 1216f ,D,W,Pf ,D,W, x Waferl0 Wafer2variations:, INL D,W,P (a)fL ,W,P1416layoutlayoutlayoutY x Waferl149',log(I LEAKN ) ,D,W,Plog(I LEAKN ) ,D,W, (b)x waferl0 wafer2INL ,W,Pand IPL D,W,P Proc. of SPIE Vol. 7275 727505-6,(c)IPL ,W,Plog(I LEAKP ) ,D,W,Plog(I LEAKP ) ,D,W, .,

:bij moApi sA a!p-0-a!pIog(I LEAKN): layout vs. die-to-die0-010-9100-Iog(I LEAKP): layout vs. die-to-die0.140.08 0.07-0.13-DoEl --010Xa 1k'XXSTOD60 160dij1tJJMII0.06S10.04-00o E(X0.03--0X wafer 10 wafer 2XX-0.92 -0.9 -0.88 -0.86 -0.84-0.960.05-0 0.07- oZIJMSIT 11IñP.JA ADunbJJSOT0.08-0.06-0DOIDJo 000.11-0.020.010i-1.02 -1 -0.98-1.06Chip average Iog(ILEAKN)Fig. 9: (a) range f ,D,W,Pvs. log(I LEAKN ) ,D,W, ,f ,D,W, , (b) range log(I LEAKN ) ,D,W,Pvs.PP(c) range log(I LEAKP ) ,D,W,P vs. log(I LEAKP ) ,D,W, -0.94Chip average Iog(ILEAKP)P5.3 Wafer-to-wafer variationWe measured 45nm test chips from two wafers. According to direct gate CD measurement data provided by the line thatproduced our test chips, there is a nominal 4nm split in the average gate length between the two wafers, and the spreadof gate CD of the two wafers is about the same.This split in gate length enables us to explore and validate our assumption that LEFF variation is causing the across-wafersystematic variation. As shown in Fig. 6, the slower wafer (#1) and the faster wafer (#2) share a similar across-waferfunction for RO frequency, log(ILEAKN), and log(ILEAKP). Because the sensitivity of the RO frequency to LEFF increases asLEFF gets shorter, the wafer with smaller LEFF should have greater curvature in the across-wafer function. Thisphenomenon is indeed observed on Fig. 10a, where the across-wafer function of wafer #2 shows almost twice the rangeof that of wafer #1. While higher RO frequencies correspond to wider frequency range when comparing wafers due tonon-linear dependency on LEFF, this does not always apply to two patterns with different speeds, which again suggeststhe pattern-to-pattern difference is not likely to be caused by LEFF change, as discussed in section 5.2. The LEFF split isalso helpful in identifying the accuracy and effectiveness of the physical models used for SPICE simulation, which willbe discussed in the next section.Range of fitted across-wafer functionRange of Fitted Across-wafer function0.14- E0* xx1.051.1D(X wafer 1wafer 2-0.95-0.9-0.85Average Iog(ILEAKN) by layout1.15Fig. 10: (a) range f ,D,W,PXAW (c) range log(I LEAKP ) ,D,W,P D)vs. f , ,W,PAWg0.09-00.08GroupsXXttX0.041'ix0.08-Average frequency by layouto Uci:8E0.1-0.10o 95D60.ii-Doo0.060.12-0z 0.12-CsRange of fitted across-wafer function0.130.16Group

Hierarchical Modeling of Spatial Variability with a 45nm Example Kun Qian, Borivoje Nikoliü and Costas J. Spanos Dept. of EECS, University of California, 550 Cory Hall, Berkeley, CA USA 94720 ABSTRACT In previous publications we have proposed a hierarchical variability model and verified it with 90nm test data. This

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