Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, And SPARC

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureEach SPARC T5 processor provides sixteen cores, with each core able to switch between up to eightthreads (128 threads per processor) using a modified LRU (Least Recently Used) algorithm for threadchoice. In addition, each core provides two integer execution pipelines, so a single SPARC core iscapable of executing two threads at a time. Unlike the SPARC T3 processor, the SPARC T5 processorfetches one of eight threads for instruction propagation through stages of the pipeline to present to theselect stage by the fetch3 stage. Thread instructions are grouped into two-instruction decode groupsand proceed through the decode, rename, and pick stages before proceeding to the issue stage, afterwhich they are sent to one of four subsequent execution pipelines, depending upon the type ofinstruction to be performed.Up to this point, each instruction from any thread has proceeded through the pipeline independent ofthe type of instruction. Two instructions are issued for execution by the issue stage per cycle, unlikewith the SPARC T3 processor, which issued only one instruction per cycleFigure 3 provides a simplified high-level illustration of the thread model supported by a 16-coreSPARC T5 processor.Figure 3. A single 16-core SPARC T5 processor supports up to 128 threads, with up to two threads running in eachcore simultaneously.SPARC T5 Processor ArchitectureThe SPARC T5 processor extends Oracle’s multicore/multithreaded initiative with an elegant androbust architecture that delivers real performance to a wide range of applications. From OLTPtransactional workloads, to data warehousing, as well as single-thread sensitive batch operations. Figure4 provides a block-level diagram of the SPARC T5 processor.6

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureFigure 4. The SPARC T5 processor provides seven coherence links to connect to up to four other processors.The SPARC T5 processor is a single chip multiprocessor (CMP) and contains 16 physical processorcores. Each physical processor core has full hardware support for eight strands, two integer executionpipelines, one floating-point execution pipeline, and one memory pipeline.In addition to outstanding multithreaded performance, the SPARC T5 processor offers greatlyimproved single-thread performance. In particular, the SPARC T5 processor provides a robustout-of-order, dual-issue processor core that is heavily threaded among eight strands. It has a 16-stageinteger pipeline to achieve high operating frequencies, advanced branch prediction to mitigate theeffect of a deep pipeline, and dynamic allocation of processor resources to threads. This allows theSPARC T5 processor to achieve very high single-thread performance (about 30 percent higher than theSPARC T4 processor), while still scaling to very high levels of throughput.Each physical core has a 16-KB, 4-way associative instruction cache (32B lines), a 16 KB, 4-wayassociative data cache (32B lines), a 64-entry fully-associative instruction translation lookaside buffer(TLB), and a 128-entry fully associative data TLB that are shared by the eight strands. It also includes aprivate, 128-KB, 8-way inclusive write-back L2 cache with 32B lines. Each physical core also includescryptographic acceleration hardware, accessible via user-level instructions.The SPARC T5 processor has coherence link interfaces to allow communication between up to eightSPARC T5 chips in a system without requiring any external hub chip. There are seven coherence links,each with 12 lanes in each direction running at 153.6 Gb/sec. The SPARC T5 processor has sevencoherence link units (CLUs), four coherence units, and a cross bar (CLX) between coherence units andCLUs.7

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureThe SPARC T5 processor interfaces to external DDR3 DIMMs via an external buffer-on-board (BoB)chip using proprietary unidirectional high-speed links. There are four memory links on the SPARC T5processor. Each memory link is 12 lanes southbound and 12 lanes northbound and operates at 12.8Gb/sec. Each BoB chip has a DDR3 channel for a total of up to eight DDR3 channels per SPARC T5processor. Each DDR3 channel has two DIMMs providing up to 16 DDR3 DIMMs per SPARC T5processor.The SPARC T5 processor can support one-, two-, four-, and eight-socket implementations. A typicaltwo-socket implementation is shown in Figure 5. Dual-socket, as well quad-socket SPARC T5implementations interconnect the processors’ seven coherence links. No additional circuitry isrequired.Figure 5. A typical dual-socket SPARC T5 configuration.SPARC T5 Processor Cache ArchitectureThe SPARC T5 processor has a three-level cache architecture. Levels 1 and 2 are specific to each core,that is, these two levels of cache are not shared with other cores. Level 3 is shared across all cores of agiven processor. Cache sharing does not occur across another processor even though that processormay be in the same physical system. The SPARC T5 processor has Level 1 caches that consist ofseparate data and instruction caches. Both are 16 KB and are per core. A single Level 2 (L2) cache,again per core, is 128 KB. The Level 3 (L3) cache is shared across all sixteen cores of the SPARC T5processor and is 8 MB, has eight banks, and is 16-way set associative. Figure 6 illustrates therelationship between the L2 and Level 3 caches and shows them connected by a 8x9 crossbar:8

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureFigure 6. The relationship between the L2 and L3 caches.SPARC T5 Core ArchitectureThe SPARC T5 processor represents a fundamental redesign of the core within a SPARC multicorearchitecture and a continuation of the previous SPARC T4 processor. Now included within the coreare the following aspects that are more conventionally associated with superscalar designs: Out-of-Order (OoO) instruction execution Sophisticated branch prediction Prefetching of both instructions and data Much deeper pipelines (relative to previous versions of multicore processors from Sun/Oracle) Three levels of cache Support for a much larger memory management unit (MMU)page size (2 GB) Multiple instruction issueThere are many functional units, pipelines, and associated details that are present within the SPARC T5core but are beyond the scope of this paper. However, due to the significantly new characteristics andfeatures of the SPARC T5 core, this paper does attempt to touch upon the major exposed features orcharacteristics (that is, those that are visible to either programmers or users of SPARC T5–basedsystems).9

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureOne aspect by which the designers of the SPARC T5 architecture were able to achieve a physical spacesavings of chip real estate was to reuse many physical pieces of a given core for widely varyingfunctionality. For example, for each of the four major pipelines present within each core, the first 14stages of each pipeline are actually shared. This represents a major space utilization efficiency bymaking each of the first 14 stages identical. Thus, they can be used by one of two integer instructions, afloating-point graphics instruction, or a load-store instruction. In Figure 7, the first six blocks representthe 14 identical stages, which are specifically defined in Figure 8.Dynamic ThreadingThe SPARC T5 processor is dynamically threaded. While software can activate up to eight strands oneach core at a time, hardware dynamically and seamlessly allocates core resources such as instruction,data, and L2 caches and TLBs, as well as out-of-order execution resources such as the 128-entryreorder buffer in the core. These resources are allocated among the active strands. Software activatesstrands by sending an interrupt to a halted strand. Software deactivates strands by executing a HALTinstruction on each strand that is to be deactivated. No strand has special hardware characteristics. Allstrands have identical hardware capabilities.Since the core dynamically allocates resources among the active strands, there is no explicitsingle-thread mode or multithread mode for software to activate or deactivate. If software effectivelyhalts all strands except one on a core via critical thread optimization (described later in this document),the core devotes all its resources to the sole running strand. Thus, that strand will run as quickly aspossible. Similarly, if software declares six out of eight strands as noncritical, the two active strandsshare the core execution resources.The extent to which strands compete for core resources depends upon their execution characteristics.These characteristics include cache and TLB footprints, inter-instruction dependencies in theirexecution streams, branch prediction effectiveness, and others. Consider one process that has a smallcache footprint and a high correct branch prediction rate such that when running alone on a core, itachieves two instructions per cycle (the SPARC T5 processor’s peak rate of instruction execution).This is termed a high IPC process. If another process with similar characteristics is activated on adifferent strand on the same core, each of the strands will likely operate at approximately oneinstruction per cycle. In other words, the single-thread performance of each process has been cut inhalf. As a rule of thumb, activating N high-IPC strands will result in each strand executing at 1/N of itspeak rate, assuming each strand is capable of executing close to two instructions per cycle.Now consider a process that is largely memory-bound. Its native IPC will be small, possibly 0.2. If thisprocess runs on one strand on a core with another clone process running on a different strand, there isa good chance that both strands will suffer no noticeable performance loss, and the core throughputwill improve to 0.4 IPC. If a low-IPC process runs on one strand with a high-IPC process running onanother strand, it’s likely that the IPC of either strand will not be greatly perturbed. The high-IPCstrand might suffer a slight performance degradation (as long as the low-IPC strand does not cause asubstantial increase in cache or TLB miss rates for the high-IPC strand).10

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server ArchitectureThe guidelines above are only general rules-of-thumb. The extent to which one strand affects anotherstrand’s performance depends upon many factors. Processes that run fine on their own, but sufferfrom destructive cache or TLB interference when run with other strands, might suffer unacceptableperformance losses. Similarly, it is also possible for strands to cooperatively improve performancewhen run together. This might occur when the strands running on one core share code or data. In thiscase, one strand may prefetch instructions or data that other strands will use in the near future.The same discussion can apply between cores running in the chip. Since the L3 cache and memorycontrollers are shared between the cores, activity on one core can influence the performance of strandson another core.Figure 7 is a block-level diagram representing a single SPARC core on the SPARC T5 processor.Sixteen cores are supported per processor.Figure 7. Block-level diagram of a single core of the SPARC T5 processor.Components implemented in each core include the following: Trap logic unit (not shown). The trap logic unit (TLU) updates the machine state as well ashandling exceptions and interrupts. Instruction fetch unit. The instruction fetch function is responsible for selecting the thread,fetching instructions from instruction cache (icache) for the selected thread, and providing up tofour instructions to the select stage every cycle. On the SPARC T5 processor, it performs thefollowing major functions: Select the thread to be fetched. Fetch instructions from icache for the selected thread, and place them in the instruction buffersfor the select unit.11

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Predict direction and target of delayed control transfer instructions (DCTI) on the thread beingfetched. On icache miss, fetch data from the L2 cache (L2 ), pre-decode it, and store it in icache. Select unit. The primary responsibility of the select unit is to schedule a thread for execution on theSPARC T5 processor's pipeline for each cycle. For each cycle, up to one thread out of eight threadstotal can be selected for execution. A thread is in one of two states: Ready or Wait. Threads can be ina Wait state due to postsync conditions, mispredicted branches, lack of valid instructions, or otherinstruction-related wait conditions. For each cycle, the select unit selects one thread for executionfrom among the ready threads using a least-recently-used (LRU) algorithm for fairness. For theselected thread, up to two instructions are sent to the decode unit per cycle. Decode unit. The decode unit on the SPARC T5 processor is responsible for the following: Identifying illegal instructions Decoding integer and FP sources and sinks for up to two instructions per cycle as well as detectingsource/sink dependencies Generating flat mapping of integer and FP registers Decoding condition-code sources and destinations Generating micro-ops for complex instructions Generating instruction slot assignments Detecting DCTI (delayed control transfer instruction) couples Creating NOOPs when exceptions or annulling are detected Maintaining speculative copies of window registers and executing certain window registerinstructions Decoding up to two instructions every cycle Preparing the data and the addressing for the Logical Map Tables (LMTs), which are part of therename unit (RU) Rename unit. The rename unit is responsible for renaming the destinations of instructions andresolving destination-source dependencies between instructions within a thread as well as creatingage vector dependency based on issue-slot. Renaming takes three cycles: R1, R2, and R3. For eachcycle, the rename unit gets up to two instructions from the decode unit at the end of the D2 cycle.Each group of instructions is called a decode group. The rename unit does not break the decodegroup of instructions received from decode unit. Pick unit. The pick unit schedules up to three instructions per cycle out of a 40-entry pick queue(PQ). Up to three instructions (two instructions plus one store data acquisition op) are written intothe PQ during the second phase of the R3. The PQ is read during the first phase of the pick cycle.12

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Issue unit. The primary responsibility of the issue unit is to provide instruction sources and data tothe execution units. The SPARC T5 processor has six execution units corresponding to the threeissue slots, as shown in Figure 8.Figure 8. Relationship between issue slots and execution units. Floating point/graphics unit. A floating point/graphics unit (FGU) is provided within each coreand it is shared by all eight threads assigned to the core. Thirty-two floating-point register file entriesare provided per thread. A fused floating point Mul/Add instruction is implemented. In addition, theinteger Fused Mul/Add instruction from the SPARC64 VII instruction set has been added. This alsoperforms part of the cryptographic calculations based upon the algorithm being executed.A newly designed core for the SPARC T5 processor implements a 16-stage integer pipeline, a20-stage load-store pipeline, and a 27-stage floating-point graphics pipeline. All are present in each ofthe sixteen cores of a SPARC T5 processor (Figure 9).Figure 9. A 16-stage integer pipeline, a 20-stage load-store pipeline, and a 27-stage floating-point graphics pipelineare provided by each SPARC T5 processor core.13

Oracle's SPARC T5-2, SPARC T5-4, SPARC T5-8, and SPARC T5-1B Server Architecture Stream processing unit. Each core contains a stream processing unit (SPU) that providescryptographic processing. This functionality has been implemented within the core pipelines in theSPARC T5 processor and is accessible by 29 new user-level instructions. Load-store unit. The load-store unit (LSU) is responsible for processing all memory referenceinstructions and properly ordering all memory references. The LSU will receive load and storeinstructions out of order as they are picked by the pick unit. Loads might be issued out of order withrespect to other loads and stores might be issued out of order with the respect to other loads andstores. However, loads will not be issued ahead of previous stores. In addition to the memoryreferences required by the instruction set, the LSU also contains a hardware prefetcher, whichprefetches data into the L1 cache based upon detected access patterns. Memory management unit. The memory management unit (MMU) provides a hardware tablewalk (HWTW) and supports 8-KB, 64-KB, 4-MB, 256-MB, and 2-GB pages. Integer execution unit. The integer execution unit (EXU) is capable of executing up to twoinstructions per cycle. Single-cycle integer instructions are executed in either the EXU0 (slot0) orEXU1 (slot1) pipeline. Load and store address operations go to EXU0 (slot0). Branch instructionsare executed in EXU1 (slot1). Floating point, multicycle integer, and SPU instructions go throughthe EXU1 (slot1) pipeline. Store data operations go to EXU0 (slot2), but are not considered separateinstructions by the EXU since the store address operation must also occur for the same instruction.To illustrate how the dual integer pipelines function, Figure 10 depicts the dual EXUs with theworking register files (WRFs), floating-point register files (FRFs), and integer register files (IRFs)shown along with the various data paths.Figure 10. Threads are interleaved between the two integer pipelines and are restricted to EXU0 or EXU1 according to

Table 2 provides a comparison between the SPARC T5, SPARC T4, SPARC T3 processors. The SPARC T5 leverages many of the elements from the SPARC T4 processor. TABLE 2. SPARC T5, SPARC T4, AND SPARC T3 PROCESSOR FEATURE COMPARISON FEATURE SPARC T5 PROCESSOR SPARC T4 PROCESSOR SPARC T3 PROCESS