Introduction To SMIPS

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6.S078 - Computer Architecture:A Constructive ApproachIntroduction to SMIPSLi-Shiuan PehComputer Science & Artificial Intelligence Lab.Massachusetts Institute of TechnologyFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-1Stored Program Concept! Instructions are bits (i.e., as numbers)! Programs are stored in memory!to be read or written just like data Treating Instructions inthe same way as Data memory for data, programs, compilers, editors, etc.! Fetch & Execute Cycle!!!Instructions are fetched and put into a special registerBits in the register "control" the subsequent actionsFetch the next instruction and continue1

Multiple Levels ofRepresentation temp v[k];High LevelLanguageProgram v[k] v[k 1]; v[k 1] temp; Compilerlwlwsw 16,sw 15,AssemblyLanguageProgram Assembler Machine LanguageProgram 0000 1010 1100 010110011111011010001100010110100000 15, 0( 2) 16, 4( 2)0( 2)4( 01011100000010101000011010011111 MachineInterpretation Control SignalSpecification ALUOP[0:3] InstReg[9:11] & MASK High and low signals on control linesInstruction SetArchitecture (ISA)! Programmer’s view of thecomputer!February 22, 2012Instructions, operandshttp://csg.csail.mit.edu/6.S078L5-42

ExampleISAs!!!!!!Intel 80x86ARMIBM/Motorola PowerPCHP PA-RISCOracle/Sun Sparc6.004’s BetaWhy MIPS?It’s simple!Most taught ISA3

MIPS I InstructionSet Architecture Registers! Instruction Categories r0 - r31Load/StoreComputationalJump and BranchFloating Point" coprocessorMemory ManagementSpecial!!!!!! PC HI LO 3 Instruction Formats: all 32 bits wide OP rs rt OP rs rt OP rd sa funct immediate jump target SMIPS: a subset of the full MIPS32 ISASMIPS Registers: FastLocations for Data! 32 32-bit registers: 0, 1, , 31!!!!operands for integer arithmeticaddress calculationstemporary locationsspecial-purpose functions defined by convention! 1 32-bit Program Counter (PC)! 2 32-bit registers HI & LO:!used for multiply & divide4

MIPS arithmetic! All instructions have 3 operands! Operand order is fixed (destination first)Example: C code: MIPS code:A B Cadd s0, s1, s2 C code:A B C D;E F - A; MIPS code:add t0, s1, s2add s0, t0, s3sub s4, s5, s0MIPS Load-StoreArchitecture! Every operand must be in a register (a fewexceptions)! Variables have to be loaded in registers.! Results have to be stored in memory. a b c d a b load b in register Rx load c in register Ry Rz Rx Ry store Rz in a Rt Rz Rx store Rt in d more variables than registers, so need explicit load and stores.5

Memory Organization! Viewed as a large, single-dimension array, with anaddress.! A memory address is an index into the array! "Byte addressing" means that the index points to abyte of memory. 0 1 2 3 4 5 6 . 8 bits of data 8 bits of data 8 bits of data 8 bits of data 8 bits of data Q: How to specify a memory location? 8 bits of data 8 bits of dataLoad & StoreInstructions! Base Offset addressing mode: offset(base register)e.g., 32( s3)! Example:!!C code: A[8] h A[8];" A: an array of 100 words" the base address of the array A is in s3 base register: s3 offset: 32MIPS code:lw t0, 32( s3)add t0, s2, t0sw t0, 32( s3)! Store word has destination last6

Example: Compiling using aVariable Array Index! C code:g h A[i] s3: base register for Ag, h, i: s1, s2, s4! MIPS code:add t1, s4, s4add t1, t1, t1# t1 2 * i# t1 4 * iadd t1, t1, s3lw t0, 0( t1)# t1 address of A[i]# t0 A[i]add s1, s2, t0# g h A[i]LUI instruction! Load upper immediate! LUI rt, zero-ext-imm! Shifts 16-bit immediate into high-order 16 bits, with 16 zeros in loworder bits - rt! How is LUI useful?February 22, 2012http://csg.csail.mit.edu/6.S078L5-147

Control: bne & beq! Decision making instructions!!alter the control flow,i.e., change the "next" instruction to be executed! MIPS conditional branch instructions:bne t0, t1, Labelbeq t0, t1, Label! Example: if (i j) h i j;bne s0, s1, Labeladd s3, s0, s1Label:.SLTinstructions Set if less than E.g. SLTI rt, rs, signed-immIf (rs imm), rt 1, else rt 0What is SLT used for?8

Jumps (J, JAL, JR, JALR)! MIPS unconditional branch instructions:j label Example:if (i! j)h i j;elseh i-j;beq s4, s5, Lab1add s3, s4, s5j Lab2Lab1:sub s3, s4, s5Lab2:. PC - PC 4 4*SEXT(literal)Jumps! JAL target (jump and link)!!!February 22, 2012PC 8 - R31Why PC 8?How is JAL useful?http://csg.csail.mit.edu/6.S078L5-189

Jumps! JR rs!Jumps to address in register! PC - Reg[rs]! JR vs. J or JAL?http://csg.csail.mit.edu/6.S078February 22, 2012L5-19Jumps! JALR – Jump and link register! JALR rd, rs!!Jumps to rsWrites link address into rd! Why JALR vs. JAL?February 22, 2012http://csg.csail.mit.edu/6.S078L5-2010

MIPS: Stack detective!! Call procedure: jump and link (jal)! Return from procedure: jump register(jr)! Argument values: a0 - a3! Return value: v0! Template:!!!!Call setupPrologueEpilogueReturn cleanupFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-21February 22, 2012http://csg.csail.mit.edu/6.S078L5-2211

February 22, 2012http://csg.csail.mit.edu/6.S078L5-23Procedure call setup1. Place current parameters into stack (spacealready allocated by caller of thisprocedure)2. Save any TEMPORARY registers that needto be preserved across the procedure call3. Place first 4 parameters to procedure into a0- a34. Place remainder of parameters toprocedure into allocated space within thestack frameFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-2412

Procedure call setupFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-25Prologue1. allocate space for stack frame2. save return address in stack frame3. copy needed parameters from stack frameinto registers4. save any needed SAVED registers intocurrent stack frameFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-2613

Time to actually callfunction! #February 22, 2012http://csg.csail.mit.edu/6.S078L5-27Return cleanup1. copy needed return values and parametersfrom v0-v1, a0-a3, or stack frame tocorrect places2. restore any temporary registers from stackframe (saved in call setup)February 22, 2012http://csg.csail.mit.edu/6.S078L5-2814

Epilogue1. restore (copy) return address from stack frame into ra2. restore from stack frame any saved registers (saved inprologue)3. de-allocate stack frame (move sp so the space for theprocedure's frame is gone)February 22, 2012http://csg.csail.mit.edu/6.S078L5-29MIPS coprocessor 0instructions:mfc0, mtc0! interrupts, exceptions, resets! Beta vs MIPSFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-3015

Exception Registers! Not part of the register file.!Cause" Records the cause of the exception!EPC (Exception PC)" Records the PC where the exception occurred! EPC and Cause: part of Coprocessor 0! Move from Coprocessor 0!!mfc0 t0, EPCMoves the contents of EPC into t0Exceptions Save cause and exception PC Jump to exception handler (0x0000 1100) Exception handler:–– –––Saves registers on stackReads the Cause registermfc0 Cause, t0Handles the exceptionRestores registersReturns to program mfc0 EPC, k0 jr k016

Exception CausesFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-33Cause registerFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-3417

Reset!!!!!mtc0 zero, 9 #init countermtc0 zero, 11 #timer interrupt::J kernel initFebruary 22, 2012http://csg.csail.mit.edu/6.S078L5-3518

0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 ALUOP[0:3] InstReg[9:11] & MASK High and low signal

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