MATLAB And Simulink For Embedded System Design

Pieter J. 4595596597598599600/* Logic: ' S3 /either' */rtb either power window con B.passenger control b power window con B.passenger control a;/* Logic: ' S13 /allow action' incorporates:* Inport: ' Root /driver up'* Logic: ' S13 /overrule'*/rtb temp34 power window con U.driver up&& (!(rtb either));Senior Research ScientistThe MathWorks, Inc. 2007 The MathWorks, Inc.MATLAB and Simulink forEmbedded System Design

Introduction Increasing complexity of embedded systemsComplexity– Intricacy– SizeRaising the Level of AbstractionCompilers to handle the complexity because ofsize2

Agenda The System Design ChallengeSoftware Design FlowHardware Design FlowSummary3

The System Design Challenge We design, simulate, andvalidate system models andalgorithms in MATLAB and/or Simulink How can we implement andverify designs on DSPs andGPPs? How can we implement andverify designs on FPGAs andASICs?MATLAB and Simulink Algorithm and System DesignHDLCMCUDSPFPGAASIC4

Integrated Design Flow forEmbedded Software and Hardware Verify hardware and softwareimplementations against thesystem and algorithm modelsHDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveGenerateAutomatically generate C andHDLReal-Time WorkshopEmbedded Coder,Targets, LinksGenerate MATLAB and Simulink Algorithm and System DesignVerifyDesign, simulate, and validatesystem models and algorithms inMATLAB and SimulinkVerify DSPFPGAASIC5

Agenda The System Design ChallengeSoftware Design FlowHardware Design FlowSummary6

Integrated Design Flow forEmbedded Software Implementation–––HDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveGenerate–Real-Time WorkshopEmbedded Coder,Targets, LinksGenerate–Floating- and fixed-point codeIntegration with downstreamIDEs and toolsLinks to verificationDevice driversOptimization optionsMATLAB and Simulink Algorithm and System DesignVerifyImplementation withautomatic C code generationVerify DSPFPGAASIC7

Representative Application – Video Video system design and implementation–Encapsulates challenges: complexity,convergence, time-to-market–Sophisticated algorithms–Floating- and fixed-point issues–DSP or FPGA/ASIC implementationsEmbedded SoftwareCase Study:Video Edge Detectionon a DSPDesign flows and steps shown directlyapplicable to other signal processingapplicationsLiveMATLABDemo8

Example: Video Edge Detection Floating point video edge detection system based onPrewitt algorithmCompositing original image with detected edgesUtilizes blocks from Video and Image Processing Blockset9

Converting to Fixed-Point Polymorphic blocks capable of floating- and fixed-pointoperation8-bit input datatype – blocks inherit fixed-point dataSimulink Accelerator provides fast fixed-point simulation8-bit fixed-point input10

Automatic Code Generationfor Implementation on GPPs and DSPsFixed-point modelCode generationoptionsand preferencesSelect target or flavorof generated code11

Code Generation ReportHTML reportLinks to code filesfrom HTML reportLinks to Simulinkmodel fromgenerated codeReadable,commented code12

Video Edge DetectionEmbedded Software System on TI 6000TMTCP/IP Blocks13

Target Code Generation OptionsHigh-Speed RTDXInline Signal ProcessingBlockset functionsIncorporateDSP/BIOS14

Code Execution on Target and Profiling Build and execute– Auto-generate C and ASM–Integrate RTOS andscheduler–Create full CCS project–Invoke compiler, linker, anddownload code–Run on targetProfile code performanceSystem profilingincludes entire DSPapplication codeSubsystem profiling15

Code Optimization Options Utilize target-specific blocks––––– C-callable assembler librariesSimulate bit-true in SimulinkGenerate calls to hand-optimizedassembler librariesHighly optimized implementationof core functionalityC62x and C64x fixed-point DSPsManual optimization by user16

Design Verification and Visualization:MATLAB as software test benchVisualize and debug embeddedsoftware with MATLABInput videoMATLAB script(test bench)Capturedvideo17

Design Verification and Visualization:Simulink as software test benchProcessor and hardware-in-theloop testing, simulation,visualization, and verification ofembedded software with SimulinkSimulink test benchDevice or designunder test (DUT)Simulink system designembedded on DSP18

Review: Integrated Design Flow forEmbedded Software Use code profiles to identifyand optimize bottlenecks Verify code with Links toIDEs and processorsHDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveGenerateQuickly create completeworking code baseReal-Time WorkshopEmbedded Coder,Targets, LinksGenerate MATLAB and Simulink Algorithm and System DesignVerifyDrive system developmentwith an executablespecificationVerify DSPFPGAASIC19

Agenda The System Design ChallengeSoftware Design FlowHardware Design FlowSummary20

Integrated Design Flow for Hardware(FPGA and ASIC) Implementation––HDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveGenerate–Real-Time WorkshopEmbedded Coder,Targets, LinksGenerate–HDL code generation(VHDL and Verilog)test bench generationLinks to verificationIntegration withsynthesis toolsMATLAB and Simulink Algorithm and System DesignVerifyDesign elaborationVerify DSPFPGAASIC21

What We Will Show In This Case Study Behavioral modeling and simulationFixed-point modeling and simulationDesign elaborationHDL generationCo-simulation using Link for ModelSimHardware Case Study:Video Edge Detectionon an FPGALiveMATLABDemo22

Executable Specification23

Design ElaborationAutomatically generateVerilog or VHDL code fromelaborated models24

HDL Code Generation Using GUISelect subsystem, targetlanguage, directorySelect output optionsCheck model for errorsGenerate HDL Code25

More Code Generation OptionsSelect reset andclock optionsSet language-specificoptions: input/outputdatatypes, timescaledirectives, 26

Automatically Generate Test BenchSelf-checking HDL test bench comparesSimulink results to HDL results27

Co-simulate Generated HDLLink for ModelSimHDL code executing onModelSim simulator28

Review:Integrated Design Flow for Hardware Verify code with Links toRTL simulators andsynthesis toolsHDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveGenerateQuickly create completeworking HDL code baseand test benchesReal-Time WorkshopEmbedded Coder,Targets, LinksGenerate MATLAB and Simulink Algorithm and System DesignVerifyDrive system developmentwith an executablespecificationVerify DSPFPGAASIC29

Agenda The System Design ChallengeSoftware Design FlowHardware Design FlowSummary30

SummaryHDLCMCUSimulink HDL CoderLink for ModelSimLink for Cadence IncisiveVerifyReal-Time WorkshopEmbedded Coder,Targets, LinksGenerateDesign and verify softwareand hardware from MATLABand SimulinkMATLAB and Simulink Algorithm and System DesignGenerate Accelerate development usingModel-Based Design– Generate Real-Time Workshop Simulink HDL Coder– Verify Link for CadenceIncisiveVerify DSPFPGAASIC31

MATLAB and Simulink Automatically generate C and HDL Verify hardware and software implementations against the system and algorithm models C MATLAB and Simulink Algorithm and System Design Real-Time Workshop Embedded Coder, Targets, Links V e r i f y Simulink HDL Coder Link for ModelSim Li