HCMOS Design Considerations (Rev. A) - TI

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HCMOS Design ConsiderationsSCLA007ASeptember 20021

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections,modifications, enhancements, improvements, and other changes to its products and servicesat any time and to discontinue any product or service without notice. Customers should obtainthe latest relevant information before placing orders and should verify that such information iscurrent and complete. All products are sold subject to TI’s terms and conditions of sale suppliedat the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time ofsale in accordance with TI’s standard warranty. Testing and other quality control techniques areused to the extent TI deems necessary to support this warranty. Except where mandated bygovernment requirements, testing of all parameters of each product is not necessarilyperformed.TI assumes no liability for applications assistance or customer product design. Customers areresponsible for their products and applications using TI components. To minimize the risksassociated with customer products and applications, customers should provide adequatedesign and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under anyTI patent right, copyright, mask work right, or other TI intellectual property right relating to anycombination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third–party products or services does not constitute a license from TIto use such products or services or a warranty or endorsement thereof. Use of such informationmay require a license from a third party under the patents or other intellectual property of the thirdparty, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproductionis without alteration and is accompanied by all associated warranties, conditions, limitations, andnotices. Reproduction of this information with alteration is an unfair and deceptive businesspractice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters statedby TI for that product or service voids all express and any implied warranties for the associatedTI product or service and is an unfair and deceptive business practice. TI is not responsible orliable for any such statements.Mailing Address:Texas InstrumentsPost Office Box 655303Dallas, Texas 75265Copyright 2002, Texas Instruments Incorporated2

ContentsTitlePageIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1HCMOS Designer’s Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1CMOS Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1High-Speed CMOS Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Latch-Up Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Fan-Out and Capacitance Loading Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13HCT Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Power-Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Decoupling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Connecting Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Powering-Up/Down Sequence for High-Speed CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1414151515High-Speed CMOS Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16General Interfacing Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Driving-Gate Output Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input-Gate Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CMOS-to-Standard-TTL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Standard TTL-to-CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CMOS-to-LS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LS-to-CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CMOS-to-ALS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ALS-to-CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CMOS-to-AS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .AS-to-CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CMOS-to-NMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .NMOS-to-CMOS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Using HCT Devices to Interface with CMOS From TTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161717181819212122222323242424Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Crystal-Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25252525Drivers for LEDs and Relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Driving LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Driving Relays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27iii

Contents (continued)TitlePageSN54/74HC Interchangeability Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28TTL: Transistor-Transistor Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284000 Series: Metal-Gate CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Interchangeability Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Other TTL Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4000 Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28282829Electrostatic Discharge (ESD)30.Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30What is ESD and How Does It Occur? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Latent Defects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .What Voltage Levels of ESD Are Possible? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .How to Avoid ESD Damage to ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ESD Coordinator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Audits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TI ESD Handling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30303030313131323232Moisture Sensitivity of Plastic Surface-Mount Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34iv

List of IllustrationsFigureTitlePage1Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Transmission Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Exclusive-OR/NOR Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Inverting 3-State Output Buffer With Active-Low Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Transparent Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Negative-Edge-Triggered D-Type Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Simplification of Diagrams by Combining Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Power Consumed vs Frequency for High-Speed CMOS Compared to LS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610Typical Distribution of Switching Frequencies for Gates Within a SystemWith Maximum Clock Frequency, fs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611Contribution to Total Power by Gates Running at Frequencies From 0 to fs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612High-Speed CMOS and LS Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713ESD Input Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814ESD Output Protection Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915Parasitic Bipolar Transistors in CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916Schematic of Parasitic SCR With P-Gate and N-Gate Electrodes Connected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017Unique Latch-Up Suppression Utilizes Guard Rings to Virtually Eliminate Latch-Up . . . . . . . . . . . . . . . . . . . . . . 1018Worst-Case Output and Input Circuits of High-Speed CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1119Gate Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1420Test Circuit for Decoupling Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1421VCC Transients vs Decoupling Capacitor Distance From DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1522Voltage Transfer Characteristic of a Typical Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1623Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1724Output Model of a Driving Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1825SN54/74HC Input Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1826SN54/74HC-to-TTL Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1927TTL-to-SN54/74HC Interface With a Pullup Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1928SN54/74HC-to-LS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2129LS-to-SN54/74HC Interface With a Pullup Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2130SN54/74HC-to-ALS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2231Interface With a Pullup Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2232SN54/74HC-to-AS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2333AS-to-SN54/74HC Interface With a Pullup Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2334Simple RC Oscillator Using Two HC04 Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25v

List of Illustrations (continued)FigureTitlePage35Oscillator Circuit Using a Crystal to Set the Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2536VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2637HC04 Driving an LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2738SN54/74HC04 Gates Connected in Parallel to Drive a Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2739ESD-Protected Workstation (Side View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32TablesTableviTitlePage1Performance Comparison of High-Speed CMOS With Several Other Logic Families . . . . . . . . . . . . . . . . . . . . . . . 52Typical Fan-Out of High-Speed CMOS Devices andPropagation Delay Per pF at Various Values of VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Worst-Case Values of Primary Interfacing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Highlights of Interchangeability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

IntroductionHCMOS data sheets specify, under recommended operating conditions, input tt 1000 ns, (10%–90%) for VCC 2 V. Ifcertain devices are used in the threshold region (from VILmax 0.5 V to VIHmin 1.5 V), there is a potential to go into thewrong state from induced grounding, causing double clocking. Operating with the inputs at tt 1000 ns and VCC 2 V doesnot damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggleoperating modes.Devices susceptible to the above condition are: HC112, HC161, HC163, HC164, HC165, HC166, HC191, HC193, HC393,HC590A, and HC4040.HCMOS Designer’s InformationCMOS CircuitryThe elementary CMOS building blocks are the inverter and the transmission gate. Each uses a complementary pair of oneN-channel and one P-channel enhancement-type field-effect transistor. Figures 1 and 2 show these together with various logicsymbols1 used to represent them.VCCP Channel11N ChannelFigure 1. InvertersNNNVCCTGX1P11PPFigure 2. Transmission Gates1 The various logic symbols are equivalent. The distinctive-shape form of the inverter and gate symbols and the “TG” form of the transmissiongate typically are used in the device logic diagrams. The logic inversion symbol ( ) is shown at the input or the output, whichever maintainslogical consistency with the driving output or the driven input. This technique is used to indicate the true/complement levels of the signal as itprogresses through the circuit. For example, refer to Figure 7 in this section. The rectangular forms of the inverter and gate symbols and theindicates apolarity indicator ( ) replacing the inversion symbol usually are used in this book only in the device logic symbols. Thehigh-current output.1

Logic gates are created by adding transistors in parallel or in series to the transistors making up the elementary inverter. Thus,the simplest gates are inverting (see Figure 3). An odd number of additional inverters is sometimes added to the outputs of gatesto make them noninverting. Basic CMOS gates usually have no more than three inputs. Arrays of gates are used when morethan three signals are ANDed or ORed.VCCAYBYAYB 1&AAAYBYBBPositive Logic: Y AB or A BVCCAAYBBYA 1&AAYBYBPositive Logic: Y A B or A BFigure 3. Gates2YB

The exclusive-OR or exclusive-NOR gate is implemented most easily using two inverters and two transmission gates as shownin Figure 4. In complex chains of gates, the inverters can be made unnecessary by complementary signals that arealready available.ABTG 1AYAYYBTGBPositive Logic: Y A B A B or A BABTG 1AYAYYBTGBPositive Logic: Y A B AB or A BFigure 4. Exclusive-OR/NOR GatesThe 3-state output buffer has logic elements in the gate connections to each of the transistors in the final inverter so that bothcan be turned off under the control of an enable function. Figure 5 illustrates an inverting output buffer.VCCOEOEYOEENYFigure 5. Inverting 3-State Output Buffer With Active-Low Enable3

The transparent latch typically is implemented as shown in Figure 6. This is the simplest form. Logic diagrams show thatadditional inverters can be added as buffers or to optimize timing. The true and complementary outputs (Q and Q) may be takenoff at other points. Outputs brought out to terminals always are buffered to minimize any feedback effects. The exception tothis is the HCU device, which has unbuffered outputs.CDQTGCCCTGCD1DQCC1QQCCFigure 6. Transparent LatchesPutting two transparent latches in series produces an edge-triggered D-type flip-flop. Inverters can be converted to 2-inputgates to provide asynchronous set and reset functions. Figure 7 illustrates a negative-edge-triggered circuit. Exchanging theconnections of C and C produces a positive-edge-triggered ure 7. Negative-Edge-Triggered D-Type Flip-Flops4Q

Detailed logic diagrams for flip-flops are given in the data sheets, when useful, to illustrate special features, such assynchronous clearing, J/K inputs, and toggle enabling.In general, the logic diagrams have been simplified. They indicate the logic implementation, but should not be used to predictdynamic performance. Inverters existing in series can be combined or eliminated in the diagrams, as shown in Figure 8. orFigure 8. Simplification of Diagrams by Combining InvertersHigh-Speed CMOS CharacteristicsTable 1 compares the main characteristics of the high-speed CMOS family with those of standard TTL, LS, S, ALS, AS, andmetal-gate CMOS.Table 1. Performance Comparison of High-Speed CMOS With Several Other Logic FamiliesTECHNOLOGY†Device ANCEDSCHOTTKYTTL4000SN74SN74LSSN74ALSSN74ASPower dissipation per gate 10218.5Propagation delay time (ns) (CL 15 pF)83.7105101041.5Maximum clock frequency (MHz)(CL 15 pF)4013012354070200Standard outputs481.6168820High-current outputs681.6482424/4848/64Standard outputs1020440202050High-current outputs152041206060/120120/160 0.001 0.001–0.001–1.6–0.4–0.1–0.5At 100 kHzMinimum output drive (mA) (VO 0.4 V)Fan-out (LS loads)Maximum input current, IIL (mA)(VI 0.4 V)† Family characteristics at 25 C, VCC 5 V; all values typical unless otherwise noted. This table is provided for broad comparisons only.Parameters for specific devices within a family may vary. For detailed comparisons, please consult the appropriate data book.The major advantages of high-speed CMOS can be summarized as follows: The high-speed CMOS family can operate at speeds comparable to LS. The high-speed CMOS family has acparameters ensured at a supply voltage of 2 V, 4.5 V, and 6 V over the full operating temperature range into a 50-pFload (also, 150 pF for high-current outputs). Note that at the higher operating frequencies, the power consumptionalso is comparable to LS (see Figure 9).Figure 9 also shows that the high-speed CMOS family covers a wide range of applications: low-power drain forlow-speed systems and a slightly higher drain for higher-speed systems.5

PowerLSHCFrequencyFigure 9. Power Consumed vs Frequency for High-Speed CMOS Compared to LS Minimum system power. Only the gates that are switching contribute to system power consumption. This reducesthe size of the power supply required, resulting in lower system cost and improved reliability through lowerheat dissipation.No. of Gates SwitchingAs mentioned previously, the power consumption for an individual gate at the maximum speed is comparable to LS.However, in typical systems, only a fraction of the gates are switching at the clock frequency; therefore, significantpower savings can be realized. On a system level where the individual gate switching frequencies are distributedbetween zero and the system clock frequency (see Figure 10), the power saved with high-speed CMOS can be quitesignificant, as shown in Figure 11. The total system power is the area under each curve. The graph in Figure 11 isobtained by multiplying the individual gate characteristics (see Figure 9) by the frequency distribution in Figure 10.fsFrequencyContribution toTotal System PowerFigure 10. Typical Distribution of Switching Frequencies for Gates Within a SystemWith Maximum Clock Frequency, ÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇÇLS SystemPower SavedHC SystemFrequencyfsFigure 11. Contribution to Total Power by Gates Running at Frequencies From 0 to fs6

High-speed CMOS is ideal for battery-operated systems or systems requiring battery backup because there isvirtually no static power dissipation (see Figure 9).Improved noise immunity over bipolar devices is due to the rail-to-rail (VCC to ground) output voltage swings.Figure 12 illustrates the noise immunity provided by the high-speed CMOS family as it compares to the LS family.This noise immunity makes it ideal for high-noise environments. Minimum and maximum output voltages areensured at 4 mA (6 mA for high-current devices). If the output currents exceed these limits, the noise immunity isimpaired. HCT devices have input noise margins similar to LS because their inputs are TTL-voltage compatible.The outputs of HCT are the same as standard HC outputs.VOH VCC – 0.1 VI/O Voltage6VNH(HC) 0.29 VCC5VIH 0.7 VCC4HCVOH 2.7 VÉÉÉÉÉÉÉÉ3VNH(LS) 0.14 VCCVIH 2 V2VIL 0.8 V1LSVNL(LS) 0.08 VCCVOL 0.4 V03VNL(HC) 0.19 VCCLSHC2ÉÉÉÉÉÉÉÉVIL 0.2 VCC45LS6VOL 0.1 VVCC 5 V 10%Power-Supply VoltageFigure 12. High-Speed CMOS and LS Noise Margins High-speed CMOS devices can drive up to 10 LS loads (15 LS loads for high-current outputs) while maintaininggood noise immunity.High-speed CMOS devices are specified for operation over an extended temperature range:SN54HC/HCT–55 C to 125 C (military)SN74HC/HCT–40 C to 85 C(industrial)All specified ac and dc characteristics are ensured over this range with the exception of power dissipation capacitance (Cpd),which is specified as a typical value at 25 C.7

Protection CircuitryElectrostatic discharge (ESD) and latch-up are two traditional causes of CMOS device failure. To protect HCMOS devicesfrom ESD and latch-up, additional circuitry has been implemented on the inputs and outputs.ESD ProtectionESD occurs when a buildup of static charges on one surface arcs through a dielectric to another surface that has the oppositecharge. If this discharge current flows through an integrated circuit, the high currents can damage delicate devices on the chip.The protection circuits designed by Texas

High-Speed CMOS Characteristics Table 1 compares the main characteristics of the high-speed CMOS family with those of standard TTL, LS, S, ALS, AS, and metal-gate CMOS. Table 1. Performance Comparison of High-Speed CMOS With Several Other Logic Families TECHNOLOGY† SILICON-GATE CMOS AHC METAL-GATE

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