Electronic Packaging Technologies - Carleton University
Electronic PackagingTechnologiesSergio Lopez-Buedo, Eduardo BoemoUniversidad Autonoma de Madride-mail: sergio.lopez-buedo@uam.esElectronic Packaging Technologies1Introduction to Electronic Packaging Electronic Packaging is a multi-disciplinary subject– Mechanical, Electrical and Industrial Engineering, Chemistry,Physics and even Marketing Electronic Packaging: Housing and interconnectionof integrated circuits to form electronic systems Electronic Packaging must provide–––––Circuit support and protectionHeat dissipationSignal distributionManufacturability and serviceabilityPower distributionElectronic Packaging Technologies2
Issues in Electronic PackagingElectricalanalysis andtestingChemistry,Physics, Mat.Eng.Manufacturingand IndustrialEng.Mechanicalanalysis andtestingReliability,performance, cost,marketneed/timing,manufacturability,yields otherThermalanalysis andtestingMarketanalysisElectronic Packaging Technologies3Hierarchy of Interconnection Levels Level 0– Level 1– Connections between PCBs,including backplanes ormotherboardsLevel 4– PCB, from component to componentor to external connectorLevel 3– Connections from the chip to itspackageLevel 2– Gate-to-gate interconnections on thesilicon dieConnections betweensubassemblies, for example a rackLevel 5–Connections between physicallyseparate systems, using forexample an Ethernet LANElectronic Packaging Technologies4
Blue Gene: Example of Connection Hierarchy5Electronic Packaging TechnologiesThe Three Breakthroughs inChip Packaging TechnologynDeVOLUME1960ysitThru Hole DIP Pin GridSurface Mount QFP TSOP SOJ BGA19802000Chip Scale CSP Wafer Level Stacked DieYEARElectronic Packaging Technologies6
Through (Thru) Hole MountingSinclair ZX48 motherboard(Manufactured 1984)Electronic Packaging Technologies7Through-Hole Benefits and Drawbacks The pins of the components go throughthe previously drilled PCB holesBenefits– Easy to solder, either automatically(wave) or by hand– Easy to desolder and test– Implement interconnections betweenupper and lower layers (vias) in nonplated hole technologies Drawbacks– Signals must necessarily go through allPCB layers– Low density due to minimum pindiameter and only one-sided mountingElectronic Packaging Technologies8
Surface-Mount Technology (SMD)USB Flash drive (Manufactured 2004)Electronic Packaging Technologies9SMD Benefits and Drawbacks The pins of the devices are mounted directlyonto the surface of the PCBBenefits– Much higher density: pins can be thinner, devicescan be mounted on both sides of the PCB,components do not block signals in inner layers– Higher degree in the automation of the mountingprocess– Less parasitic inductance and capacitance– Reduced costs (½ to ¼) and size (¼ to one tenth) Drawbacks– Poor manual solderability and reparability– Reliability issues due to thermal/mechanical stressduring soldering and operation (different thermalexpansion coefficients)– Classic verification procedures no longer validElectronic Packaging Technologies10
Chip Scale Packages (CSP) Chip Scale Package, or CSP, based on IPC/JEDECJ-STD-012 definition, is a single-die, direct surfacemountable package with an area of no more than 1.2times the original die areaElectronic Packaging Technologies11CSP Benefits and Drawbacks CSP is not a new mounting technology, is an evolution of SMDThe passive components surrounding the chips must also beminiaturized (resistors, decoupling capacitors)Benefits– CSP is the only way to achieve pervasive and ubiquitous computing– Further improvement in high-speed performance Drawbacks– Difficulty of PCB fabrication and mounting due to minute pin pitches(0.5 mm)– Long-term reliability not studied– Not serviceableElectronic Packaging Technologies12
Three Packaging Technologies: SummarySurface MountThrough HoleCSP / WLPCSP/WLPTSOP! 25 mil pitch! Limited by perimeter leads! Area array 0.8 mm to 0.5 mm! Limited by substrate wiringDIP! 100 mil pitch! Limited by through hole spacingElectronic Packaging Technologies13First Step of Packaging: The Silicon Wafer The problem: How do I knowthat the chip is going to workbefore packaging it?Solution: Test it. But this is noteasy to achieve ––––Probing pads 150 µm awayArea array padsPowering the chipRemoving the heat itgenerates– Testing it in a reasonable time Only a limited testing (if any) isusually performed, full testing isdone after packagingElectronic Packaging Technologies14
A Typical Low-Density SMD Processfrom Silicon Wafer to PackageElectronic Packaging Technologies15Wafer Preparation and DicingWafers are mounted on a laminating tapethat adheres to the back of the wafer. Itholds the wafer throughout the dicing andthe die attaching process.The die-sawing machine using a diamond saw bladesaws the wafer into the individual die/pellet on theadhesive backing tape. Deionized water and CO2bubbles are dispensed on the wafer to remove silicondust/debris besides lubricating and cooling down thebladeElectronic Packaging Technologies16
Die Attach and Wire BondingThe die attach machine will pick up the die anddeposit it on the frame. It may utilize the wafermapping method to pick up only good die. Formost processes, die attach materials like gold orlead-tin based solder wires or silver epoxy pastepotting on the frame are required prior to diebonding process.Either Au or Al wires are used depending onapplication. Bonded one at a time, the wire isfed through a ceramic capillary. With a goodcombination of temperature and ultrasonicenergy, a good metalized wire bond is formed.Electronic Packaging Technologies17Moulding and Solder PlatingThe moulding process aims to encapsulatethe whole wire bonded die against exposureto contamination and other physicaldamages. The lead frames that hold thedies are placed in individual cavities whichare filled with liquid resin.This step provides a layer of TinLead solder on the lead frame formaking easier the PCB assemblyprocess. Lead free finishing withTin Bismuth plating or Tin Copperdipping can also be used.Electronic Packaging Technologies18
Marking and Lead Trim/FormMarking is the coding process that writescustomer's corporate and productidentification code on a packaged device.It commonly uses a laser-based machineThe final process is to trim awaythe leads of the packaged devicefrom the frame strip. The leadsare cut and formed mechanicallyto the specified shapeElectronic Packaging Technologies19Chip Attachment to thePackage Substrate The die attachment compound should provide– Electrical grounding– Thermal dissipation There are three alternatives– Soft Solder Die Attach: This process uses a solder material to bondthe die to the lead frame. The solder is introduced as a wirepreform and melted onto the hot lead frame surface as a liquidsolder dot.– Epoxy Die Attach: Epoxy die attach is the most commonly usedprocess. Usually silver-loaded polymers are used, but the termgenerally encompasses the use of other adhesives, such aspolyimide- or silicone-based materials.– Metal-filled glasses: Less used because the high temperaturesneeded, but have been used in ceramic packages Points to pay attention to: Different CTEs, fatigue, creepsElectronic Packaging Technologies20
Chip-Package Connection: Wire Bonding Connections are made from the chipto the pad frame via thin wires– Typically 100x100 !m metal pads on200 !m pitch– Mechanical bonding of one pin at atime (sequential) The wires are made of low resistivityalloys or doped metals– Gold and aluminum– Also copper and silver– Typically 25 !m diameter for logicdevicesElectronic Packaging Technologies21Drawbacks of Wire Bonding Slow process– One pin at a time– Speeds from 4 to 10 wires persecond Pads are limited to the chipperiphery– Low pad density and reducedpad pitch– Up to approx 500 pads Electrical limitations– High inductance ( 1nH) ofwires ( 10nH plus pins)– Crosstalk between adjacentwiresElectronic Packaging Technologies22
Chip-Package Connection: TAB Tape automated bonding– The interconnections arepatterned on a multilayerpolymer tape.– The tape is positioned abovethe bare die' so that the metaltracks (on the polymer tape)correspond to the bondingsites on the die Advantages over wire bonding– Smaller and closer pads:higher density, up to 850 pins– Better electrical characteristics– Faster procedure but moreexpensive machineryElectronic Packaging Technologies23Chip-Package Connection: Flip-ChipChipSolder bumpsPackage padsThe chip is “soldered” tothe package substrateusing the solder balls“bumps” that have beengrown over the die padsControlled Collapse Chip Connection, C4Electronic Packaging Technologies24
Flip-Chip Advantages and Drawbacks Flip-chip is currently the preferred process for highend integrated circuits– High frequency of operation, small size and/or many I/O pins Many advantages:– Improved density: pad pitch and size is not better than inwire bonding, but I/O pads can be distributed all over the die,not just in the borders– Reduced inductance ( 0.1 nH) due to the elimination ofwires and better power/ground behavior– Faster process, all the pads are soldered at the same time Some drawbacks– Alignment is critical (and blind), although there is sometolerance due to its self-alignment property– Mechanical stress due to different thermal expansioncoefficients of the silicon and the package substrate25Electronic Packaging TechnologiesFlip-Chip: No Longer Pad-Limited ChipsCore-LimitedPad-LimitedElectronic Packaging TechnologiesArea-Array Pads26
Flip-Chip: Growing the Solder Bumps There are many techniques, for example:Plated bumping removes the oxide layer on the Al bond pad throughwet chemical cleaning processes. Electroless nickel plating is thenemployed to cover the Al bond pad with a nickel layer to the desiredplating thickness, forming the foundation of the bump. An immersiongold layer is then added over the nickel bump for protection. Adhesive bumping is a flip-chip bumping processthat stencils electrically conductive adhesive over anunderbump metallization placed over the bondpad. The stenciled adhesive serves as the bumpafter it has been cured.A bump is typically 70-100 µm high, and 100-125 µm in diameter.Current materials for the bumps are: SnPb Eutectic (63%Sn,37%Pb), high lead (95%Pb, 5%Sn) or lead-free (97.5%Pb,2.5%Ag) compositionsElectronic Packaging Technologies27Flip-Chip Concept at the Board Level:BGA PackagesElectronic Packaging Technologies28
Flip-Chip: Direct Access to Silicon Viewor Using a Lid/OvermoldElectronic Packaging Technologies29Materials Used in Electronic PackagingElectronic Packaging Technologies30
Metals In a metal, the outer electrons are shared among all the atomsin the solid Each atom gives up its outer electrons and becomes slightlypositively charged– The negatively charged electrons hold the metal atoms together– Since the electrons are free to move, they lead to good thermaland electrical conductivity It is impossible to see through metals, since these valenceelectrons absorb any photons of light which reach the metal.– No photons pass throughElectronic Packaging Technologies31Metal Alloys Alloys are compounds consistingof more than one metal– Adding other metals can affect thedensity, strength, fracturetoughness, plastic deformation,electrical conductivity andenvironmental degradation Unlike pure metals, many alloys donot have a single melting point.– Instead, they have a melting rangein which the material is a mixtureof solid and liquid phases.– Alloys can be designed with asingle melting point, and these arecalled eutectic mixtures– Example: 63%Sn, 37%PbElectronic Packaging Technologies32
Properties of Metals and Metal Alloys At least good, but usually excellent thermal andelectrical conductivities Relatively high densities, especially compared topolymers– Materials with high densities often contain atoms with highatomic numbers, such as gold– However, some metals such as aluminum or magnesiumhave low densities, and are used in applications that requireother metallic properties but low weight Fracture Toughness– Ability to avoid fracture, especially when a flaw is introduced Plastic deformationElectronic Packaging Technologies33Lead Poisoning Saturnism, plumbism or painter's colic Neurological problems– reduced IQ, nausea, abdominal pain, irritability, insomnia,excess lethargy or hyperactivity, headache and, in extremecases, seizure and coma Gastrointestinal problems– constipation, diarrhea, abdominal pain, vomiting, poorappetite, weight loss Other associated affects are anemia, kidneyproblems, and reproductive problems– Lead toxicity often causes the formation of bluish line alongthe gums, which is known as the "Burtons's line " Elimination of lead: RoHS EU directives (Restrictionof Hazardous Substances)Electronic Packaging Technologies34
RoHS Directive “Directive on the restriction of the use of certain hazardoussubstances in electrical and electronic equipment”– 2002/95/EC, took effect July 1st, 2006 Forbidden substances:–––––– LeadMercuryCadmiumHexavalent chromium (Cr6 )Polybrominated biphenyls (PBB)Polybrominated diphenyl ether (PBDE)The maximum permitted concentrations are 0.1% or 1000 ppm(except for cadmium, which is limited to 0.01% or 100 ppm) byweight of homogeneous material:– Limits do not apply to the weight of the finished product– But to any single substance that could be separated mechanicallyElectronic Packaging Technologies35Ceramics Ceramics: Often broadly defined asany inorganic nonmetallic material.Examples of such materials can beanything from NaCl (table salt) to clay(a complex silicate).– Metallic plus nonmetallic elementsjoined together by ionic and/or covalentbonds– Crystalline, polycrystalline oramorphous. The last one is sometimestreated as a different category, glasses Glasses: An inorganic nonmetallicamorphous material (does not have acrystalline structure). Examples ofglasses range from bottles to theextremely high purity silica glass inoptical fibers.Electronic Packaging Technologies36
Properties of Ceramics and Glasses High melting temperatureLow densityHigh strength and HardnessWater resistanceCorrosion resistanceMany ceramics are good electrical and thermal insulators– Graphite: electrical and thermal conductor Low to null ductilityLow fracture toughnessSome ceramics have special properties:– Magnetic materials– Piezoelectric materials– Superconductors at very low temperaturesElectronic Packaging Technologies37Plastics: Polymers Poly-mer “several-parts”–––– Typically organic materialsBut could be inorganic like siliconesOffer poor protection levelsBut they are cost effectiveElectrical characteristics– High resistivity (insulator)– Low dielectric constant ( 4) Thermal characteristics– Bad thermal conductivity– Low coefficient of thermalexpansion (CTE) for T Tg– Thermal stability up to 300 ºC forsome compounds Good mechanical propertiesHigh water and solvent absorptionGood adhesionElectronic Packaging Technologies38
Glass Transition and Melting Point Glass transition temperature Tg :RubberMeltingPointTgGlassFluidRubber Melting point: Temperature of fusion Glass and melting points of a polymer will determinewhich applications it will be suitable for– Many industrially important polymers have glass transitiontemperatures near the boiling point of water, and they aremost useful for room temperature applications– Some specially engineered polymers can withstandtemperatures as high as 300 ºCElectronic Packaging Technologies39Characteristics of a Package Thermal performance – Ability to dissipate the heatgenerated by the IC – The best package is useless if itcannot be soldered. It should notrequire excessive handlingprecautionsSignal integrity– To ensure that the packageparasitic inductances andcapacitances do not distort theI/O signalsPower distribution– The package must be able tosupply enough current for the ICto work, and it must be alsocapable of handling the highestcurrent peaksManufacturability Testability– To check if all pins have beencorrectly soldered. It is alsoabout its prototyping capabilities Reliability– The package must provide agood long-term reliability even inthe harshest environmentsAll this features should be achieved at a reasonable COSTElectronic Packaging Technologies40
Thermal Behavior of a Package For modeling the thermal behavior of a package, acomparison to this circuit is used:TJTA"JA– Where the intensity is the power dissipated, the thermalresistance means the ability of the package to remove theheat, and the voltage relates to the temperatures– This model just says that the increase in the junctiontemperature respect to the ambient one is proportional to thepower dissipated and the thermal characteristics of thepackageTJ # T A " ! JA PDElectronic Packaging Technologies41Thermal Resistances The thermal model of a package can be verycomplex: Moreover, it may have a heat sink over it, or a forcedflux of air, etc. So the thermal resistance is oftensplitted into resistance from junction-to-case and fromcase-to-ambient:! JA # ! JC " ! CAElectronic Packaging Technologies42
Some Thermal Aspectsin Package DesingCavity-Up or Cavity-Down packagesThermally enhanced packages (TI)43Electronic Packaging TechnologiesElectrical Model of the PackageCrosstalkPackageSignal PadsSignal PinsChipVDDBond WireLead werDistributionand IntegritySignalIntegrityElectronic Packaging Technologies44
Very strong driver:despicable outputimpedanceVVSpice Simulation: Strong DriverL150nOFFSET 0AMPLITUDE 3.3DELAY 0RISE 5nFALL 5nPWIDTH 45nPERIOD 100nV2C150p010 MHz square signal with 5 nsfall and rise timesPin inductance 50 nH, parasiticcapacitance 50 pFToo muchringingElectronic Packaging Technologies45VVSpice Simulation: Weak DriverR1OFFSET 0AMPLITUDE 3.3DELAY 0RISE 5nFALL 5nPWIDTH 45nPERIOD 100nV2500L150nVery weak driver:500 ohm outputimpedanceC150p010 MHz square signal with 5 nsfall and rise timesPin inductance 50 nH, parasiticcapacitance 50 pFToo muchdampingElectronic Packaging Technologies46
Parasitic Capacitance as Function of theInterconnection LevelC 10 x f FaradsC pFaradsC 10 x pFaradsC 10 x pFaradsC 100 x pFaradsElectronic Packaging Technologies47Crosstalk Crosstalk occurs when a line or pin (aggressor)induces some voltage changes in other line or pin(victim) via their mutual capacitance or inductanceSignal PadsSignal PinsChip This two parameters depend on the geometry of thepackage, and the mutual inductance also on theproximity of a ground pin or plane (length of groundloops)Electronic Packaging Technologies48
Power Integrity and DistributionTotal Pin 000The PWR/GND pins are no longer despicable in comparison to the I/OsElectronic Packaging Technologies49Ground Bounce When many I/O simultaneously switch from 1 to 0, a sudden current surge goesthrough the GND leads parasitic inductance, causing the chip ground to “bounce”A similar phenomenon happens to Vcc, “Vcc Sag”, but historically has been lessworrying because the increased voltage margin for ones (in 5V TTL, ‘0’ goes from0 to 0.8 volts, but a ‘1’ is anything between 2.0 and 5.0 volts)Electronic Packaging Technologies50
Power/Ground Count There are many reasons for the recent increase in the numberof PWR/GND pins– To reduce the parasitic resistance so that the power consumptionrequirements of the IC are fulfilled (several Amps)– To reduce the parasitic inductance in order to eliminate the groundbounce and Vcc sag problems– To ensure that there is a ground pin close to each I/O pin so thatthe ground loops are minimized and so the crosstalk High-end devices, at the package level, currently have a 8-1-1I/O-Power-Ground relationship– Using flip-chip, the number of PWR/GND pairs at chip level is muchhigher, because there are many bumps connected to the powerand ground planes created in the package substrateElectronic Packaging Technologies51Evolution in Power/Ground LayoutElectronic Packaging Technologies52
Manufacturability PCB requirements– Minimum size of the tracks andpads– Pin pitch: The higher, the easiest– For the same number of I/Os,BGAs have much higher pitches Solderability– BGAs self-alignment versusconventional SMD “selfmisalignment” Handling precautions– Plastic packages tend to absorbmoisture that may cause thepackage to crack during soldering Bottom line: Always keep incontact to your PCB manufacturingand mounting partnerBGA256 vs QFP160Electronic Packaging Technologies53Testability While BGAs are good in almost every field– Electrical and thermal performance– Solderability Their verification capabilities are very poor– No access to I/O signals, no way to view the pads to assessthe quality of the soldering– Automated verification approaches are needed– X-Ray inspection may also be needed to ensure the qualityof the soldering process, or special optic-fiber cameras Fine-pitch BGAs Is prototyping over?– Fortunately, there are companies who build sockets foralmost everythingElectronic Packaging Technologies54
Example: Emulation TechnologyElectronic Packaging Technologies55Reliability Plastic packages are best suited for controlled environments– For example, low moisture and applications not requiring long-termstorage or extreme temperature cycling Ceramic packages offer the best performance in terms ofthermal characteristics, moisture absorption and endurance inharsh environments– Moisture permeability is orders of magnitude better than in plastics– Moisture is the most important cause of corrosion Qualification tests impart varying extent of stresses on thepackages– The purpose is to accelerate any potential failure mechanism,which may occur during actual operation– Temperature cycling, high-pressure and high moisture, etc – The manufacturer provides reliability data based on these tests Fabrication process certification– QML, MIL-PRF-38535Electronic Packaging Technologies56
Package Types The basic types are sharedamong manufacturersBut each manufacturer hasits own nomenclature forthe variants– Acronym salad Fundamental types for ICs––––Example:Philips DIP, PGACLCCSOP, PLCC, QFPBGASpecific types for discreteand passive componentsElectronic Packaging Technologies57Example of IC PackagesElectronic Packaging Technologies58
DIP: Dual In-Line PackageElectronic Packaging Technologies59PGA: Pin Grid ArrayElectronic Packaging Technologies60
CLCC: Ceramic LeadLess Chip CarrierElectronic Packaging Technologies61SOP: Small Outline PackageElectronic Packaging Technologies62
PLCC: Plastic Leadless Chip CarrierElectronic Packaging Technologies63QFP: Quad Flat PackElectronic Packaging Technologies64
BGA: Ball Grid Array65Electronic Packaging TechnologiesReduced Pin Count DevicesTO-92TO-220TO-3SOT-23 (TO-236)SOT-223 (TO-261)TO-263Electronic Packaging Technologies66
Passive Components Through hole – AxialSurface Mount (SMD)– 1206, 0805, 0603, 0402 (in x 100)120660 mils120 mils– Radial– Case A: 3216, Case B: 3528,Case C: 6032 (mm x 10)Electronic Packaging Technologies67Advanced Packaging:Multi-Chip-Modules (MCMs) Increase integration level ofsystem (smaller size)Decrease loading of externalsignals: Higher performanceNo packaging of individual chipsProblems with known good die:– Single chip fault coverage: 95%– MCM yield with 10 chips:(0.95)10 60% Problems with coolingExpensiveElectronic Packaging Technologies68
Yielddie cost is f (die area) 4Electronic Packaging Technologies69Pentium Pro:Example of Commercial MCMCPU plus separated, on-package, level-2 cachesElectronic Packaging Technologies70
Chip Stacked Packages Currently based on wirebonding, but there is researchon flip-chip Used for example in memorydevices for mobile applications(Flash SRAM)71Electronic Packaging TechnologiesExamples of Chip Stacked Packages: IntelBiggerFlashFlash andSRAMElectronic Packaging Technologies72
But Are Packages Really Necessary?Chip-On-Board Mounting (COB) Chips are directly mounted over the PCB,using a wire bonding technique very similarto the one used in packagingDrawbacks– Obtaining Known-Good-Dies (KGD)– Component StorageElectronic Packaging Technologies73Sources Sammakaia, Fundamentals of Electronic PackagingT. Di Stefano, Issues Driving Wafer-Level Technologies, Stanford U.Renesas Semiconductor Assembly ServiceFrear, Materials Issues in Area-Array Microelectronic PackagingHarris & Bushnell, Packages and Power, Rutgers UniversityThe Nordic Electronics Packaging GuidelineBrown, Advanced Electronic Packaging: With Emphasis on MCMs Additional sources for Images: Xilinx, IBM, Bill Bertram (Wikipedia),Farnell, John Fader (Wikipedia), Philips, Maxim, Intel, FraunhoferInstitute, SMART Group, Hochschule Heilbronn, DRS Test & EnergyManagement, cpu-world.com, hardwarezone.com, Amkor, TI,coolingzone.com, NASA Office of Logic Design, Altera, Fairchild,Emulation Technology, National Semiconductor, OKISemiconductor, ASE Malaysia, Pro Systems China, ToshibaElectronic Packaging Technologies74
Electronic Packaging Technologies 2 Introduction to Electronic Packaging Electronic Packaging is a multi-disciplinary subject – Mechanical, Electrical and Industrial Engineering, Chemistry, Physics and even Marketing Electronic Packaging: Housing and interconnection of
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BONDED FRP SHEETS IN RC SHEAR WALLS FOR EARTHQUAKE RESISTANCE Ahmed HASSAN Graduate Student, Carleton University, Canada ahmedhassan@cmail.carleton.ca David T. LAU Professor, Carleton University, Canada David.lau@carleton.ca Carlos A. CRUZ-NOGU
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Fundamentals of Packaging Technology Seminar Course Outline . Semester 4 Day Three 4-7 Packaging Machinery Package design and machine-ability . packaging 4-11 Packaging Software Standards Applications Use in Packaging Special Packaging Applications - Graphics Design - Structural Design
interconnection, thermal management, and mechanical and environmental protection. Each packaging level reflects a trade-off among many interrelated factors including design requirements, economics, and manufacturing infrastructure. (Keywords: Electronic components, Electronic packaging, Packaging design, Packaging levels.)
In 2006, this unique packaging technology was patented4 and qualified in 2008 through test and demonstration on a naval missile system5. Since this time, imbedded packaging technologies have enabled the miniaturization of electronics hardware that current packaging technologies, such as SMT, cannot. Imbedded Packaging Technology Design Methodology
AKKINENI NAGESWARA RAO COLLEGE, GUDIVADA-521301, AQAR FOR 2015-16 1 The Annual Quality Assurance Report (AQAR) of the IQAC Part – A AQAR for the year 1. Details of the Institution 1.1 Name of the Institution 1.2 Address Line 1 Address Line 2 City/Town State Pin Code Institution e-mail address 08674Contact Nos. Name of the Head of the Institution: Dr. S. Sankar Tel. No. with STD Code: Mobile .
