Development Of A New Improved High Performance Flip Chip .

OvermoldFlat LidExposedDieFlip Chip on SubstrateFlip ChipAfter MoldingMold Cpda) 3D Quarter Model (Section A-O-B).Flip ChipFlat LidMoldCpdFinal ProductBT substrateSolder JointsFig 4. Actual Samples of the XP-fcBGA Package.PCB3. Package Performance AssessmentsTest vehicles of the XP-fcBGA package were built fordetailed development study. It has a body size of 40x40mmwith a nominal total height of 2.82mm. The package is madeup of a 6-layer build-up BT substrate of 1.1mm, a flip chip ofsize 16x22mm backgrinded to 0.52mm thick, a mold blocksize of 39x39mm with thickness of 0.63mm, and a flat copperlid of 40x40x0.5mm in dimension. Various aspects of thepackage performance in structural integrity, solder jointsfatigue assessment, thermal, electrical and reliability will bediscussed. The Finite Element Analysis (FEA) technique isalso employed to study the impact of temperature excursionon materials deformation. Three-dimensional (3D) FEAmodels were created using ANSYS 7.0 for stress, warpage andsolder joint fatigue analysis. The 3D quarter model wascreated along the cut-out section A-O-B for package relatedstudy, while the 3D slice model of the section O-C was usedfor board interconnects analysis (see Figs. 5 & 6). The firstlevel of flip chip interconnects (solder bumps) was assumedto exhibit the behavior of the underfill layer, hence notincluded in both the FE models. Inelastic strain energydensity representing the damage per cycle of the solder jointwould be extracted from the solution for solder jointreliability study. Detailed material properties and FEAmodeling have been reported in Chong et al’s work [7].ACMoldCpdOBFlipChipFig 5. Package Cut-out for the 3D Quarter and 3D SliceModels.BT SubstrateCuPadSolder JointSMPCBb) 3D Slice Model (Section O-C).Fig 6. 3D Quarter and Slice FE Models for XP-fcBGA.3.1. Structural IntegrityWith package sizes large than 20x20mm, warpage willalways pose many challenges to the assembly processes. Forinstance, high warpage in a package will cause great difficultyin solder ball mounting onto the substrate and the eventualboard assembly. With the present package size of 40x40mmfor the flip chip package, it is critical to keep packagewarpage to a minimum. The package warpage was extractedfrom the finite element models after a thermal loading from150oC to 25oC and comparison made with actual substratewarpage measured by a RVSI machine (refer to Fig. 7). Itcould be seen that XP-fcBGA has generated a higher warpagethan the HP-fcBGA (approx. 31% higher). However with theuse of a low stress adhesive, a lower warpage could beachieved by the XP-fcBGA package. Good correlation trendhas been observed between the finite element results andexperimental values, with the exception on the low stressadhesive case. The reason can be attributed to the use ofelastic material properties for the mold compound. Asmolding compound exhibits viscoelastic behavior in nature,warpage may not be accurately captured by simulation.Nonetheless, the warpage data is considerably low for allcases falling below 150um.11762004 Electronic Components and Technology Conference

damage to it will result in losing its electrical functionality.The heat spreader attached onto the package is able todissipate large amount of heat away from the die and help tomaintain a low junction temperature. Any failure in the heatspreader will lower its heat transfer efficiency and may resultin over-heating of the silicon die. The die stress, as well as theinterfacial shear stresses for die/underfill and heatspreader/mold compound are plotted in Fig. 9. With siliconbeing a brittle material, the maximum principal stress (S1)accumulated in the die will be extracted for analysis.Package Warpage vs Package Design1.5FEANormalised Warpage1.25Exp10.750.50.250HP-fcBGAXP-fcBGAPackage DesignXP-fcBGA- Low Stress AdhePrincipal and Shear Stresses in the Package1.4HP-fcBGAXP-fcBGAXP-fcBGA - Low Stress AdheNormalised Stresses1.2Fig 7. Package Warpage for Different Package Designs.Due to the additional molding process in the XP-fcBGAdesign, the package will be subjected to post mold curingprior to lid attachment. When the mold compound cures andset permanently, chemical shrinkage and CTE mismatch willinduce warpage to the package thereby increasing thedifficulty in mounting the flat lid onto the flip chip and moldtop surface. A parametric study was performed in aid toreduce package warpage after post mold curing (before lid isattached). From the results plotted in Fig. 8, it was discoveredthat an increase in substrate thickness has resulted in thedecrease in warpage. The reason can be attributed to thethicker substrate that makes the structure more rigid, henceless susceptable to deformation. The use of a lower Tg moldcompound can also help to reduce the package warpage. Areduction in Tg changes the effective CTE of the moldcompound, giving a coupling effect on the overall CTEmismatch within the system. However, the varying in diethickness and modulus of mold compound does not havemuch influence on the warpage behavior.Param etric Study of XP-fcBGA Warpage1.25Substrate Thk1.125Die .60.40.20Die (S1)Die ThkTgHS InterfaceFig 9. Stresses Experienced in Flip Chip BGA Packages.In the die stress response, the XP-fcBGA designillustrated a lower die stress than the HP-fcBGA package. Areduction of 23% in die stress could be achieved by the XPfcBGA, with a larger 33% difference by using the low stressadhesive. The stress distribution in the die is shown in Fig.10, with the maximum stress located at the outermost cornerof the active die side. The interfacial shear stress, where it isan indication of the adhesion strength between interfacematerials, is investigated next. At the die to underfillinterface, XP-fcBGA has again constituted to a lower shearstress with a significant decrease of more than 80% comparedto HP-fcBGA. It strongly indicates slimmer chances ofdelamination taking place at the die/underfill interface. Inboth cases, the mold compound serves as a buffer to absorbthe residual stresses resulting from CTE mismatches undertemperature loading. Without the mold compound, the die andunderfill would have to absorb the bulk of residual stresswhich may eventually lead to potential failure such as diecracking or interfacial delamination.4Max. S1V a ria t io nSubstrate ThkDie/UF InterfacePackage Material / InterfaceDie CentreM odulusFig 8. Parametric Effects on XP-fcBGA StructureWarpage (without lid).Failures such as die cracking and interfacial delaminationwould render a package faulty and useless. Thus reliability ofa new package under development has to be characterizedeffectively. The package stresses are being analyzed next,with focus on the flip chip and heat spreader. The silicon diebeing the heart and most vital part in the package, any1177S1 (MPa)Die Centrea) HP-fcBGAS1 (MPa)Max. S1b) XP-fcBGAFig 10. Principal Stress Distribution Within the Die.2004 Electronic Components and Technology Conference

3.2. Solder Joint Reliability AssessmentsSolder joints fatigue performance has always been acritical concern in new package development. Generalindustrial standard requires the solder joint’s fatigue life of apackage to surpass 1000 cycles. Board level solder jointreliability of the XP-fcBGA package will be tested andanalysed. When undergoing a temperature cycling testaccording to the test standard of IPC-SM-785 (-40oC to 125oC, 1 cycle/hr), the HP-fcBGA package reported acharacteristic life (63.2% failure, θ) of 1777 cycles (with a βof 11.3) with the first failure occurring at 1430 cycles. Thefailure data is illustrated in the Weibull plot (2 parameters) ofFig. 11. Based on a 3D slice model FEA simulation, thewidely accepted Darveaux’s volume average strain energydensity approach was used to calculate the solder joint fatiguelives [8]. A predicted fatigue life of 1425 cycles for HPfcBGA was computed, with fairly good correlation of 1.25times with the experimental value. The FEA model alsopredicted solder joint cracks occurring at the package side(due to solder-mask defined pad design), agreeing well withthe cross-sectional failure analysis pictures (see Fig. 12).Similar modeling and fatigue life predictions for the XPfcBGA package were performed, with estimated improvedfatigue life shown in Fig. 13. The XP-fcBGA design revealeda significant fatigue improvement of 2.62 times of the HPfcBGA. It is thus anticipated that the actual characteristic lifefor XP-fcBGA can surpass 1777 cycles. The solder jointfatigue life can be further enhanced by the use of a low stressadhesive. The preceding section illustrated a significantreduction in the shear stress at the lid interface in XP-fcBGAdesign. Lesser interference is thus transmitted from the lid tothe solder joints through the molding compound. Due to itslow modulus, the low stress adhesive provides a largecushioning effect between the lid and the mold compound.The trend revealed that with the removal of the directinteraction between the lid and BT substrate, the new designis able to survive longer fatigue life cycles. This prediction isindeed very encouraging as high reliability solder jointperformance is always desired for this package type andapplication. Test vehicles of the XP-fcBGA package iscurrently undergoing thermal cycling test with the sameloading conditions. Test result up to the present stage standsat 2100 cycles with no solder joint failure. Complete failuredata will be reported at a later stage and be correlated tomodeling results.Solder Joint Fatigue Life Predictions3.5Normalised Fatigue LifeWith attention moving to the heat spreader interface, alower shear stress of more than 70% decrement is beingobserved in XP-fcBGA over HP-fcBGA. With a largeradhesion area of the flat lid to the mold compound in the XPfcBGA package than the cavity lid to the substrate in HPfcBGA, the flat lid is able to experience a lesser shear impact.This also shows a much lower interaction force between thelid and the mold compound than the lid with the BT substrate.Thus the potential of delamination at lid interface is reducedto a minimum for the XP-fcBGA package, enhancing the lid’scapability in dissipating heat.32.521.510.50HP-fcBGAXP-fcBGAPackage DesignXP-fcBGA- LowStress AdheFig 13. Solder Joint Fatigue Lives Comparison for Flip ChipBGA Packages.63.2%Fig 11. Weibull Reliability Data Plot for HP-fcBGA Package.Package SideCracks along thetop solder interfacePCB SideFig 12. Cross-sectional View of Cracked Solder Jointsin the HP-fcBGA Package.In driving for higher solder joint reliability, furtherparametric studies have been performed on die and lidthickness. In both cases, a lower thickness has constituted to abetter board level solder joints fatigue performance. It is dueto the lower effective CTE mismatch with the PCB by thethinner die and lid.3.3. Heat Dissipation and Thermal PerformanceSuperior heat dissipation and low thermal resistance isone of the main attractions for the development of thispackage type. It is therefore necessary to ensure the thermalperformance of the XP-fcBGA package should not becompromised. Thermal simulations were carried out usingFlotherm 4.1 to assess the heat dissipation capability of theXP-fcBGA design. Experimental thermal measurementconducted for HP-fcBGA package mounted onto a 4-layerPCB (based on JESD 51-9 standard) recorded a junction-toambient thermal resistance (θJA) of 8.89oC/W at zero11782004 Electronic Components and Technology Conference

windspeed, achieving good correlation with the modelingresults [7]. A device power of 3 watts was being used.Correlation within 10% range was also obtained for forcedconvection conditions of 1, 2, & 3m/s windspeeds. With thesame power capacity, thermal simulation predictions for theXP-fcBGA package are shown in Table 1.Table 1. Thermal Simulations Data of θJA (oC/W) forHP-fcBGA and XP-fcBGA Packages.Package08.688.838.82Windspeed AXP-fcBGAXP-fcBGA*XP-fcBGA with6.17external heatsink* Single dispense of thermally conductive adhesiveThrough thermal simulations in the still air condition,only a slight increase in θJA of 1.62% to 1.73% for the XPfcBGA package was observed. It thus reveals comparableheat dissipation strength with the HP-fcBGA package.However XP-fcBGA is able to perform better than HPfcBGA thermally under forced convections. This is due to theextra thermal path from the die’s side surfaces to the moldcompound and eventually through the flat lid (where this pathdoes not exist in the HP-fcBGA design). It results in a largerheat distribution area on the lid surface where air flow is ableto remove the heat away. And results for all cases showed thatthermal resistance can be reduced with assisted air flows. Forfurther improvement of the thermal performance, an externalheatsink can be attached to the XP-fcBGA package top formaximum heat removal. Modeling result showed that with apin fin type heatsink (base area 2"x2", overall height 0.78", number of pins 11x11) mounted, a 30% reduction inθJA can be achieved. Lastly thermal measurements will beconducted for the XP-fcBGA package with values to becorrelated with modeling results.3.4. Electrical Performance ConsiderationsThe use of flip chip solder bumps interconnect hasshortened the electrical path between the silicon chip and thechip carrier significantly, thus driving ultimate performancesfor higher speeds and frequencies. The possible use of thincore in BT substrates will provide a low impedance and highstatic capacitance for the power distribution network in an ICpackage. With decreased operating voltage and increasedpower demands, the current needed to run a system isincreasing which requires low impedance for the powerdistribution network. In addition, the increased staticcapacitance between the power and ground plane is helpful inpower supply decoupling.There are several advantages for using a thin coresubstrate. Firstly, the thin core minimizes the loop inductanceof power/ground as well as signal nets due to reduced vialength. For a power/ground net with a parasitic inductance ofL, the induced noise due to one signal switch is given by:di(1)V Ldtwhere V is the induced voltage, and di is the transient currentover the signal transition period of time dt. Thus, a reduced Lresults in lower simultaneous switching noise (SSN). For asignal net, lower inductance causes less impedancediscontinuity resulting in higher signal transmissionefficiency. Secondly, thin core can offer superior wiringdensities due to smaller via diameters. This makes it possiblefor packing a shrunk die in a smaller package, or retaining thepackage size while allocating more I/Os for power/grounddistribution. The increased power/ground I/Os will result ineven lower parasitic inductances, higher current handlingcapability as well as better heat dissipation. Thirdly, thin coresubstrate is able to offer a thin profile package solution. If thethickness of a package’s substrate is kept constant, thin coreprovides the possibility for more solid planes to beincorporated as power or ground plane. These solidpower/ground planes have the advantage of providing moreeffective system power distributions. Furthermore, signallayers are usually sandwiched between the power and groundplanes forming stripline structures (see Fig. 14) compared to amicrostrip design. A 2-dimensional electrical simulation waspreformed using Ansoft Spicelink, and the parasitics formicrostrip and stripline designs were compared in Table 2. Byvirtue of a stripline structure, adjacent signal nets will have alower near-end and a nearly zero far-end crosstalk for a Interference (EMI). Thus it could be seen that a thin coresubstrate provides several possibilities in improving apackage electrical performance. The overmolded structure ofXP-fcBGA will help in easy handling of the thin coresubstrates during assembly processes, and thus able to driveits popularity in the semiconductor industry.Table 2. Electrical Performance Parameters for“Microstrip” and “Stripline” Structures.StructureLsLmCs(nH/mm) (nH/mm) fF/mm)17.75Zo(Ohm)100.00X talk(%)18%18.9045.006%148.90* Note: w/s 35/45 um and dielectric thickness 100um.WSWtDielectrica) MicrostripHWSWDielectricHtHb) StriplineFig 14. Schematic for “Microstrip” and “Stripline” Structures.11792004 Electronic Components and Technology Conference

3.5. Package Level Reliability Tests ResultsReliability tests were conducted at the package level toassess its internal structural integrity. The flip chip solderbumps interconnection was monitored and check on possibleinterfacial delamination was carried out using CSAMtechnique. Three tests namely temperature cycling (TC),unbiased autoclave (also known as pressure cooker test, PCT)and high temperature storage (HTS) were conducted with asample size of 22 units for each test. The moisturepreconditioning was set at JEDEC level 4. Both the standardand low stress adhesive dispense types were studied. Table 3shows the results of the reliability evaluation. The XP-fcBGApackage with the low stress adhesive showed good reliabilitydata with no solder bump crack or delamination failure. Thestandard adhesive XP-fcBGA tests are still in progress andresults will be reported when completed.Table 3. Package Reliability Test Results for theXP-fcBGA Package.ResultsTestTCPCTHTSCondition(JEDEC Standard)-55oC to 125o2 cycles/hr(JESD22-A104-B)121oC / 100% RH2 atm(JESD22-A102-C)150 oC(JESD22-A103-B)XP-fcBGAXP-fcBGA(low stress adhe)Test in progressPassed 1000 cyclesTest in progressPassed 168 hoursTest in progressPassed 1000 hours4. ConclusionsThe new XP-fcBGA package has been successfullydeveloped, with various aspects of the package performancein structural integrity, solder joints fatigue assessment,thermal, electrical and reliability being addressed. Byencapsulating the flip chip with a molding compoundexposing the die top surface, a flat lid can be mounted on theplaner top surface for heat dissipation purpose. As such, thedirect interaction of the metal lid with the substrate can beremoved thus enhancing solder joint reliability.The XP-fcBGA package shows clearly its strength overthe original HP-fcBGA design with comparable packagewarpage, lower package stresses and higher solder jointfatigue lives. In board level reliability test, the XP-fcBGAsolder joints have survived more than 2000 cycles with noobserved failure. In package level reliability tests, the optionof low stress adhesive is able to withstand stringent testconditions. In addition, the XP-fcBGA package is able toexhibit high heat dissipation capability with a low thermalresistance. With the overmolded structure which increasesrigidity during process handling, thin core substrates can beused for improved electrical performances. Furtherdevelopments of the XP-fcBGA design include expanding todifferent package sizes and thickness, and the evaluation ofthe new design as a multi-chip module.5. Future WorkExperimental board level solder joint fatigue lives will becorrelated with simulation results. Thermal measurements willalso be conducted for the XP-fcBGA package to determine itsthermal resistance. Lastly, package level reliability testsresults will be reported when tests are completed.AcknowledgmentsThe authors would like to thank the UTAC managementin support of the development project. The use of thermalcycling test and measurement systems in the NanyangTechnological University is also greatly appreciated.References1. J. Xue et al, “Evaluation of Manufacturing AssemblyProcess Impact on Long Term Reliability of a HighPerformance ASIC using Flip Chip HyperBGAPackage”, Proc 53rd Electronic Components andTechnology Conf, New Orleans, LA, May 2003, pp. 359364.2. S. Y. Teng, M. Brillhart, “Reliability Assessment of aHigh CTE CBGA for High Availability System”, Proc52nd Electronic Components and Technology Conf, 2002,pp. 611-616.3. L. Zhang, S.S. Chee, A. Maheshwari, “MPM BGAPackage”, Proc 52nd Electronic Components andTechnology Conf, 2002, pp. 1114-1118.4. B. Stone, J.M. Czarnowski, J.R

Fig 1. One-Piece Lid High Performance Flip Chip BGA (HP-fcBGA) Package. A new design of flip chip BGA package (patent pending) has been looked into for improved board level performance. In this new design, the flip chip will be plastic encapsulated (with the die top surface expo