ECE 546 Lecture 28 High Speed Links

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ECE 546Lecture ‐ 28High‐Speed LinksSpring 2020Jose E. Schutt-AineElectrical & Computer EngineeringUniversity of Illinoisjesa@illinois.eduECE 546 – Jose Schutt‐Aine1

Inter-IC Communication TrendsECE 546 – Jose Schutt‐Aine2

High-Speed Bus and Networks Memory Bus (Single‐ended, Parallel) Cable (Differential, Serial) DDR (4.266 Gbps) USB (4.266 Gbps) LPDDR4 (4.266 Gbps) HDMI (4.266 Gbps) GDDR (7 Gps) Firewire: Cat 5, Cat 5e, Cat 6 XDR (differential, 4.8 Gbps) Storage (Differential, Serial) Wide IO2, HBM eMMC, UFS (6 Gbps) SAS, STATA (6 Gbps) Front Side Bus (Differential, Parallel) FiberChannel (10 – 20 Gbps) QuickPath Interconnect (6.4 Gbps) HyperTransport (6.4 Gbps) Computer IO (Differential, Parallel) PCIe (8 Gbps) InfiniBand (10 Gbps) Ethernet (Differential, Serial) XAUI (10 Gbps) XFI (10 Gbps) CEI‐6GLR SONNET (10 Gbps) 10GBase‐x, 100GBase (25 Gbps)ECE 546 – Jose Schutt‐Aine3

Basic Serial Link ArchitectureECE 546 – Jose Schutt‐Aine4

Basic Serial Link ArchitectureECE 546 – Jose Schutt‐Aine5

Why SERDES? Traditional parallel communication not suitablefor inter‐IC data transport in high‐speed links.– Serial links are most cost‐effective.–– High design overhead due to cross‐talk, data‐skew.Parallel links extra pins Higher packaging costs.Speed v/s cost tradeoff with serial links.Solution SERDES!!!––Parallel communication still used in internal buses ofICs thus a need for SerDes.Mitigate cost while maintaining high‐speeds with a fastserial‐parallel data conversion.ECE 546 – Jose Schutt‐Aine6

What is a SERDES? SERDES SERializer – DESerializer––––Used to transmit high speed IO‐data over a seriallink in I/O interfaces at speeds upwards of 2.5Gbps.SerDes TX: transmit parallel data to receiveroverhigh speed serial‐link.SerDes RX: receive data from serial‐link and deliverparallel data to next‐stage.Advantage: Fast signaling, robust, high signalintegrity.ECE 546 – Jose Schutt‐Aine7

Serial Links in SoC: Oracle SPARC T5*About 50 SerDes IPs– Single IP power & area– Integrated with SoC– Portable with SoC* J. Hart et al., "A 3.6GHz 16-Core SPARC SoC Processor in 28nm", Proceedings of the 2013 IEEEInternational Solid-State Circuits Conference.ECE 546 – Jose Schutt‐Aine8

Serializer/Deserializer Blocks Serializer: DeserializerECE 546 – Jose Schutt‐Aine9

Embedded Clock Architecture Converts parallel data into serial data (Tx side) Applies equalization to the data stream Converts serial data into parallel data (Rx side)ECE 546 – Jose Schutt‐Aine10

Forwarded Clock Architecture Additional lane for delivering the clock Jitter introduced by the clock can be canceled at receiver Offers better jitter performanceECE 546 – Jose Schutt‐Aine11

DC and AC CouplingAC Coupled LinkAC coupling hasadvantage of isolatingcommon‐mode voltagelevels between RX and TXTerminated to VCCDC Coupled LinkTerminated to VSSTerminated to VcmECE 546 – Jose Schutt‐Aine12

Transmitter Need large enough voltage swing Pre‐driver is used to deliver large enough swing to Tx FFE can be realized anywhere along data pathECE 546 – Jose Schutt‐Aine13

Current-Mode Driver Group of differential pairs Arranged in a binary weighted form Controlled by 6-bit equalized dataECE 546 – Jose Schutt‐Aine14

Current-Mode DriverDC-Coupled LinkAC-Coupled LinkECE 546 – Jose Schutt‐Aine15

Receiver Receives data Performs equalization Recovers data and clockECE 546 – Jose Schutt‐Aine16

Link Classification Number of data bits per clock cycle Need multiple phases for half rate and quarter rateECE 546 – Jose Schutt‐Aine17

Signaling Protocol NRZ vs RZECE 546 – Jose Schutt‐Aine18

Clock SynthesizerECE 546 – Jose Schutt‐Aine19

PLL OverviewBasic PLL Block Diagram: Closed‐loop feedback system that synchronizes theoutput CLK phase with that of the reference CLK. Tracks phase changes w/i the specified BW. Idea is that the PD (Phase Detector) will compare thereference CLK phase with that generated by the VCO.– Goal: Stabilize Δ𝜙 0 such that VCO output CLK andreference CLK are locked at same frequency and phase.– Tracks low‐frequencies but rejects high‐frequencies.ECE 546 – Jose Schutt‐Aine20

Why need PLLs? Reduces jitter. Reduces clock‐skew in high‐speed digital ckts. Instrumental in frequency synthesizers. Essential building block of CDRs.ECE 546 – Jose Schutt‐Aine21

PLL Building BlocksBasic PLL Components: PD/PFD Phase/Phase Frequency Detector CP Charge pump circuit LF Loop‐Filter VCO Voltage controlled oscillator Frequency DividerECE 546 – Jose Schutt‐Aine22

PD/PFD CircuitsCommon PD Implementations:Common PFD Implementations:XOR PDGilbert‐cell Mixer PD/PFD are strictly digital circuits in high speed SerDestransceivers. Ideal PD is a “multiplier” in time‐domain, ex: Mixer Analog PD High Jitter, noise. XOR PD sensitive to clock duty cycle PFD best to lock phase and frequency!ECE 546 – Jose Schutt‐Aine23

PFD Theory1. PFD is needed to adjust thecontrol voltage for VCO accordingto the phase difference betweenthe VCO output and referencefrequency2. PFD can be seen as a state machine withthree states. It will change the controlvoltage of VCO according to its current stateand phase/frequency difference will causestate transition.ECE 546 – Jose Schutt‐Aine24

PFD Analysis1. PFD is in state 0 with no phasedifference.2. PFD is in state 1 with positivephase difference.3. PFD is in state ‐1 with negativephase difference.ECE 546 – Jose Schutt‐Aine25

PFD Design OverviewCharge pumpDowncircuitUP circuitPhase Frequency detectorECE 546 – Jose Schutt‐Aine26

PFD SimulationECE 546 – Jose Schutt‐Aine27

The Hogge Phase Detector Two Functions– Transition detection– Phase DetectionECE 546 – Jose Schutt‐Aine28

The Charge Pump Combination ofcurrent source andsink Converts PD outputto a current pulseinfluencing controlvoltage of VCOECE 546 – Jose Schutt‐Aine29

Charge-Pump CircuitCommon CP Implementations: Used in conjunction with PFD over PD LF combo. b/c:– Higher capture/lock acquisition range of PLL0 provide no device mismatch exists.– Δ𝜙– Provide infinite gain for a static phase‐errorECE 546 – Jose Schutt‐Aine30

The Loop Filter Low‐pass forrejection of highfrequency noise Forms the controlvoltage of the VCOECE 546 – Jose Schutt‐Aine31

Loop-FilterCommon LF Implementations: Extracts average of PD error signals generate VCO controlvoltage. Integrates low‐frequency phase‐errors on C1 to set avg. freq. R adds thermal noise, C1 determines loop BW, C2 smoothenscontrol voltage ripple.ECE 546 – Jose Schutt‐Aine32

Loop-Filter Design1. Needed to filter out high frequency noisegenerated by PFD2. Due to the superior performance of PFD, onlya passive second order RC low pass filter isneeded.WhereAssuming25MHzLow pass filter forcurrent inputECE 546 – Jose Schutt‐Aine33

Voltage Controlled Oscillator Generates anoutput withoscillationfrequencyproportional to thecontrol voltage Helps the CDRaccumulate phaseand achieve lockECE 546 – Jose Schutt‐Aine34

VCOCommon VCO Implementation:LC‐Tank Oscillator Extracts average of PD error signals generate VCOcontrol voltage. PLL acts like a High‐pass filter with respect to VCO jitter. VCO always has one pole!ECE 546 – Jose Schutt‐Aine35

Oscillators Overview Closed‐Loop Transfer function:– Barkhausen’s criteria for oscillation:–– 𝜔 oscillation‐frequency.EC

ECE 546 –Jose Schutt‐Aine 3 Memory Bus (Single‐ended, Parallel) DDR (4.266 Gbps) LPDDR4 (4.266 Gbps) GDDR (7 Gps) XDR (differential, 4.8 Gbps) Wide IO2, HBM Cable (Differential, Serial) USB (4.266 Gbps) HDMI (4.266 Gbps) Firewire: Cat 5, Cat 5e,

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