Using PSoC 3 And PSoC 5LP GPIO Pins - AN72382

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AN72382Using PSoC 3 and PSoC 5LP GPIO PinsAuthor: Greg ReynoldsAssociated Project: No Associated Part Family: All PSoC 3 and PSoC 5LP partsSoftware Version: PSoC Creator 2.1 SP1 and higherRelated Application Notes: For a complete list of related application notes, click here.Abstract AN72382 shows you how to use GPIO pins effectively in PSoC 3 and PSoC 5LP. Major topics include GPIObasics, configuration, mixed-signal use, registers, interrupts, and low-power behavior.ContentsIntroduction .1GPIO Pin Basics .2Physical Structure of GPIO Pins .2Digital System Interconnect Overview .2Analog Routing Overview .3GPIO Power Structure and Limits .3Relative Voltages of VDDA, VDDD, and VDDIO .4Startup and Low-Power Behavior .4DMA Access to GPIO Pins .4Port Interrupt Control Unit.4GPIO Pins in PSoC Creator .5PSoC Creator APIs .5Pin Component Symbols and Macros .5Pin Component Interrupts.5External Terminals .6Manual Pin Assignments .6GPIO Examples, Tips, and Tricks .7The GPIO ―Hello World‖ Project .7Read an Input and Write to an Output .7Add Multiple GPIO Pins as a Logical Port .7Configure GPIO Output Enable Logic .9Enable the Configurable XRES Feature .9Disable Debug Logic on GPIO Pins . 10Toggle GPIOs Faster with Data Registers. 10Use 8051 Special Function Registers . 11Use both Analog and Digital on a GPIO . 11Control Analog Switching with Hardware. 12Use the DSI as a Clock Source . 14Change PICU Settings with Firmware . 16Gang Pins for More Drive/Sink Current . 17Level-Shift Signals . 17Related Application Notes . 18www.cypress.comAbout the Author . 18Appendix A: GPIO API and Register Reference . 19Component API . 19Per-Pin API . 19GPIO Registers . 20Nonvolatile Latches . 21Appendix B: PSoC Creator Settings and Registers. 22Document History. 33Introduction The any-signal-to-any-pin routing available with PSoC 3and PSoC 5LP GPIOs helps to optimize PCB layout,shorten design time, and allow for a large degree ofsolder-less rework. However, with this freedom comes asteeper learning curve than with a traditionalmicrocontroller. This application note introduces you toPSoC 3 and PSoC 5LP GPIO basics and demonstratestechniques for their effective use in a design.It is assumed that you are familiar with PSoC Creator and the PSoC 3 and PSoC 5LP family device architecture.If you are new to PSoC, see the introductions in AN54181,Getting Started with PSoC 3, and AN77759, GettingStarted with PSoC 5LP. If you are new to PSoC Creator,see the PSoC Creator home page.For a list of related PSoC design resources, see theRelated Application Notes section.Document No. 001-72382 Rev. *E1

Using PSoC 3 and PSoC 5LP GPIO PinsGPIO Pin BasicsDigital System Interconnect OverviewIn PSoC 3 and PSoC 5LP devices, the GPIO, SIO, andUSB pins are similar. Unlike GPIO pins, though, the SIOand USB pins have different drive strengths andapplication-specific features. Some of the GPIO pins alsohave secondary dedicated functions, such as opampinputs and outputs, programming and debugginginterfaces, or DAC outputs. When they are not being usedfor special functions, all GPIO pins behave the same.Depending on the package type, PSoC devices can haveas many as 62 GPIO pins.The PSoC 3 and PSoC 5LP digital subsystem has aprogrammable interconnect that allows connectionsbetween the built-in peripherals, custom logic functions(Universal Digital Blocks, or UDBs), and any I/O pin. Thedigital system interconnect (DSI) routing interface allowsGPIO pins to connect to any digital resource in the chip,as Figure 2 illustrates.Figure 2. DSI Block DiagramPhysical Structure of GPIO PinsThe GPIO pins have eight drive modes to support themany analog and digital I/O capabilities that PSoC offers.A detailed block diagram of the GPIO structure appears inthe Technical Reference Manual (TRM), as well as in thePSoC 3 and PSoC 5LP family datasheets. Figure 1 showsa simplified version.Figure 1. Simplified GPIO Block DiagramDigital Input PathDigital SystemInterconnectDigital Output PathGPIOAnalog Global& Analog MuxLCD BusAnalogLCDThe various drive modes and their custom settings aredescribed in detail in the Pins Component datasheet,which is available as part of PSoC Creator or as aseparate download from the Cypress website.www.cypress.comAll digital resources are routed to the DSI for connection toeach other or to the system core. For more details aboutthe DSI operation, see the UDB Array and Digital SystemInterconnect section of the TRM.Document No. 001-72382 Rev. *E2

Using PSoC 3 and PSoC 5LP GPIO PinsAnalog Routing OverviewThe GPIO pins are connected to analog resources, or toeach other, through a series of analog routing busesjoined by switches and muxes. The two primary analogrouting buses are the Analog Global (AG) bus and AnalogMux (AMUX) bus. The AG bus is divided into fourquadrants (AGL0-4, AGL4-7, AGR0-4, and AGR4-7), andthe AMUX bus is divided into two halves (AMUXL andAMUXR). Figure 3 shows a portion of the analog routingdiagram from the TRM.supplies power to a particular set of pins is indicated bysolid lines drawn on the pinout diagrams. Figure 4 showsa 48-pin PSoC 3 with the VDDIO quadrant indicatorshighlighted in red.Figure 4. Example VDDIO Quadrants Highlighted in RedFigure 3. Upper-Left Analog Routing QuadrantThe VDDIO pins are often tied to the same power rail asVDD. Little thought is given to how much current anyindividual VDDIO quadrant is sourcing and sinking, but thereare limitations. Table 1 shows the limits according toPSoC family and package type.Table 1. VDDIO Quadrant Current LimitsFamilyEach AGx can connect to two of the pins on an associatedport in each quadrant, while each AMUX can connect toevery pin on its half of the chip. The analog buses alsoconnect to the inputs and/or outputs of various analogresources, such as comparators, DACs, and ADCs. Inaddition, switches allow the left and right buses to beconnected to each other.An in-depth description of the analog routing system in thePSoC 3 and PSoC 5LP devices is in the Analog Routingsection of the TRM. Application notes AN58304 andAN58827 discuss analog routing and pin selection indetail.100-pin68-pinPSoC 3PSoC 5LP48-pin100-pin68-pinPSoC 548-pinGPIO Power Structure and LimitsIn general, GPIO pins can source 4 mA and sink 8 mA.GPIO pins can be ganged together (shorted) to allow formore current to be sourced or sunk than what a single pincan provide, but you need to consider additional powerlimitations.PackageSourceSink100 mA perVDDIO100 mA per VDDIO100 mAVDDIO0 VDDIO2100 mAVDDIO0 VDDIO2100 mAVDDIO1 VDDIO3100 mAVDDIO1 VDDIO320 mA per VDDIO20 mA per VDDIO20 mAVDDIO0 VDDIO220 mAVDDIO0 VDDIO220 mAVDDIO1 VDDIO320 mAVDDIO1 VDDIO3Note: Total source sink current should not exceed 100mA forany VDDIO quadrant (or VDDIO pair in the case of the 48-pinpackages).PSoC 3 and PSoC 5LP devices provide as many as fourindividual I/O voltage domains through the VDDIO pins. Inthe PSoC 3 and PSoC 5LP datasheets, the VDDIO pin thatwww.cypress.comDocument No. 001-72382 Rev. *E3

Using PSoC 3 and PSoC 5LP GPIO PinsIn applications for which the typical current sourced andsunk by the GPIO pins is expected to exceed 80 percentof the limit, make sure that no single quadrant of GPIOpins exceeds its maximum under the worst operatingconditions. Doing so might mean that the design needs touse pins in separate VDDIO quadrants to spread out thecurrent.Relative Voltages of VDDA, VDDD, and VDDIOVDDA must be at the highest voltage present on thePSoC 3 or PSoC 5LP device. All other power supply pinsmust be less than or equal to VDDA. The VDDD and VDDIOpins may be less than, greater than, or equal to eachother.The System tab of the Design Wide Resources file has avoltage configuration section that lets you define thevoltage at which each power domain will operate. Thevalues entered in these fields, shown in Figure 5, are usedby PSoC Creator if a component or feature is dependenton the voltage at which it is running.Figure 5. Voltage Configuration in Design Wide ResourcesStartup and Low-Power BehaviorOut of the box, all GPIO pins start up in an Analog HI-Zstate, where they remain until reset is released. The initialoperating configuration of each pin is loaded during bootand takes effect at that time. You can change the resetbehavior of GPIOs using the PRTxRDM fields of thenonvolatile latch array, which are written when the PSoCis programmed.In all low-power modes, GPIO pins retain their state untilthe part is reset or awakened. The port interrupt logiccontinues to function in all low-power modes so that pinscan be used as wakeup sources.Note UDB-based components, such as control registers,are typically not active during sleep or hibernate. They canglitch when the PSoC enters or exits these modes. Theglitch could cause a GPIO to be set at an unwanted state.To avoid that, set the pins explicitly to a HIGH or LOWlogic state before the PSoC enters a low-power mode.DMA Access to GPIO PinsThe PSoC devices have a DMA controller that connects todifferent internal peripherals, including the I/O interface.Because GPIO registers are memory-addressed, DMAtransfers can be used to configure GPIO pins and writedata to the digital output path without requiring any actionby the CPU.DMA configuration and data transfer is a topic that is toocomplex to be covered in this application note. Severalother application notes and code examples are available,including AN52705 – PSoC 3 and PSoC 5LP – GettingStarted with DMA.Port Interrupt Control UnitThe PSoC 3 and PSoC 5LP have a Port Interrupt ControlUnit (PICU) that manages I/O interrupts. Each GPIO pincan generate an interrupt on a rising edge, falling edge, oreither edge condition. Level-sensitive interrupts areimplemented by tying a cy isr component to the interruptterminal of a pin component.Proper voltage configuration in PSoC Creator isrecommended in all cases, regardless of whichcomponents or features are used.When a GPIO interrupt is triggered, the corresponding bitin that GPIO‘s status register is set to ‗1‘. The bit willremain at ‗1‘ until the register is read or a chip resetoccurs. The API provided by PSoC Creator managesGPIO interrupt configuration and reporting.The individual GPIO interrupt signals within a port areORed together, and a single PICU request is sent to theinterrupt controller. The port interrupt requests are daisychained together to generate a single wakeup signal,which is sent to the PSoC power manager. The PICUremains active in all low-power modes, but the individualGPIO interrupts must still be managed after wakeup.www.cypress.comDocument No. 001-72382 Rev. *E4

Using PSoC 3 and PSoC 5LP GPIO PinsGPIO Pins in PSoC CreatorThis section describes how to use PSoC Creator toconfigure and manipulate GPIO pins. PSoC Creatorcombines text and graphical editing interfaces so thatdesigners can set their hardware configuration and writefirmware at the same time.PSoC Creator APIsCypress provides a set of APIs that you can use todynamically control GPIOs through firmware. The APIs forthe Pins component enable access on both a componentwide and per-pin basis.You are not confined to one type of pin configurationbased on which macro symbol you choose. After youplace the pin symbol on the schematic, you can configureits behavior using the component customizer optionsdescribed later in this document.By default, several components, including the cy pinscomponent, are hidden from view in the componentcatalog. To view the hidden components, simply go toTools Options in PSoC Creator and select the ShowHidden Components check box, as Figure 7 shows.Figure 7. Show Hidden Components OptionThe cy boot component also provides functions to accesschip resources. The functions in cy boot are not part ofthe individual component libraries, but the libraries canuse them. The per-pin APIs, which are provided as part ofcy boot, in the cypins.h file, are documented in the Pinssection of the System Reference Guide. You can usethese APIs to control the configuration registers for eachphysical pin.For a summary and a simple code example for the APIsrelated to GPIOs, see Appendix A: GPIO API and RegisterReference, starting on page 19.Pin Component Symbols and MacrosThe cy pins component is the recommended way forinternal PSoC resources to connect to a physical pin. Itallows PSoC Creator to automatically place and route thesignals within the PSoC based on the chosenconfiguration of the pin. The standard Cypress componentcatalog contains four types of predefined GPIOconfigurations (macros) in the Ports and Pins class ofsymbols—analog, digital bidirectional, digital input, anddigital output. Drag one of these component macros to theschematic to add a pin to the project, as Figure 6 shows.Figure 6. Pin Component Symbol Types in PSoC CreatorThere are no differences in features or behavior betweenthe hidden cy pins component and the pins macros. Themacros are added for convenience to help reduce designtime.Pin Component InterruptsYou can enable interrupts in pin components with thecy pins configuration dialog in PSoC Creator, as Figure 8shows. Double-click on the pin component to open it.Figure 8. Interrupt Configuration in PSoC Creatorwww.cypress.comDocument No. 001-72382 Rev. *E5

Using PSoC 3 and PSoC 5LP GPIO PinsThe pin component symbol changes when interrupts areenabled, as Figure 9 shows. The irq signal of the pincomponent will toggle when a pin interrupt is triggered.You do not need to connect the irq terminal to an isrcomponent to enable a pin interrupt.Figure 9. The Pin Component Symbol Changes withInterrupts EnabledIf interrupts are enabled, you can use only one pincomponent with each physical GPIO port. The reason forthis limitation is that all pin interrupts in a port are ORedtogether, so only one irq signal can be shown on theschematic.For example, consider two pin components with interruptsenabled, as Figure 10 shows. These components cannotbe mapped to pins in the same physical port becausethere are now two separate irq signals in the Creatorschematic, but there is really only one physical PICUinterrupt generated for the entire port.External TerminalsThe cy pins configuration dialog also has an option toshow an external terminal. This allows you to add Off-ChipComponents to your schematic and show theirconnections to the Pin. Figure 12 shows an example of aPin component driving an off-chip LED.Figure 12. Off-Chip Component Connection ExampleManual Pin AssignmentsA Pins component is assigned to a physical pin throughthe Pins tab of the Design-wide Resources interface(cydwr). PSoC Creator automatically assigns pins if noneare chosen by the user, but this may lead to pin placementthat is more difficult to route on a PCB. Also, some GPIOpins are directly connected to analog or digital resources.Figure 13 shows three assigned pins. The pins highlightedin gray were manually assigned, and the pin highlighted inyellow was automatically assigned. The Lock check boxprevents the pin from being reassigned by PSoC Creator.Figure 13. Pin Assignment in cydwr WindowFigure 10. Two pin components with interrupts.Creator will give an error if you try to assign these twocomponents to the same port. The accepted method is toassign multiple pins to the same component, as Figure 11shows. This ensures that there is only one irq signal in theschematic for that physical port. You can still assign eachpin its own interrupt edge type. The only limitation is thatthe pins must be contiguous.Figure 11. Pin selection with different interrupt edge types.PSoC Creator makes it simple to reassign pins as needed,but designers should consider pin selection before boardsare designed. The Analog Interconnect diagram in theTRM, AN58304, and AN58827 are valuable resources tohelp determine optimal analog pin selection.You can also use the PICUx INTTYPEy registers toenable or change interrupts on any GPIO pin, regardlessof component settings. See the appendices for moreinformation on these registers.www.cypress.comDocument No. 001-72382 Rev. *E6

Using PSoC 3 and PSoC 5LP GPIO PinsGPIO Examples, Tips, and TricksThis section provides practical examples of how to useGPIO pins. The examples were generated for PSoC 3devices, but the same techniques apply to PSoC 5LP.Both basic examples and more advanced techniques areincluded.Read an Input and Write to an OutputThis example demonstrates how to read and write to aGPIO pin with the component APIs. The output pin willdrive the inverse of the input pin state.1.The GPIO “Hello World” ProjectFigure 15. Input and Output Example SchematicThe simplest use of a GPIO is to set the output of a pinHIGH or LOW. This example demonstrates how to set theoutput using the Pin component API.1.Place a Digital Output Pin component, configured toStrong drive mode, in the project schematic, asFigure 14 shows.2.Name the component ―MyPin‖ and assign it to P6[2].Place two pins in the project schematic—one digitalinput pin and one digital output pin—as Figure 15shows.Figure 14. Hello World Example Schematic2.Use the component APIs to set the state of OutputPinbased on InputPin, as shown here:for(;;){/* Set OutputPin state to theinverse of the InputPin state */OutputPin Write( InputPin Read() );}3.In main.c, use the component API to toggle theoutput, as shown here:for(;;){/* Set MyPin output state to high */MyPin Write(1);/* Delay for 500ms */CyDelay(500);/* Set MyPin output state to low */MyPin Write(0);The result is that OutputPin is always at the opposite stateas InputPin.Add Multiple GPIO Pins as a Logical PortIn PSoC Creator, you can organize a group of as many as64 pins into a logical port, which can then be referenced incode by the port‘s defined name. All of the pins may bepart of the same physical port, or they may be fromseparate physical ports.1.Place a single pin symbol, as Figure 16 shows.Figure 16. Single Pin Symbol Placed in a Schematic/* Delay for 500ms */CyDelay(500);}4.Build the project and program the PSoC.The result is an output that toggles high/low every 500 ms.2.Double-click on the pin symbol to open the pincustomizer window.3.Type the number of pins in the Number of Pins fieldin the configuration window.The pins will appear in the list below the field. Selectan individual pin in the list to allow it to be customizedindependently of the others. Select [All Pins] to affectevery pin in the port.4.www.cypress.comFor this example, set three of the pins as digitaloutput pins. Set the last as a digital input, as shown inFigure 17.Document No. 001-72382 Rev. *E7

Using PSoC 3 and PSoC 5LP GPIO PinsFigure 17. One of Four Pins Configured as a DigitalInputThis feature does not affect the behavior of the port.Note All pins must be of the same type for them to bedisplayed as a bus.Figure 20. Four Pins Displayed as a Port Bus Symbol7.(Optional) Select Contiguous in the Mapping tab toforce the pins to be physically adjacent, as Figure 21shows.Figure 21. Contiguous Pin Placement Option5.Click OK to apply the changes.After you define the number of pins and their types,the schematic symbol will resemble Figure 18.Figure 18. Pin Component in Port ConfigurationWhen you select Contiguous, PSoC Creator willmodify the list of available pinout options to match theport‘s configuration, as Figure 22 shows.6.(Optional) Select Display as Bus in the Mapping tabof the pin configuration window to display the port asa bus symbol, as Figure 19 and Figure 20 show.Figure 22. Pin Placement of Contiguous Port PinsFigure 19. Display as Bus OptionThese features are described in more detail in the pinconfiguration window and the Pins component datasheet.www.cypress.comDocument No. 001-72382 Rev. *E8

Using PSoC 3 and PSoC 5LP GPIO PinsFigure 25. Control Register Driving Pins' OutputEnableConfigure GPIO Output Enable LogicThis example demonstrates how to configure and use theoutput enable logic of a GPIO pin.1.Place two digital output pins in the project schematic.2.Open the configuration dialog for each pin and checkthe Output Enable box, as Figure 23 shows.Figure 23. Output Enable Selection7.Add the following code to the main.c file:for(;;){for( i 0; i 3; i ){ControlReg Write(i);CyDelay(500);}}8.Compile and program the PSoC 3 or PSoC 5LP.The result is the output of the two pins gated by the stateof ControlReg.3.Place a control register in the schematic.4.Configure the control register for two outputs, asFigure 24 shows.Figure 24. Control Register Configured with TwoOutputsEnable the Configurable XRES FeatureThis example demonstrates how to enable theconfigurable XRES feature. You can configure Pin P1[2]as an optional XRES pin to support an external reset forsmall packages. The feature is also available in the largerpackages.1.Open the System tab in the Design Wide Resourcesfile, as shown in Figure 26.2.Select the Use Optional XRES box to enable theoptional XRES logic. If this box is selected, P1[2]stops functioning as a GPIO pin and is configured asan active LOW input with an internal pull-up.Figure 26. Optional XRES Pin Enable5.Add two clock components, configured in any way.6.Connect the clocks to the pins, as Figure 25 shows.www.cypress.comDocument No. 001-72382 Rev. *E9

Using PSoC 3 and PSoC 5LP GPIO Pins3.Program the PSoC to write the setting to thenonvolatile array. It will take effect after the nextpower-on.4.Clear the check box and reprogram the PSoC torestore normal GPIO functionality.Note that all PSoC 3 and PSoC 5LP devices come fromthe factory with the optional XRES feature disabled. Usingthe configurable XRES pin does not change thefunctionality of a dedicated XRES pin.Figure 28. Pin placed in schematic3.Disable Debug Logic on GPIO Pinsfor(;;){// These are API functionsMyPin Write(1); //set MyPin outputMyPin Write(0); //clear MyPin output}This example demonstrates how to disable the debuglogic associated with the port 1 pins. If the debug portfeature is enabled, the PSoC will enter debug mode if itdetects activity on these pins at boot time.1.2.Open the Design-wide Resources file and click theSystem tab.Add the following code to the main.c file:4.Select Debug ports disabled from the drop-downmenu, as Figure 27 shows.Observe the output of P6[0] using the API, as Figure29 shows.Figure 29. Pin Toggle Using API Switch MethodFigure 27. Debug Port Disabled3.Compile and program the PSoC 3 or PSoC 5LP.Note that the debug port must be manually enabled againif debug is needed. Disabling the debug interface does notaffect the ability to program the device.5.for(;;){MyPin DR MyPin MASK; //Set MyPinMyPin DR & MyPin MASK; //Clear}Toggle GPIOs Faster with Data RegistersThis example demonstrates how to use port data registersand masks to quickly toggle pins. While the componentAPI is the easiest way to control GPIO pins, the number ofprocessor cycles needed to update the pin can affect howfast a toggle can occur. The register definitions and masksin the pin name .h file that is created for eachcomponent can be used to more quickly update pins.1.Place a digital output pin in the schematic and name itMyPin for convenience.2.Configure the component with no hardwareconnection and assign it to a physical pin (thisexample uses P6[0]), as Figure 28 shows.www.cypress.comReplace the previous code in main.c with this code:6.Observe the output of P6[0] using the fast switching,as Figure 30 shows.Document No. 001-72382 Rev. *E10

Using PSoC 3 and PSoC 5LP GPIO PinsFigure 30. Pin Toggle Using Fast Switching MethodUse both Analog and Digital on a GPIOThis example demonstrates how to configure and use apin for both analog and digital functions. Assume that aGPIO pin needs to output a 10-kHz clock signal for a shorttime, switch to a reference voltage for a short time, andthen switch back to the 10-kHz signal.1.Place an analog pin, a VREF, and a clock in theschematic.2.Assign the pin component to a physical pin (thisexample uses P3[6]), as Figure 31 shows.Figure 31. Basic Components Placed in the SchematicA pin can toggle almost four times faster using the fastswitching method rather than the API functions. This codealso has the advantage of being portable. If the pinassignment is changed during development, you do nothave to write to a specific physical pin‘s registers.Use 8051 Special Function Registers3.The 8051 in PSoC 3 has a set of Special FunctionRegisters (SFRs) that allow faster access to a limited setof PSoC registers. You can use two of those registers toquickly toggle GPIO pins.Figure 32. MyPin Configured as Both Analog and Digital1.Place a digital output pin component in the projectschematic and assign it to a physical pin, just as youdid in the previous example. This example also usesP6[0].2.Add the following code to the main.c file:Configure the pin with both analog and digital outputsettings, as Figure 32 shows./* Enable SFR access for P6[0]. *//* Only done once in the beginning. */SFRPRT6SEL 0x01;/* Toggle GPIO pin. */for(;;){/* Switch on P6[0] */SFRPRT6DR 0x01;/* Switch off P6[0] */SFRPRT6DR & 0x01;}4.3.An alternative method is:Connect the clock to the digital terminal and the VREFto the analog terminal, as Figure 33 shows.for(;;){/* Toggle P6[0] */SFRPRT6DR 0x01;}Either method will result in very fast pin toggles. For moreinformation on the SFRs, see the PSoC 3 TechnicalReference Manual.www.cypress.comDocument No. 001-72382 Rev. *E11

Using PSoC 3 and PSoC 5LP GPIO PinsFigure 33. PSoC Creator Schematic of Analog andDigital Switching SchemeThe result is an output that alternates every 100 msbetween the clock signal and the reference voltage.Control Analog Switching with HardwareThis example shows how an external signal is used togate the output of an analog pin without CPU intervention.1.Place a digital input pin (Ext Gate in this example),an analog pin (Analog Out), and an analog source(VDAC8) in the project schematic, as Figure 34shows.Figure 34. Components for Hardware-Controlled Gate5.Compile the project to create the API necessary todetermine the analog routing that PSoC Creator uses.6.Open the cyfitter cfg.c file and look for eitherCYREG PRT3 AG (the analog global enable) orCYREG PRT3 AMUX (the analog mux bus enable). Inthis case, the routing tool has chosen to use the AGbus for Port 0, as shown below.CY SET REG8(CYREG PRT3 AG, 0x40);Note that the analog routing may change wheneverthe project is rebuilt. If any changes are made to theproject, you must check the routing.7.Add the following code to the main.c file:2.Configure the Analog Out pin with both analog anddigital properties, as Figure 35 shows.Figure 35. Analog Out Pin Configurationfor(;;){/* Set pin to Analog */// Set P3[6] to Analog Hi-ZCyPins SetPinDriveMode(CYREG PRT3 PC6, PIN DM ALG HIZ);// Make AG connection for P3[6]CY SET REG8(CYREG PRT3 AG,CY GET REG8(CYREG PRT3 AG) 0x40);// Wait forsignalCyDelay(100);100mswhiledriving/* Set pin to digital */// Break AG connection for P3[6]CY SET REG8(CYREG PRT3 AG,CY GET REG8(CYREG PRT3 AG) & 0xBF);//Set P3[6] to Strong Drive modeCyPins SetPinDriveMode(CYREG PRT3 PC6, PIN DM STRONG);// Wait forsignalCyDelay(100);100mswhiledriving}8.Compile and program the PSoC 3 or PSoC 5LP.www.cypress.comDocument No. 001-72382 Rev. *E12

Using PSoC 3 and PSoC 5LP GPIO Pins3.Configure the drive mode of the Analog Out pin asOpen Drain Drives Low, as Figure 36 shows.Figure 37. Analog Pin with Hardware GateFigure 36. Analog Out Pin Drive Mode5.Add the following line of code to the main.c file. In thisexample, it sets the bidirectional bit for pin 0 in thePort 0 configuration registers:// Set P0[0] to bidirectional modeCY SET REG8(CYDEV IO PRT PRT0 BIE,0x01);4.Connect the components, as Figure 37 shows.6.Assign the Analog Out pin to P0[0] to match theprevious code.7.Compile and program the PSoC 3 or PSoC 5LP.Figure 38, which is taken from the detailed GPIO blockdiagram in the PSoC 3 and PSoC 5LP datasheets, showshow the GPIO control logic is used to implement thistechnique.www.cypress.comDocument No. 001-72382 Rev. *E13

Using PSoC 3 and PSoC 5LP GPIO PinsFigure 38. Highlighted GPIO Block Diagram from the PSoC 3 and PSoC 5LP DatasheetsDigital Output PathPRT[x]SLWPRT[x]SYNC OUTVddioPRT[x]DR0DSI Output (Ext PRT[x]DM0Bidir ControlPRT[x]BIEAnalog(Analog Out)OE101Capsense ControlCAPS[x]CFG101SwitchesPRT[x]AGAnalog Global (VDAC8)PRT[x]AMUXAnalog MuxThe Ext Gate signal is routed through the DSI to thedigital portion of the Analog Out pin. The signal from theDSI (red) is routed to the analog switches because

PSoC 3 and PSoC 5LP GPIO basics and demonstrates techniques for their effective use in a design. It is assumed that you are familiar with PSoC Creator and the PSoC 3 and PSoC 5LP family device architecture. If you are new to PSoC, see the introductions in AN54181, Getting Started

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