PRELIMINARY PSoC 5LP: CY8C58LP Family Datasheet .

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PSoC 5LP: CY8C58LP FamilyDatasheet PRELIMINARYProgrammable System-on-Chip (PSoC )General DescriptionWith its unique array of configurable blocks, PSoC 5LP is a true system-level solution providing microcontroller unit (MCU), memory,analog, and digital peripheral functions in a single chip. The CY8C58LP family offers a modern method of signal acquisition, signalprocessing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples(near DC voltages) to ultrasonic signals. The CY8C58LP family can handle dozens of data acquisition channels and analog inputs onevery general-purpose input/output (GPIO) pin. The CY8C58LP family is also a high-performance configurable digital system withsome part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN).In addition to communication interfaces,the CY8C58LP family has an easy to configure logic array, flexible routing to all I/O pins, anda high-performance 32-bit ARM Cortex -M3 microprocessor core. You can easily create system-level designs using a rich libraryof prebuilt components and boolean primitives using PSoC Creator , a hierarchical schematic design entry tool. The CY8C58LPfamily provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minutedesign changes through simple firmware updates. Library of advanced peripheralsFeatures Cyclic redundancy check (CRC) 32-bit ARM Cortex-M3 CPU core Pseudo random sequence (PRS) generator DC to 67 MHz operation Local interconnect network (LIN) bus 2.0 Flash program memory, up to 256 KB, 100,000 write cycles, Quadrature decoder20-year retention, and multiple security features Analog peripherals (1.71 V VDDA 5.5 V) Up to 32-KB flash error correcting code (ECC) or configuration storage 1.024 V 0.1% internal voltage reference across –40 C to 85 C Up to 64 KB SRAM Configurable delta-sigma ADC with 8- to 20-bit resolution 2-KB electrically erasable programmable read-only memory(EEPROM) memory, 1 M cycles, and 20 years retention Sample rates up to 192 ksps 24-channel direct memory access (DMA) with multilayer Programmable gain stage: 0.25 to 16[1]AHB bus access 12-bit mode, 192 ksps, 66-dB signal to noise and distortion Programmable chained descriptors and prioritiesratio (SINAD), 1-bit INL/DNL High bandwidth 32-bit transfer support 16-bit mode, 48 ksps, 84-dB SINAD, 2-bit INL, 1-bit DNL Low voltage, ultra low power Up to two SAR ADCs, each 12-bit at 1 Msps Wide operating voltage range: 0.5 V to 5.5 V Four 8-bit 8 Msps current IDACs or 1-Msps voltage VDACs High-efficiency boost regulator from 0.5 V input to 1.8 V to Four comparators with 95-ns response time5.0 V output Four uncommitted opamps with 25-mA drive capability 3.1 mA at 6 MHz Four configurable multifunction analog blocks. Example con Low power modes including:figurations are programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and sample and hold 2-µA sleep mode with real time clock (RTC) and low-voltage detect (LVD) interrupt CapSense support 300-nA hibernate mode with RAM retention Programming, debug, and trace Versatile I/O system JTAG (4 wire), serial wire debug (SWD) (2 wire), single wire[2]viewer (SWV), and TRACEPORT interfaces 28 to 72 I/Os (62 GPIOs, 8 SIOs, 2 USBIOs ) Cortex-M3 flash patch and breakpoint (FPB) block Any GPIO to any digital or analog peripheral routability Cortex-M3 Embedded Trace Macrocell (ETM ) gener LCD direct drive from any GPIO, up to 46 16 segments [3]ates an instruction trace stream. CapSense support from any GPIO Cortex-M3 data watchpoint and trace (DWT) generates data 1.2 V to 5.5 V I/O interface voltages, up to 4 domainstrace information Maskable, independent IRQ on any pin or port Cortex-M3 Instrumentation Trace Macrocell (ITM) can be Schmitt-trigger transistor-transistor logic (TTL) inputsused for printf-style debugging All GPIOs configurable as open drain high/low, DWT, ETM, and ITM blocks communicate with off-chip debugpull-up/pull-down, High-Z, or strong outputand trace systems via the SWV or TRACEPORT2 Configurable GPIO pin state at power-on reset (POR) Bootloader programming supportable through I C, SPI,UART, USB, and other interfaces 25 mA sink on SIO Digital peripherals 20 to 24 programmable logic device (PLD) based universaldigital blocks (UDBs)[2] Full CAN 2.0b 16 RX, 8 TX buffers[2] Full-Speed (FS) USB 2.0 12 Mbps using internal oscillator Four 16-bit configurable timers, counters, and PWM blocks 67-MHz, 24-bit fixed point digital filter block (DFB) toimplement finite impulse response (FIR) and infinite impulseresponse (IIR) filters Library of standard peripherals 8-, 16-, 24-, and 32-bit timers, counters, and PWMs Serial peripheral interface (SPI), universalasynchronoustransmitter receiver (UART), and I2C Many others available in catalog Precision, programmable clocking 3- to 62-MHz internal oscillator over full temperature and voltage range 4- to 25-MHz crystal oscillator for crystal PPM accuracy Internal PLL clock generation up to 67 MHz 32.768-kHz watch crystal oscillator Low power internal oscillator at 1, 33, and 100 kHzTemperature and packaging –40 C to 85 C degrees industrial temperature 68-pin QFN and 100-pin TQFP package options.Notes1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus2. This feature on select devices only. See Ordering Information on page 115 for details.3. GPIOs with opamp outputs are not recommended for use with CapSense.Cypress Semiconductor CorporationDocument Number: 001-84932 Rev. ** 198 Champion Court ,San Jose CA 95134-1709 408-943-2600Revised December 7, 2012

PRELIMINARYPSoC 5LP: CY8C58LP FamilyDatasheetContents1. Architectural Overview . 32. Pinouts . 53. Pin Descriptions . 94. CPU . 114.1 ARM Cortex-M3 CPU .114.2 Cache Controller .124.3 DMA and PHUB .124.4 Interrupt Controller .155. Memory . 175.1 Static RAM .175.2 Flash Program Memory .175.3 Flash Security .175.4 EEPROM .175.5 Nonvolatile Latches (NVLs) .185.6 External Memory Interface .195.7 Memory Map .206. System Integration . 216.1 Clocking System .216.2 Power System .246.3 Reset .286.4 I/O System and Routing .297. Digital Subsystem . 367.1 Example Peripherals .367.2 Universal Digital Block .387.3 UDB Array Description .417.4 DSI Routing Interface Description .417.5 CAN .437.6 USB .447.7 Timers, Counters, and PWMs .447.8 I2C .457.9 Digital Filter Block .468. Analog Subsystem . 468.1 Analog Routing .488.2 Delta-sigma ADC .508.3 Successive Approximation ADC .518.4 Comparators .518.5 Opamps .538.6 Programmable SC/CT Blocks .53Document Number: 001-84932 Rev. **8.7 LCD Direct Drive .548.8 CapSense .558.9 Temp Sensor .558.10 DAC .558.11 Up/Down Mixer .568.12 Sample and Hold .569. Programming, Debug Interfaces, Resources . 579.1 JTAG Interface .579.2 SWD Interface .599.3 Debug Features .609.4 Trace Features .609.5 SWV and TRACEPORT Interfaces .609.6 Programming Features .609.7 Device Security .6010. Development Support . 6110.1 Documentation .6110.2 Online .6110.3 Tools .6111. Electrical Specifications . 6211.1 Absolute Maximum Ratings .6211.2 Device Level Specifications .6311.3 Power Regulators .6511.4 Inputs and Outputs .6911.5 Analog Peripherals .7711.6 Digital Peripherals .10011.7 Memory .10411.8 PSoC System Resources .10811.9 Clocking .11112. Ordering Information . 11512.1 Part Numbering Conventions .11613. Packaging . 11714. Acronyms . 11915. Reference Documents . 12016. Document Conventions . 12116.1 Units of Measure .12117. Revision History . 12218. Sales, Solutions, and Legal Information . 122Page 2 of 122

PSoC 5LP: CY8C58LP FamilyDatasheetPRELIMINARY1. Architectural OverviewIntroducing the CY8C58LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bitPSoC 3 and 32-bit PSoC 5LP platform. The CY8C58LP family provides configurable blocks of analog, digital, and interconnect circuitryaround a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enablesa high level of integration in a wide variety of consumer, industrial, and medical applications.Figure 1-1. Simplified Block DiagramAnalog InterconnectClock TreeIMODigital SystemQuadrature DecoderUDBUDBUDBUDBI 2C SlaveSequencerUniversal Digital Block Array (24 x UDB)8- BitTimer16- BitPWMUDB8- Bit SPIUDBUDBUDBUDBUDBUDBUDBUDB22 ΩUDBUDBFS USB2.04xTimerCounterPWM12- Bit SPIUDBMaster/SlaveUDBUDB8- BitTimerLogicUDBUDBI2CCAN2.016- Bit PRSLogicUDBUDBUARTUDBUDBUSBPHYGPIOs32.768 KHz( Optional)GPIOsXtalOscSIOSystem WideResourcesUsage Example for UDB4- 25 MHz( Optional)GPIOsDigital Interconnect12- Bit PWMRTCTimerWDTandWakeEEPROMSRAMEMIFFLASHCPU SystemInterruptControllerCortex M3CPUProgram &DebugGPIOsSystem BusMemory SystemProgramGPIOsDebug &TraceILOCacheControllerPHUBDMABoundaryScanLCD DirectDriveDigitalFilterBlockPOR andLVD1.71 to5.5 VSleepPower1.8 V LDOSMP4 x SC / CT Blocks(TIA, PGA, Mixer etc)TemperatureSensorGPIOsPower ManagementSystemAnalog SystemADCs2xSARADC 4xOpamp- 4x DACCapSense1xDel SigADC4xCMP-3 perOpampGPIOsSIOsClocking System0. 5 to 5.5 V( Optional)Figure 1-1 illustrates the major components of the CY8C58LPfamily. They are: ARM Cortex-M3 CPU subsystem Nonvolatile subsystem Programming, debug, and test subsystem Inputs and outputs Clocking Power Digital subsystem Analog subsystemDocument Number: 001-84932 Rev. **PSoC’s digital subsystem provides half of its uniqueconfigurability. It connects a digital signal from any peripheral toany pin through the digital system interconnect (DSI). It alsoprovides functional flexibility through an array of small, fast, lowpower UDBs. PSoC Creator provides a library of pre-built andtested standard digital peripherals (UART, SPI, LIN, PRS, CRC,timer, counter, PWM, AND, OR, and so on) that are mapped tothe UDB array. You can also easily create a digital circuit usingboolean primitives by means of graphical design entry. EachUDB contains programmable array logic (PAL)/programmablelogic device (PLD) functionality, together with a small statemachine engine to support a wide variety of peripherals.Page 3 of 122

PRELIMINARYIn addition to the flexibility of the UDB array, PSoC also providesconfigurable digital blocks targeted at specific functions. For theCY8C58LP family, these blocks can include four 16-bit timers,counters, and PWM blocks; I2C slave, master, and multimaster;Full-Speed USB; and Full CAN 2.0b.For more details on the peripherals see the “ExamplePeripherals” section on page 36 of this datasheet. Forinformation on UDBs, DSI, and other digital blocks, see the“Digital Subsystem” section on page 36 of this datasheet.PSoC’s analog subsystem is the second half of its uniqueconfigurability. All analog performance is based on a highlyaccurate absolute voltage reference with less than 0.1% errorover temperature and voltage. The configurable analogsubsystem includes: Analog muxes Comparators Analog mixers Voltage references ADCs DACs Digital filter block (DFB)All GPIO pins can route analog signals into and out of the deviceusing the internal analog bus. This allows the device to interfaceup to 62 discrete analog signals. One of the ADCs in the analogsubsystem is a fast, accurate, configurable delta-sigma ADCwith these features: Less than 100-µV offset A gain error of 0.2% Integral non linearity (INL) less than 2 LSB Differential non linearity (DNL) less than 1 LSBSINAD better than 84 dB in 16-bit mode This converter addresses a wide variety of precision analogapplications including some of the most demanding sensors.The CY8C58LP family also offers up to two SAR ADCs.Featuring 12-bit conversions at up to 1 M samples per second,they also offer low nonlinearity and offset errors and SNR betterthan 70 dB. They are well-suited for a variety of higher speedanalog applications.The output of any of the ADCs can optionally feed theprogrammable DFB via DMA without CPU intervention. You canconfigure the DFB to perform IIR and FIR digital filters andseveral user defined custom functions. The DFB can implementfilters with up to 64 taps. It can perform a 48-bitmultiply-accumulate (MAC) operation in one clock cycle.Four high-speed voltage or current DACs support 8-bit outputsignals at an update rate of up to 8 Msps. They can be routedout of any GPIO pin. You can create higher resolution voltagePWM DAC outputs using the UDB array. This can be used tocreate a pulse width modulated (PWM) DAC of up to 10 bits, atup to 48 kHz. The digital DACs in each UDB support PWM, PRS,or delta-sigma algorithms with programmable widths.Document Number: 001-84932 Rev. **PSoC 5LP: CY8C58LP FamilyDatasheetIn addition to the ADCs, DACs, and DFB, the analog subsystemprovides multiple: Comparators Uncommitted opampsConfigurable switched capacitor/continuous time (SC/CT)blocks. These support: Transimpedance amplifiers Programmable gain amplifiers Mixers Other similar analog componentsSee the “Analog Subsystem” section on page 46 of thisdatasheet for more details. PSoC’s CPU subsystem is built around a 32-bit three-stagepipelined ARM Cortex-M3 processor running at up to 67 MHz.The Cortex-M3 includes a tightly integrated nested vectoredinterrupt controller (NVIC) and various debug and trace modules.The overall CPU subsystem includes a DMA controller, flashcache, and RAM. The NVIC provides low latency, nestedinterrupts, and tail-chaining of interrupts and other features toincrease the efficiency of interrupt handling. The DMA controllerenables peripherals to exchange data without CPU involvement.This allows the CPU to run slower (saving power) or use thoseCPU cycles to improve the performance of firmware algorithms.The flash cache also reduces system power consumption byallowing less frequent flash access.PSoC’s nonvolatile subsystem consists of flash, byte-writeableEEPROM, and nonvolatile configuration options. It provides upto 256 KB of on-chip flash. The CPU can reprogram individualblocks of flash, enabling boot loaders. You can enable an ECCfor high reliability applications. A powerful and flexible protectionmodel secures the user's sensitive information, allowingselective memory block locking for read and write protection.Two KB of byte-writable EEPROM is available on-chip to storeapplication data. Additionally, selected configuration optionssuch as boot speed and pin drive mode are stored in nonvolatilememory. This allows settings to activate immediately after POR.The three types of PSoC I/O are extremely flexible. All I/Os havemany drive modes that are set at POR. PSoC also provides upto four I/O voltage domains through the VDDIO pins. Every GPIOhas analog I/O, LCD drive, CapSense, flexible interruptgeneration, slew rate control, and digital I/O capability. The SIOson PSoC allow VOH to be set independently of VDDIO when usedas outputs. When SIOs are in input mode they are highimpedance. This is true even when the device is not powered orwhen the pin voltage goes above the supply voltage. This makesthe SIO ideally suited for use on an I2C bus where the PSoC maynot be powered when other devices on the bus are. The SIO pinsalso have high current sink capability for applications such asLED drives. The programmable input threshold feature of theSIO can be used to make the SIO function as a general purposeanalog comparator. For devices with FS USB, the USB physicalinterface is also provided (USBIO). When not using USB, thesepins may also be used for limited digital functionality and deviceprogramming. All the features of the PSoC I/Os are covered indetail in the “I/O System and Routing” section on page 29 of thisdatasheet.Page 4 of 122

PSoC 5LP: CY8C58LP FamilyDatasheetPRELIMINARYThe PSoC device incorporates flexible internal clock generators,designed for high stability and factory trimmed for high accuracy.The internal main oscillator (IMO) is the master clock base forthe system, and has one-percent accuracy at 3 MHz. The IMOcan be configured to run from 3 MHz up to 62 MHz. Multiple clockderivatives can be generated from the main clock frequency tomeet application needs. The device provides a PLL to generatesystem clock frequencies up to 67 MHz from the IMO, externalcrystal, or external reference clock. It also contains a separate,very low-power internal low-speed oscillator (ILO) for the sleepand watchdog timers. A 32.768-kHz external watch crystal isalso supported for use in RTC applications. The clocks, togetherwith programmable clock dividers, provide the flexibility tointegrate most timing requirements.The CY8C58LP family supports a wide supply operating rangefrom 1.71 to 5.5 V. This allows operation from regulated suppliessuch as 1.8 5%, 2.5 V 10%, 3.3 V 10%, or 5.0 V 10%, ordirectly from a wide range of battery types. In addition, it providesan integrated high efficiency synchronous boost converter thatcan power the device from supply voltages as low as 0.5 V. Thisenables the device to be powered directly from a single battery.In addition, you can use the boost converter to generate othervoltages required by the device, such as a 3.3 V supply for LCDglass drive. The boost’s output is available on the VBOOST pin,allowing other devices in the application to be powered from thePSoC.PSoC supports a wide range of low power modes. These includea 300-nA hibernate mode with RAM retention and a 2-µA sleepmode with RTC. In the second mode, the optional 32.768-kHzwatch crystal runs continuously and maintains an accurate RTC.Power to all major functional blocks, including the programmabledigital and analog peripherals, can be controlled independentlyby firmware. This allows low power background processingwhen some peripherals are not in use. This, in turn, provides atotal device current of only 3.1 mA when the CPU is running at6 MHz.The details of the PSoC power modes are covered in the “PowerSystem” section on page 24 of this datasheet.PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces forprogramming, debug, and test. Using these standard interfacesyou can debug or program the PSoC with a variety of hardwaresolutions from Cypress or third party vendors. The Cortex-M3debug and trace modules include FPB, DWT, ETM, and ITM.These modules have many features to help solve difficult debugand trace problems. Details of the programming, test, anddebugging interfaces are discussed in the “Programming, DebugInterfaces, Resources” section on page 57 of this datasheet.Document Number: 001-84932 Rev. **2. PinoutsEach VDDIO pin powers a specific set of I/O pins. (The USBIOsare powered from VDDD.) Using the VDDIO pins, a single PSoCcan support multiple voltage levels, reducing the need foroff-chip level shifters. The black lines drawn on the pinoutdiagrams in Figure 2-3 and Figure 2-4 show the pins that arepowered by each VDDIO.Each VDDIO may source up to 100 mA total to its associated I/Opins, as shown in Figure 2-1.Figure 2-1. VDDIO Current LimitIDDIO X 100 mAVDDIO XI/O PinsPSoCConversely, for the 100-pin and 68-pin devices, the set of I/Opins associated with any VDDIO may sink up to 100 mA total, asshown in Figure 2-2.Figure 2-2. I/O Pins Current LimitIpins 100 mAVDDIO XI/O PinsPSoCVSSDPage 5 of 122

PRELIMINARYPSoC 5LP: CY8C58LP 2[5] (GPIO, TRACEDATA[1])VDDIO2P2[4] (GPIO, TRACEDATA[0])P2[3] (GPIO, TRACECLK)P2[2] (GPIO)P2[1] (GPIO)P2[0] (GPIO)P15[5] (GPOI)P15[4] (GPIO)VDDDVSSDVCCDP0[7] (GPIO, IDAC2)P0[6] (GPIO, IDAC0)P0[5] (GPIO, OPAMP2-)P0[4] (GPIO, OPAMP2 , SAR0 EXTREF)VDDIO0Figure 2-3. 68-pin QFN Part Pinout[4]12345678910111213141516175150Lines show VDDIOto I/O supplyassociationQFN(TOP VIEW)494847464544434241403938373635P0[3] (GPIO, OPAMP0-, EXTREF0)P0[2] (GPIO, OPAMP0 , SAR1 EXTREF)P0[1] (GPIO, OPAMP0OUT)P0[0] (GPIO, OPAMP2OUT)P12[3] (SIO)P12[2] (SIO)VSSDVDDAVSSAVCCAP15[3] (GPIO, KHZ XTAL: XI)P15[2] (GPIO, KHZ XTAL: XO)P12[1] (SIO, I2C1: SDA)P12[0] (SIO, 12C1: SCL)P3[7] (GPIO, OPAMP3OUT)P3[6] (GPIO, OPAMP1OUT)VDDIO3(GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7][5](USBIO, D , SWDIO) P15[6][5] (USBIO, D-, SWDCK) P15[7]VDDDVSSDVCCD(MHZ XTAL: XO, GPIO) P15[0](MHZ XTAL: XI, GPIO) P15[1](IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1](OPAMP3-, EXTREF1, GPIO) P3[2](OPAMP3 , GPIO) P3[3](OPAMP1-, GPIO) P3[4](OPAMP1 , GPIO) 2], GPIO) P2[6](TRACEDATA[3], GPIO) P2[7](I2C0: SCL, SIO) P12[4](I2C0: SDA, SIO) P12[5]VSSBINDVBOOSTVBATVSSDXRES(TMS, SWDIO, GPIO) P1[0](TCK, SWDCK, GPIO) P1[1](Configurable XRES, GPIO) P1[2](TDO, SWV, GPIO) P1[3](TDI, GPIO) P1[4](NTRST, GPIO) P1[5]VDDIO1Notes4. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected toground, it should be electrically floated and not connected to any other signal.5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.Document Number: 001-84932 Rev. **Page 6 of 122

PRELIMINARYPSoC 5LP: CY8C58LP FamilyDatasheetP4[5] (GPIO)P4[4] (GPIO)P4[3] (GPIO)P4[2] (GPIO)P0[7] (GPIO, IDAC2)P0[6] (GPIO, IDAC0)P0[5] (GPIO, OPAMP2-)P0[4] (GPIO, OPAMP2 , SAR0 EXTREF)P15[4] (GPIO)P6[3] (GPIO)P6[2] (GPIO)P6[1] (GPIO)P6[0] (GPIO)VDDDVSSDVCCDP4[7] (GPIO)P4[6] (GPIO)7574Lines show VDDIOto I/O 95857565554535251[6][6]VDDIO0P0[3] (GPIO, OPAMP0-, EXTREF0)P0[2] (GPIO, OPAMP0 , SAR1 EXTREF)P0[1] (GPIO, OPAMP0OUT)P0[0] (GPIO, OPAMP2OUT)P4[1] (GPIO)P4[0] (GPIO)P12[3] (SIO)P12[2] (SIO)VSSDVDDAVSSAVCCANCNCNCNCNCNCP15[3] (GPIO, KHZ XTAL: XI)P15[2] (GPIO, KHZ XTAL: XO)P12[1] (SIO, I2C1: SDA)P12[0] (SIO, I2C1: SCL)P3[7] (GPIO, OPAMP3OUT)P3[6] (GPIO, OPAMP1OUT)(OPAMP1 , GPIO) P3[5]VDDIO3(USBIO, D-, SWDCK) P15[7]VDDDVSSDVCCDNCNC(MHZ XTAL: XO, GPIO) P15[0](MHZ XTAL: XI, GPIO) P15[1](IDAC1, GPIO) P3[0](IDAC3, GPIO) P3[1](OPAMP3-, EXTREF1, GPIO) P3[2](OPAMP3 , GPIO) P3[3](OPAMP1-, GPIO) O1(GPIO) P1[6](GPIO) P1[7](SIO) P12[6](SIO) P12[7](GPIO) P5[4](GPIO) P5[5](GPIO) P5[6](GPIO) P5[7](USBIO, D , SWDIO) P15[6](TRACEDATA[1], GPIO) P2[5](TRACEDATA[2], GPIO) P2[6](TRACEDATA[3], GPIO) P2[7](I2C0: SCL, SIO) P12[4](I2C0: SDA, SIO) P12[5](GPIO) P6[4](GPIO) P6[5](GPIO) P6[6](GPIO) P6[7]VSSBINDVBOOSTVBATVSSDXRES(GPIO) P5[0](GPIO) P5[1](GPIO) P5[2](GPIO) P5[3](TMS, SWDIO, GPIO) P1[0](TCK, SWDCK, GPIO) P1[1](Configurable XRES, GPIO) P1[2](TDO, SWV, GPIO) P1[3](TDI, GPIO) P1[4](NTRST, GPIO) 787776VDDIO2P2[4] (GPIO, TRACEDATA[0])P2[3] (GPIO, TRACECLK)P2[2] (GPIO)P2[1] (GPIO)P2[0] (GPIO)P15[5] (GPIO)Figure 2-4. 100-pin TQFP Part PinoutFigure 2-5 on page 8 and Figure 2-6 on page 9 show an example schematic and an example PCB layout, for the 100-pin TQFP part,for optimal analog performance on a two-layer board. The two pins labeled VDDD must be connected together. The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and “Power System”section on page 24. The trace between the two VCCD pins should be as short as possible. The two pins labeled VSSD must be connected together.For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit BoardLayout Considerations for PSoC 3 and PSoC 5.Notes6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.Document Number: 001-84932 Rev. **Page 7 of 122

PSoC 5LP: CY8C58LP FamilyDatasheetPRELIMINARYFigure 2-5. Example Schematic for 100-pin TQFP Part with Power ConnectionsVDDDVDDDC11 UFVDDDC20.1 UFVSSDVDDIO0OA0-, REF0, P0[3]OA0 , SAR1REF, P0[2]OA0OUT, P0[1]OA2OUT, P0[0]P4[1]P4[0]SIO, P12[3]SIO, P12[2]VSSDVDDAVSSAVCCANCNCNCNCNCNCKHZXIN, P15[3]KHZXOUT, P15[2]SIO, P12[1]SIO, P12[0]OA3OUT, P3[7]VSSDVSSDVDDDC120.1 UFC151 UFC160.1 UFVDDAVDDDC80.1 UFC171 UFVSSDVSSDVDDAVSSAVCCAVSSDVSSAVDDAC91 UFC100.1 565554535251VDDDC110.1 UFVCCDVDDDOA1OUT, P3[6]P3[5], OA1 VDDIO1P1[6]P1[7]P12[6], SIOP12[7], SIOP5[4]P5[5]P5[6]P5[7]USB D , P15[6]USB D-, P15[7]VDDDVSSDVCCDNCNCP15[0], MHZXOUTP15[1], MHZXINP3[0], IDAC1P3[1], IDAC3P3[2], OA3-, REF1P3[3], OA3 P3[4], OA1-P2[5]P2[6]P2[7]P12[4], SIOP12[5], [0]P5[1]P5[2]P5[3]P1[0], SWDIO, TMSP1[1], SWDCK, TCKP1[2]P1[3], SWV, TDOP1[4], TDIP1[5], 84950VSSD12345678910111213VSSD CCDP4[7]P4[6]P4[5]P4[4]P4[3]P4[2]IDAC2, P0[7]IDAC0, P0[6]OA2-, P0[5]OA2 ,SAR0REF,P0[4]VSSDVDDD100999897969594939291908988 VDDDVSSD878685848382818079787776VCCDC60.1 UFVSSDVSSDNote The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, asshown in Figure 2-6.Document Number: 001-84932 Rev. **Page 8 of 122

PRELIMINARYPSoC 5LP: CY8C58LP FamilyDatasheetFigure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog PerformanceVSSAVDDDVSSDVDDAVSSAP lan eVSSDP lan e3. Pin DescriptionsIDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin forhigh-current DACs (IDAC).Opamp0out, Opamp1out, Opamp2out, Opamp3out. Highcurrent output of uncommitted opamp.[7]Extref0, Extref1. External reference input to the analog system.SAR0 EXTREF, SAR1 EXTREF. External references for SARADCsOpamp0-, Opamp1-, Opamp2-, Opamp3-. Inverting input touncommitted opamp.Opamp0 , Opamp1 , Opamp2 , Opamp3 . Noninvertinginput to uncommitted opamp.GPIO. Provides interfaces to the CPU, digital peripherals,analog peripherals, interrupts, LCD segment drive, andCapSense.[7]I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleepon an address match. Any I/O pin can be used for I2C SCL ifwake from sleep is not required.I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleepon an address match. Any I/O pin can be used for I2C SDA ifwake from sleep is not required.Ind. Inductor connection to boost pump.kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin.MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal

PSoC 5LP: CY8C58LP Family Datasheet Document Number: 001-84932 Rev. ** Page 3 of 122 1. Architectural Overview Introducing the CY8C58LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC

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PSoC 4: PSoC 4100 PS Datasheet Document Number: 002-22097 Rev. *B Page 3 of 44 PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs usin g

PSoC 4: PSoC 4100S Plus Datasheet Document Number: 002-19966 Rev. *H Page 3 of 44 PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using

The PSoC 5LP Prototyping Kit offers an open footprint breakout board to maximize the end-utility of the PSoC 5LP device. This kit provides a low-cost alternative to device samples while providing a platform to easily develop and integrate the PSoC 5LP device into your end-system. In addition, the

PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of systems based on PSoC 3, PSoC 4, and PSoC 5LP. See Figure 1 - with PSoC Creator, you can: 1. Drag and drop Components to build your hardware system design in the main design workspace 2.

2.1 PSoC Creator PSoC Creator is a free Windows-based Integrated Development Environment (IDE). It enables concurrent hardware and firmware design of systems based on PSoC 3, PSoC 4, and PSoC 5LP. See Figure 1 - with PSoC Creator, you can: 1. Drag and drop Components to build your hardware system design in the main design workspace 2.

agile software development methodologies (SDMs) utilizing iterative development, prototyping, templates, and minimal documentation requirements. This research project investigated agile SDM implementation using an online survey sent to software development practitioners worldwide. This survey data was used to identify factors related to agile SDM implementation. The factors that significantly .