PSoC 4: PSoC 4XX8 BLE 4.2 Family Datasheet

PRELIMINARYFunctional DefinitionCPU and Memory SubsystemCPUThe Cortex-M0 CPU in PSoC 4XX8 BLE 4.2 is part of the 32-bitMCU subsystem, which is optimized for low-power operationwith extensive clock gating. It mostly uses 16-bit instructions andexecutes a subset of the Thumb-2 instruction set. This enablesfully compatible binary upward migration of the code tohigher-performance processors such as Cortex-M3 and M4. TheCypress implementation includes a hardware multiplier thatprovides a 32-bit result in one cycle. It includes a nested vectoredinterrupt controller (NVIC) block with 32 interrupt inputs and awakeup interrupt controller (WIC). The WIC can wake theprocessor up from the Deep Sleep mode, allowing power to themain processor to be switched off when the chip is in the DeepSleep mode. The Cortex-M0 CPU provides a nonmaskableinterrupt (NMI) input, which is made available to the user whenit is not in use for system functions requested by the user.The CPU also includes an SWD interface, which is a 2-wire formof JTAG; the debug configuration used for PSoC 4XX8 BLE 4.2has four break-point (address) comparators and two watchpoint(data) comparators.FlashThe PSoC 4XX8 BLE 4.2 device has a flash module with either128 KB or 256 KB of flash memory, tightly coupled to the CPU toimprove average access times from the flash block. The flashblock is designed to deliver 2 wait-state (WS) access time at 48MHz and with 1-WS access time at 24 MHz. The flashaccelerator delivers 85% of single-cycle SRAM accessperformance on average. Part of the flash module can be usedto emulate EEPROM operation if required. Maximum erase andprogram time is 20 ms per row (256 bytes). This also applies tothe emulated EEPROM.SRAMSRAM memory is retained during Hibernate.SROMThe 8-KB supervisory ROM contains a library of executablefunctions for flash programming. These functions are accessedthrough supervisory calls (SVC) and enable in-systemprogramming of the flash memory.DMAA DMA engine, with eight channels, is provided that can do 32-bittransfers and has chainable ping-pong descriptors.System ResourcesPower SystemThe power system is described in detail in the section Power onpage 16. It provides an assurance that the voltage levels are asrequired for the respective modes, and can either delay the modeentry (on power-on reset (POR), for example) until voltage levelsare as required or generate resets (brownout detect (BOD)) orinterrupts when the power supply reaches a particular programmable level between 1.8 and 4.5 V (low voltage detect (LVD)).Document Number: 002-09848 Rev. *BPSoC 4: PSoC 4XX8 BLE 4.2Family DatasheetPSoC 4XX8 BLE 4.2 operates with a single external supply (1.71to 5.5 V without radio, and 1.9 V to 5.5 V with radio). The devicehas five different power modes; transitions between these modesare managed by the power system. PSoC 4XX8 BLE 4.2 providesSleep, Deep Sleep, Hibernate, and Stop low-power modes. Referto the Technical Reference Manual for more details.Clock SystemThe PSoC 4XX8 BLE 4.2 clock system is responsible forproviding clocks to all subsystems that require clocks and forswitching between different clock sources without glitching. Inaddition, the clock system ensures that no metastable conditionsoccur.The clock system for PSoC 4XX8 BLE 4.2 consists of the internalmain oscillator (IMO), the internal low-speed oscillator (ILO), the24-MHz external crystal oscillator (ECO) and the 32-kHz watchcrystal oscillator (WCO). In addition, an external clock may besupplied from a pin.IMO Clock SourceThe IMO is the primary source of internal clocking in PSoC 4XX8BLE 4.2. It is trimmed during testing to achieve the specifiedaccuracy. Trim values are stored in nonvolatile latches (NVL).Additional trim settings from flash can be used to compensate forchanges. The IMO default frequency is 24 MHz and it can beadjusted between 3 to 48 MHz in steps of 1 MHz. The IMOtolerance with Cypress-provided calibration settings is 2%.ILO Clock SourceThe ILO is a very low-power oscillator, which is primarily used togenerate clocks for the peripheral operation in the Deep Sleepmode. ILO-driven counters can be calibrated to the IMO toimprove accuracy. Cypress provides a software component,which does the calibration.External Crystal Oscillator (ECO)The ECO is used as the active clock for the BLE subsystem tomeet the 50-ppm clock accuracy of the Bluetooth 4.2Specification. PSoC 4XX8 BLE 4.2 includes a tunable loadcapacitor to tune the crystal clock frequency by measuring theactual clock frequency. The high-accuracy ECO clock can alsobe used as a system clock.Watch Crystal Oscillator (WCO)The WCO is used as the sleep clock for the BLE subsystem tomeet the 500-ppm clock accuracy for the Bluetooth 4.2Specification. The sleep clock provides an accurate sleep timingand enables wakeup at the specified advertisement andconnection intervals. The WCO output can be used to realize thereal-time clock (RTC) function in firmware.Watchdog TimerA watchdog timer is implemented in the clock block running fromthe ILO or from the WCO; this allows the watchdog operationduring Deep Sleep and generates a watchdog reset if notserviced before the timeout occurs. The watchdog reset isrecorded in the Reset Cause register. With the WCO andfirmware, an accurate real-time clock (within the bounds of the32-kHz crystal accuracy) can be realized.Page 5 of 47

PRELIMINARYFigure 3. PSoC 4XX8 BLE 4.2 MCU Clocking ArchitectureECOHFCLKDivider/2n (n 0.3)IMOPrescalerDivider 0(/16)SYSCLKPER 0 CLKEXTCLKDivider 9(/16)FractionalDivider 0(/16.5)WCOFractionalDivider 1(/16.5)ILOPER15 CLKLFCLKThe HFCLK signal can be divided down (see Figure 3) togenerate synchronous clocks for the UDBs, and the analog anddigital peripherals. There are a total of 12 clock dividers forPSoC 4XX8 BLE 4.2: ten with 16-bit divide capability and twowith 16.5-bit divide capability. This allows the generation of 16divided clock signals, which can be used by peripheral blocks.The analog clock leads the digital clocks to allow analog eventsto occur before the digital clock-related noise is generated. The16-bit and 16.5-bit dividers allow a lot of flexibility in generatingfine-grained frequency values and are fully supported in PSoCCreator.ResetPSoC 4XX8 BLE 4.2 device can be reset from a variety ofsources including a software reset. Reset events areasynchronous and guarantee reversion to a known state. Thereset cause is recorded in a register, which is sticky throughresets and allows the software to determine the cause of thereset. An XRES pin is reserved for an external reset to avoidcomplications with the configuration and multiple pin functionsduring power-on or reconfiguration. The XRES pin has aninternal pull-up resistor that is always enabled.Voltage ReferenceThe PSoC 4XX8 BLE 4.2 reference system generates all internally required references. A one-percent voltage reference specis provided for the 12-bit ADC. To allow better signal-to-noiseratios (SNR) and better absolute accuracy, it is possible tobypass the internal reference using a GPIO pin or use anexternal reference for the SAR. Refer to Table 19, “SAR ADC ACSpecifications,” on page 26 for details.Document Number: 002-09848 Rev. *BPSoC 4: PSoC 4XX8 BLE 4.2Family DatasheetBLE Radio and SubsystemPSoC 4XX8 BLE 4.2 incorporates a Bluetooth Smart subsystemthat contains the Physical Layer (PHY) and Link Layer (LL)engines with an embedded AES-128 security engine. Thephysical layer consists of the digital PHY and the RF transceiverthat transmits and receives GFSK packets at 1 Mbps over a2.4-GHz ISM band, which is compliant with Bluetooth SmartBluetooth Specification 4.2. The baseband controller is acomposite hardware and firmware implementation that supportsboth master and slave modes. Key protocol elements, such asHCI and link control, are implemented in firmware. Time-criticalfunctional blocks, such as encryption, CRC, data whitening, andaccess code correlation, are implemented in hardware (in the LLengine).The RF transceiver contains an integrated balun, which providesa single-ended RF port pin to drive a 50-Ω antenna via amatching/filtering network. In the receive direction, this blockconverts the RF signal from the antenna to a digital bit streamafter performing GFSK demodulation. In the transmit direction,this block performs GFSK modulation and then converts a digitalbaseband signal to a radio frequency before transmitting it to airthrough the antenna.The Bluetooth Smart Radio and Subsystem (BLESS) requires a1.9-V minimum supply (the range varies from 1.9 V to 5.5 V).Key features of BLESS are as follows:Master and slave single-mode protocol stack with logical linkcontrol and adaptation protocol (L2CAP), attribute (ATT), andsecurity manager (SM) protocols API access to generic attribute profile (GATT), generic accessprofile (GAP), and L2CAP L2CAP connection-oriented channel GAP features Broadcaster, Observer, Peripheral, and Central roles Security mode 1: Level 1, 2, 3, and 4 Security mode 2: Level 1 and 2 User-defined advertising data Multiple bond support GATT features GATT client and server Supports GATT sub-procedures 32-bit universally unique identifier (UUID) Security Manager (SM) Pairing methods: Just works, Passkey Entry, Out of Band andNumeric Comparison Authenticated man-in-the-middle (MITM) protection and datasigning LE Secure Connections (Bluetooth 4.2 feature) Link Layer (LL) Master and Slave roles 128-bit AES engine Encryption Low-duty cycle advertising LE Ping LE Data Packet Length Extension (Bluetooth 4.2 feature) Link Layer Privacy (with extended scanning filter policy, Bluetooth 4.2 feature) Supports all SIG-adopted BLE profiles Page 6 of 47

PSoC 4: PSoC 4XX8 BLE 4.2Family DatasheetPRELIMINARYThe SAR is connected to a fixed set of pins through an 8-inputsequencer. The sequencer cycles through the selected channelsautonomously (sequencer scan) and does so with zero switchingoverhead (that is, the aggregate sampling bandwidth is equal to1 Msps whether it is for a single channel or distributed overseveral channels). The sequencer switching is effected througha state machine or through firmware-driven switching. A featureprovided by the sequencer is the buffering of each channel toreduce CPU interrupt-service requirements. To accommodatesignals with varying source impedances and frequencies, it ispossible to have different sample times programmable for eachchannel. Also, the signal range specification through a pair ofrange registers (low and high range values) is implemented witha corresponding out-of-range interrupt if the digitized valueexceeds the programmed range; this allows fast detection ofout-of-range values without having to wait for a sequencer scanto be completed and the CPU to read the values and check forout-of-range values in software.Analog Blocks12-bit SAR ADCThe 12-bit, 1-Msps SAR ADC can operate at a maximum clockrate of 18 MHz and requires a minimum of 18 clocks at thatfrequency to do a 12-bit conversion (up to 806 Ksps for thePSoC 41X8 BLE derivatives).The block functionality is augmented for the user by adding areference buffer to it (trimmable to 1%) and by providing thechoice of three internal voltage references, VDD, VDD/2, andVREF (nominally 1.024 V), as well as an external referencethrough a GPIO pin. The Sample-and-Hold (S/H) aperture isprogrammable; it allows the gain bandwidth requirements of theamplifier driving the SAR inputs, which determine its settlingtime, to be relaxed if required. System performance will be 65 dBfor true 12-bit precision provided appropriate references areused and system noise levels permit it. To improve the performance in noisy conditions, it is possible to provide an externalbypass (through a fixed pin location) for the internal referenceamplifier.The SAR is able to digitize the output of the on-chip temperaturesensor for calibration and other temperature-dependentfunctions. The SAR is not available in Deep Sleep and Hibernatemodes as it requires a high-speed clock (up to 18 MHz). TheSAR operating range is 1.71 to 5.5 V.Figure 4. SAR ADC System DiagramAHB System Bus and Programmable LogicInterconnectSAR Sequencervminus vplusData andStatus al )ReferenceSelectionP7Port 3 (8 inputs)SARMUXP0Sequencingand ControlVDD/2VDDDVREFInputs from other PortsOpamps (CTBm Block)PSoC 42X8 BLE has four opamps with Comparator modes,which allow most common analog functions to be performedon-chip, eliminating external components. PGAs, voltagebuffers, filters, transimpedance amplifiers, and other functionscan be realized with external passives saving power, cost, andspace. The on-chip opamps are designed with enoughbandwidth to drive the sample-and-hold circuit of the ADCwithout requiring external buffering.Temperature SensorPSoC 4XX8 BLE 4.2 has an on-chip temperature sensor. Thisconsists of a diode, which is biased by a current source that canbe disabled to save power. The temperature sensor is connectedDocument Number: 002-09848 Rev. *Bto the ADC, which digitizes the reading and produces a temperature value by using a Cypress-supplied software that includescalibration and linearization.Low-Power ComparatorsPSoC 4XX8 BLE 4.2 has a pair of low-power comparators, whichcan also operate in Deep Sleep and Hibernate modes. Thisallows the analog system blocks to be disabled while retainingthe ability to monitor external voltage levels during low-powermodes. The comparator outputs are normally synchronized toavoid metastability unless operating in an asynchronous powermode (Hibernate) where the system wake-up circuit is activatedby a comparator-switch event.Page 7 of 47

PSoC 4: PSoC 4XX8 BLE 4.2Family DatasheetPRELIMINARYUDBs can be clocked from a clock-divider block, from a portinterface (required for peripherals such as SPI), and from the DSInetwork directly or after synchronization.Programmable DigitalUniversal Digital Blocks (UDBs) and Port InterfacesThe PSoC 4XX8 BLE 4.2 has four UDBs; the UDB array alsoprovides a switched Digital System Interconnect (DSI) fabric thatallows signals from peripherals and ports to be routed to andthrough the UDBs for communication and control.A port interface is defined, which acts as a register that can beclocked with the same source as the PLDs inside the UDB array.This allows a faster operation because the inputs and outputscan be registered at the port interface close to the I/O pins andat the edge of the array. The port interface registers can beclocked by one of the I/Os from the same port. This allowsinterfaces such as SPI to operate at higher clock speeds byeliminating the delay for the port input to be routed over DSI andused to register other inputs (see Figure 6).Figure 5. UDB ArrayS y s te mIn te rc o n n e c tCPUS u b -s y s te mC lo c k s8 to 3 24 to 8High-Speed I/O MatrixU D B IFB U S IFOther DigitalSignals in ChipR o u tin gC h a n n e lsC L K IFIR Q IFDSIPPoPrtIFIFoortrtIFDSIUDBUDBUDBUDBDSIDSIP ro g ra m m a b le D ig ita l S u b sy s te mFigure 6. Port InterfaceHigh Speed I/O MatrixTo ClockTree8Input Registers7DigitalGlobalClocks3 DSI Signals ,1 I/O Signal6Clock SelectorBlock fromUDB06.To DSI03210[1]48[1][0]2Enables[1]8Reset SelectorBlock fromUDB7[0]24Output Registers.9488From DSI[1]From DSIUDBs can generate interrupts (one UDB at a time) to the interrupt controller. UDBs retain the ability to connect to any pin on the chipthrough the DSI.Document Number: 002-09848 Rev. *BPage 8 of 47

PRELIMINARYFixed-Function DigitalTimer/Counter/PWM BlockThe timer/counter/PWM block consists of four 16-bit counterswith user-programmable period length. There is a Captureregister to record the count value at the time of an event (whichmay be an I/O event), a period register which is used to eitherstop or auto-reload the counter when its count is equal to theperiod register, and compare registers to generate comparevalue signals which are used as PWM duty cycle outputs. Theblock also provides true and complementary outputs withprogrammable offset between them to allow the use asdeadband programmable complementary PWM outputs. It alsohas a Kill input to force outputs to a predetermined state; forexample, this is used in motor-drive systems when anovercurrent state is indicated and the PWMs driving the FETsneed to be shut off immediately with no time for softwareintervention.Serial Communication Blocks (SCB)PSoC 4XX8 BLE 4.2 has two SCBs, each of which canimplement an I2C, UART, or SPI interface.I2C Mode: The hardware I2C block implements a fullmulti-master and slave interface (it is capable of multimasterarbitration). This block is capable of operating at speeds of up to1 Mbps (Fast Mode Plus) and has flexible buffering options toreduce the interrupt overhead and latency for the CPU. It alsosupports EzI2C that creates a mailbox address range in thememory of PSoC 4XX8 BLE 4.2 and effectively reduces the I2Ccommunication to reading from and writing to an array in thememory. In addition, the block supports an 8-deep FIFO forreceive and transmit, which, by increasing the time given for theCPU to read the data, greatly reduces the need for clockstretching caused by the CPU not having read the data on time.The FIFO mode is available in all channels and is very useful inthe absence of DMA.The I2C peripheral is compatible with I2C Standard-mode,Fast-mode, and Fast-Mode Plus devices as defined in the NXPI2C-bus specification and user manual (UM10204). The I2C busI/O is implemented with GPIO in open-drain modes.SCB1 is fully compliant with Standard mode (100 kHz), Fastmode (400 kHz), and Fast-Mode Plus (1 MHz) I2C signalingspecifications when routed to GPIO pins P5[0] and P5[1], exceptfor hot

PSoC 4: PSoC 4XX8 BLE 4.2 Family Datasheet Document Number: 002-09848 Rev. *B Page 5 of 47 Functional Definition CPU and Memory Subsystem CPU The Cortex-M0 CPU in PSoC 4XX8 BLE 4.2 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extens