NCP81295 - Hot Swap Smart Fuse

NCP81295, NCP81296Table 6. ELECTRICAL CHARACTERISTICS (VINx VINF 12.0 V, VON 3.3 V, CVINF 0.1 mF, CVDD 4.7 mF, CVTEMP 0.1 mF,RVTEMP 1 kW, CSS 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range 40 C TA TJ 125 Cunless noted otherwise, and are guaranteed by design and characterization through statistical correlation.ParameterSymbolTest ConditionsMinTypMaxUnitsIMON/CS OUTPUTIMON or CS Current(single EFuse)Based on 10 mA/A 5 mAIIMON/ICSAccuracy (single EFuse)TJ 0 to 85 CTJ 0 to 85 CIMON or CS Current SourceClamp VoltageVIM CLMP/VCS CLMPPre Biased Offset CurrentLoad for Auto Zero Op AmpIAZ BIASIOUT 5 A (Note 8)55mAIOUT 10 A (Note 8)105mAIOUT 25 A (Note 8)255mAIOUT 50 A (Note 8)505mAIOUT 5 A (Note 8) 6 6%IOUT 10 A (Note 8) 4 4%IOUT 25 A (Note 8) 4 4%IOUT 50 A (Note 8) 4 4%Max pullup voltage of current source3.0V5.0mACURRENT LIMIT & CLREF PINCurrent Limit VoltageVCL THIf VCS VCL TH current limiting regulationoccurs via gate9598101%VCLREFCurrent Limit Enact OffsetVoltageVENACT0.2 V VCLREF 1.4 V 70 2412mVCurrent Limit Clamp VoltageVCL LOVOUT 40% VIN, VCLREF 0.15 V135152165mVVCL HI40% VIN VOUT 80% VINVCLREF 0.5 V480504520mVMax Current Limit ReferenceVoltageVCL MXVOUT 80% VIN, VCLREF 1.6 V1.551.61.65VResponse Time (Note 8)tCL REGVCS VCLREF until current limiting10.4mACLREF Bias CurrentCLREF Current SourceClamp VoltageFET Turn off TimerICLVCL CLMPtCL LAFrom pin into a 1.2 V source2009.610msMax pullup voltage of current source3.0VDelay between current limit detection and FETturn off (GOK 0)250msD OC OUTPUTOvercurrent ThresholdVOC THIf VCS VOC TH D OC pin pulls lowOutput Low VoltageVOL DOCIDOC 1 mA838690%VCLREF0.1VOff state Leakage CurrentILK DOCVDOC 5 V 1.0mADelay (rising) (Note 8)VCS limit until D OC rising 1.0msDelay (falling) (Note 8)VCS limit until D OC falling 1.0msProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.8. Guaranteed by design or characterization data. Not tested in production.www.onsemi.com11

NCP81295, NCP81296Table 6. ELECTRICAL CHARACTERISTICS (VINx VINF 12.0 V, VON 3.3 V, CVINF 0.1 mF, CVDD 4.7 mF, CVTEMP 0.1 mF,RVTEMP 1 kW, CSS 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range 40 C TA TJ 125 Cunless noted otherwise, and are guaranteed by design and characterization through statistical correlation.ParameterSymbolTest ConditionsMinTypMaxUnitsSHORT CIRCUIT PROTECTIONCurrent Threshold (Note 8)ISCResponse Time (Note 8)tSCNCP81295100ANCP8129680AFrom IOUT ILIMSC until gate pulldown500nsVVTEMP25At 25 C450mVGain (Note 8)AVTEMP0 C10mV/ CLoad CapabilityRVTEMPAt 25 C1kWPulldown CurrentIVTEMPAt 25 C50mATTSDGOK pulls dow140 COn ResistanceRDSonTJ 25 C0.65Off state leakage currentIDSoffVIN 16 V, VON 1.2 V, TJ 25 CVTEMP OUTPUTBias Voltage TJ 125 CTHERMAL SHUTDOWNTemperature Shutdown(Note 8)OUTPUT SWITCH (FET)1.0mW1.0mAFAULT detectionVDS Short ThresholdVDS THStartup postponed if VOUT VDS TH at VON VSWON transition88.8%VINVDS Short OK ThresholdVDS OKStartup resumed if VOUT VDS OK anytimeafter postponed68.6%VINVGD Short ThresholdVDG THStartup postponed if VG VDG TH at VON VSWON transition3.1VVGD Short OK ThresholdVDG OKStartup resumed if VG VDG OK anytime after postponed3.0VVG THLatch/Restart if VGD VG TH after tSSF ENDor tGATE FLT5.4VVG Low ThresholdVOUT Low ThresholdVOUTL THLatch/Restart if VOUT VOUTL TH aftertSSF END90%VINGate Fault Timer (Note 8)tGATE FLTTime from VGD VG TH transition aftertSSF END completed200msStartup Timer Failsafe(Note 8)tSSF ENDTime from VON VSWON transition,Max programmable softstart time200msDelay from power down to retry of startup1000msAUTO RETRY (NCP81296)Auto Retry DelaytDLY RETRYProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.8. Guaranteed by design or characterization data. Not tested in production.www.onsemi.com12

NCP81295, NCP81296TYPICAL CHARACTERISTICS600600500500400400Imon (mA)Ics (mA)Test Conditions: Vin 12 V, Rcs 2 kW, Css 200 nF, RCLREF 121 kW, RIMON 2 kW30020020010010000102030405006020304050Figure 9. Ics vs. Load CurrentFigure 10. Imon vs. Load Current6060050 A50 A500400Imon (mA)400Ics (mA)10LOAD CURRENT (A)50030 A3002001000 500LOAD CURRENT (A)60030 A300200100 2502550751001250 50150 250255075100TEMPERATURE ( C)TEMPERATURE ( C)Figure 11. Ics vs. TemperatureFigure 12. Imon vs. Temperature1.016000.914000.81251501200Vtemp (mV)0.7RDS(on) (mW)3000.60.50.40.310008006004000.20.10 60 40 20200020406080100 120 1400 60 40 20020406080100 120 140TEMPERATURE ( C)TEMPERATURE ( C)Figure 13. Output Switch RDS(on) @ 22 A vs.TemperatureFigure 14. Vtemp vs. Temperature (no load)www.onsemi.com13

NCP81295, NCP81296TYPICAL CHARACTERISTICSTest Conditions: Vin 12 V, Rcs 2 kW, Css 200 nF, RCLREF 121 kW, RIMON 2 kW2500 12000POWER LOSS (mW)OFF STATE LEAKAGE (mA)0 2 3 41500Power Loss1000500 5 6 60 40 200402060800100 120 14001030205040TEMPERATURE ( C)OUTPUT CURRENT (A)Figure 15. Output Switch Off state Leakagevs. TemperatureFigure 16. Power Loss vs. Load Current60ID, DRAIN CURRENT (A)1000100100 ms250 ms101 ms10.10.0110 ms100 ms1sRDS(ON) LimitSingle PulseRqJA 24.8 C/WTA 25 C0.110 sDotted Lines: Measured SOASolid Lines: Calculated SOA10120VDS, DRAIN SOURCE VOLTAGE (V)Figure 17. Internal FET’s Safe Operating Area (SOA)10k200POWER (W)250POWER (W)100k1kTA 25 C10010.00001 0.0001 0.0010.010.1100TA 25 C50TA 85 C10150TA 85 C1.01010000.011k0.20.30.40.50.60.70.80.90.1PULSE WIDTH (s)PULSE WIDTH (s)Figure 18. Single Pulse Power Rating (10 ms 1000 s, Junction to Ambient, Note 4)Figure 19. Single Pulse Power Rating (10 ms 100 ms, Junction to Ambient, Note 4)www.onsemi.com14

NCP81295, NCP81296TYPICAL CHARACTERISTICSTest Conditions: Vin 12 V, Rcs 2 kW, Css 200 nF, RCLREF 121 kW, RIMON 2 kWFigure 20. Start Up by VIN (Iout 0 A)Figure 21. Shut Down by VIN (Iout 0 A)Figure 22. Start Up by VIN (Iout 15 A)Figure 23. Shut Down by VIN (Iout 15 A)Figure 24. Start Up by EN (Iout 0 A)Figure 25. Shut Down by EN (Iout 0 A)www.onsemi.com15

NCP81295, NCP81296TYPICAL CHARACTERISTICSTest Conditions: Vin 12 V, Rcs 2 kW, Css 200 nF, RCLREF 121 kW, RIMON 2 kWFigure 26. Start Up by EN (Iout 15 A)Figure 27. Shut Down by EN (Iout 15 A)Figure 28. Short Circuit during NormalOperation (Iout 0 A)Figure 29. Short Circuit during NormalOperation (Iout 50 A)Figure 30. Short FET’s Gate During NormalOperation (Iout 2.5 A)Figure 31. DOC Index for Current Limit duringNormal Operation (Iout 51.8 A)www.onsemi.com16

NCP81295, NCP81296TYPICAL CHARACTERISTICSTest Conditions: Vin 12 V, Rcs 2 kW, Css 200 nF, RCLREF 121 kW, RIMON 2 kWFigure 32. OCP during NormalOperation(Iout 60.2A)Figure 33. OCP during Power Up by Enablewww.onsemi.com17

NCP81295, NCP81296General InformationThe NCP81295/6 is an N channel MOSFETco packaged with a smart hotswap controller. It is suited forhigh side current limiting and fusing in hot swapapplications. It can be used either alone, or in a paralellconfiguration for higher current applications.VDD Output (Auxiliary Regulated Supply)An internal linear regulator draws current from the VINFpin to produce and regulate voltage at the VDD pin. Thisauxiliary output supply is current limited to IDD CL. Aceramic capacitor in the range of 2.2 mF to 10 mF must beplaced between the VDD and GND pins, as close to theNCP81295/6 as possible. The voltage difference betweenVIN and VINF pin voltage should be within 0.4 V for betterCS/IMON performance. Small time constant R/C filter suchas 1 W/0.1 mF on the VINF pin is recommended.tSS (ms)CSS (nF)tSS (ms)CSS 470The maximum load capacitor value NCP81295/6 canpower up depends on the device soft start time. WhenVIN 12 V, RCS 2 kW, RLOAD 2.4 W, their relationshipfor different paralleled operations are shown as below chart(above line device shuts down safely due to protection,below line device powers up successfully without triggerprotection):ON Input (Device Enable)When the ON pin voltage (VON) is higher than VSWON,and no undervoltage (UVLO) or output switch faults arepresent, the output switch turns on. When VON is lower thanVSWOFF, the output switch is off. If VON is between VPDOFFand VSWOFF for longer than tPD DEL, the output switchesoff, and a pulldown resistance to ground, of RPD, is appliedto VOUT. In other words, there is behavior as follows: When VON 0.8 V, FET turns off. When 0.8 V VON 1.2 V, VOUT will discharge with 15 mA. When VON 1.2 V, FET turns on.For standalone applications, the ON pin sources currentION, which can be used to delay output switch turn on forsome time after the appearance of input voltage byconnecting a capacitor from the ON pin to ground.A bi level control signal driving to ground can be biasedup with a resistive divider to produce ON input levelsbetween VPDOFF VON VSWON and VON VSWON inorder to always apply the output pulldown when the outputswitch is off.GOK Output (Gate OK)The GOK pin is an open drain output that is pulled low toreport the fault under the following conditions: VDD voltage is below UVLO voltage at any time. VON disabled and VDS OK is false(indicates a short from VIN to VOUT). VON disabled and VDG OK is false(indicates a short from GATE to VIN). VON enabled and VSS OK is false at tSSF END(indicates VOUT 90% after soft start completes FET latches off for NCP81295/auto retries forNCP81296). VON enabled and VG is below VG TH at tSSF END(indicates leakage on GATE in startup – FET latches offfor NCP81295/auto retries for NCP81296). VON enabled and VG is below VG TH after tGATE FLT(indicates leakage on GATE during normal operation– FET latches off for NCP81295/auto retries forNCP81296). VON enabled and a current limiting condition lastslonger than tOC LA(FET latches off for NCP81295/auto retries forNCP81296).SS Output (Soft Start)When the output switch first turns on, it does so in acontrolled manner. The output voltage (VOUT) follows thevoltage at the SS pin, produced by current ISS into a capacitorfrom SS to ground. The duration of soft start can beprogrammed by selection of the capacitor value. In parallelfuse applications, the SS pins of all fuses should be shortedtogether to one shared SS capacitor. Internal soft start loadbalancing circuity will ensure the soft start current is sharedbetween paralleled devices, so as not to stress one devicemore than another or hit a soft start current limit.The soft start capacitor value can be calculated by:CSS (tSS * ISS * AVSS)/VIN (where tSS is the targetsoft start time). The recommended range of tSS is 10 100 ms (see Table 5).The typical CSS values for different tSS are listed below:www.onsemi.com18

NCP81295, NCP81296 VON enabled and device temperature is above TTSDDuring startup (VON VSWON for less than tSS END), thecurrent limit reference voltage is clamped according to thefollowing: When VOUT 40% of VIN, VCL TH VCL LO orVCLREF (whichever is lower). When VOUT is between 40% and 80% of VIN,VCL TH VCL HI or VCLREF (whichever is lower). When VOUT exceeds 80% of VIN, VCL TH VCL MXor VCLREF (whichever is lower).(indicates an over temperature is detected FETlatches off for NCP81295/auto retries for NCP81296).Usually GOK can’t be used as power good to indicate theoutput voltage is in the normal range. Bringing VDD belowthe UVLO voltage is required to release a latching condition.IMON Output (Current Monitor)The IMON pin sources a current that is AIMON (10 mA/A)times the VOUT output current and plus IAZ BIAS. A resistorconnected from the IMON pin to ground can be used tomonitor current information as a voltage up to VIM CLMP. Acapacitor of any value in parallel with the IMON resistor canbe used to low pass filter the IMON signal without affectingany internal operation of the device.If a current limiting condition exists anytime for acontinuous duration tCL LA, then the device latches off(NCP81295) or restarts (NCP81296).The CS pin must have no capacitive loading other thanparasitic device/board capacitance to function correctly. Therecommended range of RCS is 1.8 4 kW (see Table 5).CLREF Pin (Current Limit and Over Current Reference)CS AMP OFFSET BIASThe CLREF pin voltage determines the current limitregulation point and over current indication point via itsinteraction with the CS pin voltage. The CLREF voltage canbe applied by an external source, such as a hot swapcontroller or D to A converter, or developed across aprogramming resistor to ground by the CLREF bias current,ICL. The recommended range of CLREF voltage is 0.2 1.4 V (see Table 5).NCP81295/6 use an auto zero Op Amp with low inputoffset to sense current in FET with high accuracy, and anpre biased offset current load, IAZ BIAS is need for thisOp Amp to always keep it to maintain this low input offset( 100 mV). The internal IMON and CS current sourcefollow below relationship:CS Input/Output (Current Set)I OUT )VOC THENACTRCS* I AZ BIAS10 mI OUT I OUT )VCL THENACTRCS* I AZ BIAS10 mI MON * I AZ BIAS10 m(eq. 4)For typical 5 mA IAZ BIAS, there has 0.5 A positive off setin IOUT sense.D OC Output (Over current Indicator)The D OC pin is an open drain output that indicateswhen an over current condition exists after soft start iscomplete. When the voltage on the CS pin is higher thanVOC TH, D OC is pulled low. If output current drops belowVOC TH, the D OC pin is released and gets pulled high byan external pullup resistor.VTEMP Output (Temperature Indicator)VTEMP is a voltage output proportional to devicetemperature, with an offset voltage. The VTEMP output cansource much more current than it can sink, so that if multipleVTEMP outputs are connected together, the voltage of allVTEMP outputs will be driven to the voltage produced bythe hottest NCP81295/6. A 100 nF capacitor or greater mustbe connected from the VTEMP pin to ground.(eq. 1)The VOC TH trip point is based on a percentage of VCLREF(86%).During normal operation (VON VSWON for longer thantSS END), if the voltage on the CS pin is above VCL TH(VCL TH is clamped at VCL MX if VCL TH VCL MX), thenthe gate voltage of the FET is modulated to limit current intothe output based on the following formula:V(eq. 3)andThe CS pin is both an input and an output. The CS pinsources a current that is ACS (10 mA/A) times the VOUTcurrent and plus IAZ BIAS. This produces a voltage on the CSpin that is the product of the CS pin current and an externalCS pin resistance to ground.The voltage generated on VCS determines the D OCover current indicator trip point and the current limitregulation point, via its interaction with the voltage onCLREF pin.When the voltage on the CS pin is higher than VOC TH ,D OC is pulled low. If the CS pin voltage drops belowVOC TH, the D OC pin is released to and gets pulled high bythe external pullup resistor. D OC transitions based on thefollowing formula:VI CS * I AZ BIAS10 mI OUT (eq. 2)The VCL TH regulation point is equal to VCLREF.www.onsemi.com19

NCP81295, NCP81296 VIN to VOUT short, non latching/non auto retryAuto Retry Restart (NCP81296)Under certain fault conditions, the FET is turned off andanother soft start procedure takes place. Between the faultand the new soft start, there is a delay of tDLY RETRY. Theprotection features that use this hiccup mode restart are: Over Current Short Circuit Detection Over Temperature Excessive Soft Start Duration Gate Leakage Protection FeaturesFor the following protection features, the FET eitherlatches off (NCP81295) or the FET turns off and initiates arestart (NCP81296), unless noted otherwise. Excessive Current LimitingIf a current limiting condition exists anytime for acontinuous duration tCL LA, then the FET latches/restarts.condition. If the device is disabled andVOUT VDS TH then GOK is pulled low and thedevice is prevented from powering up. The device isallowed to power up once VOUT VDS OK.GATE to VIN short, non latching/non auto retrycondition. If the device is disabled andGATE (Pin 8) VDG TH, then GOK is pulled low anddevice is prevented from powering up. The deviceallowed to power up once GATE VDG OK.GATE leakage startup.If (GATE – VINF) VG TH at tSSF END, then GOK ispulled low and FET latches/restarts.GATE leakage normal operation.If (GATE – VINF) VG TH for tGATE FLT time afterthe soft start timer completes, then GOK is pulled lowand device latches/restarts.FET SOA LimitsIf VOUT VOUTL TH when tSSF END expires, then theFET latches/restarts.In built timed current limits and fault monitoring circuitsensure the copackaged FET is always kept within SOAlimits.Short Circuit DetectionMultiple Fuse Power UpExcessive Soft Start DurationWhen multiple NPC81295 are paralleled together asshown in Figure 4, the NPC81295s will turn on together.Keeping the current through each switch within 1 A (typical)helps to prevent overstress on each switching duringsoft start.Due to NCP81296 is featured by Auto Retry Modeprotection, please follow the below reference schematicof NCP81296 for paralleled operation.If switch current exceeds ISC, the device reacts within tSC,and the FET latches/restarts. The short circuit currentmonitor is independent of CS, CLREF, IMON and currentlimit setting (cannot be changed externally).Over Temperature ShutdownIf the FET controller temperature TTSD, then the FETlatches/restarts.FET Fault DetectionThe device contains various FET monitoring circuits:www.onsemi.com20

NCP81295, NCP81296When paralleled multiple NPC81295 encounter fault, the system can recover the E fuse by resetting their VDD with belowbuffer and reset circuit.www.onsemi.com21

NCP81295, NCP8129622nF22nFwww.onsemi.com22

MECHANICAL CASE OUTLINEPACKAGE DIMENSIONSLQFN32 5x5, 0.5PCASE 487AAISSUE ADATE 03 OCT 20171 32SCALE 2:1ABDÉÉÉÉÉÉÉÉÉPIN ONEREFERENCE0.10 C0.10 CDETAIL AALTERNATECONSTRUCTIONEÉÉÉÉÉÉÇÇÇTOP VIEWA1DETAIL B(A3)ALTERNATECONSTRUCTIONA0.05 CNOTE 4A1SIDE VIEWCSEATINGPLANEGENERICMARKING DIAGRAM*L2K9XXXXXXXXXXXXXXXXAWLYYWWGGDETAIL C1732XL2MILLIMETERSMINMAX1.201.40 0.050.20 REF0.180.305.00 BSC3.303.505.00 BSC3.303.500.50 BSC0.300.500.13 REF1D2DETAIL ADIMAA1A3bDD2EE2eLL2A3DETAIL B0.10 CNOTES:1. DIMENSIONING AND TOLERANCING PERASME Y14.5M, 1994.2.

10 VIN10 Input of high current output switch 11 VIN11 Input of high current output switch 12 VIN12 Input of high current output switch 13 VIN13 Input of high current output switch 14 VIN14 Input of high current output switch 15 VIN15 Input of high current output switch 16 VIN16 Input of high current outp