DAC7554: 12-Bit, Quad, Ultralow Glitch, Voltage Output DAC .

2y ago
12 Views
2 Downloads
1.04 MB
20 Pages
Last View : 22d ago
Last Download : 2m ago
Upload by : Elisha Lemon
Transcription

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 200412-BIT, QUAD, ULTRALOW GLITCH, VOLTAGE OUTPUTDIGITAL-TO-ANALOG CONVERTERFEATURES DESCRIPTION2.7-V to 5.5-V Single Supply12-Bit Linearity and MonotonicityRail-to-Rail Voltage OutputSettling Time: 5 µs (Max)Ultralow Glitch Energy: 0.1 nVsUltralow Crosstalk: –100 dBLow Power: 880 µA (Max)Per-Channel Power Down: 2 µA (Max)Power-On Reset to Zero ScaleSPI-Compatible Serial Interface: Up to 50 MHzSimultaneous or Sequential UpdateSpecified Temperature Range: –40 C to 105 CSmall 10-Lead MSOP PackageThe DAC7554 is a quad-channel, voltage-output DACwith exceptional linearity and monotonicity. Its proprietary architecture minimizes undesired transientssuch as code to code glitch and channel to channelcrosstalk. The low-power DAC7554 operates from asingle 2.7-V to 5.5-V supply. The DAC7554 outputamplifiers can drive a 2-kΩ, 200-pF load rail-to-railwith 5-µs settling time; the output range is set usingan external voltage reference.The 3-wire serial interface operates at clock rates upto 50 MHz and is compatible with SPI, QSPI,Microwire, and DSP interface standards. The outputsof all DACs may be updated simultaneously orsequentially. The parts incorporate a power-on-resetcircuit to ensure that the DAC outputs power up tozero volts and remain there until a valid write cycle tothe device takes place. The parts contain apower-down feature that reduces the current consumption of the device to under 1 µA.APPLICATIONS Portable Battery-Powered InstrumentsDigital Gain and Offset AdjustmentProgrammable Voltage and Current SourcesProgrammable AttenuatorsIndustrial Process ControlThe small size and low-power operation makes theDAC7554 ideally suited for battery-operated portableapplications. The power consumption is typically 3.5mW at 5 V, 1.65 mW at 3 V, and reduces to 1 µW inpower-down mode.The DAC7554 is available in a 10-lead MSOP package and is specified over –40 C to 105 C.FUNCTIONAL BLOCK ingDAC ABufferVOUTAInputRegisterDACRegisterStringDAC BBufferVOUTBInputRegisterDACRegisterStringDAC CBufferVOUTCInputRegisterDACRegisterStringDAC ower-DownLogicGNDPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.Copyright 2004, Texas Instruments Incorporated

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integratedcircuits be handled with appropriate precautions. Failure to observe proper handling and installationprocedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precisionintegrated circuits may be more susceptible to damage because very small parametric changes couldcause the device not to meet its published specifications.ORDERING DTEMPERATURERANGEPACKAGEMARKINGDAC755410 MSOPDGS–40 C TO 105 ce TubeDAC7554IDGSR2500-piece Tapeand ReelABSOLUTE MAXIMUM RATINGSover operating free-air temperature range (unless otherwise noted) (1)UNITVDD to GND–0.3 V to 6 VDigital input voltage to GND–0.3 V to VDD 0.3 VVout to GND–0.3 V to VDD 0.3 VOperating temperature range–40 C to 105 CStorage temperature range–65 C to 150 CJunction temperature (TJ Max)(1)2150 CStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may affect device reliability.

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004ELECTRICAL CHARACTERISTICSVDD 2.7 V to 5.5 V, REFIN VDD, RL 2 kΩ to GND; CL 200 pF to GND; all specifications –40 C to 105 C, unlessotherwise specifiedPARAMETERTEST CONDITIONSMINTYPMAXUNITSSTATIC PERFORMANCE (1)Resolution12Relative accuracyDifferential nonlinearitySpecified monotonic by design 1LSB 0.08 0.5LSB 12mVOffset errorZero-scale errorBits 0.35 12All zeroes loaded to DAC registerGain errorFull-scale errormV 0.15%FSR 0.5%FSRZero-scale error drift7µV/ CGain temperature coefficient3ppm of FSR/ CPSRROUTPUTVDD 5 V0.75mV/VCHARACTERISTICS (2)Output voltage rangeOutput voltage settling time0RL 2 kΩ; 0 pF CL 200 pFSlew rateREFINV5µs1Capacitive load stabilityRL 470RL 2 kΩDigital-to-analog glitch impulse1 LSB change around major carryChannel-to-channel crosstalk1-kHz full-scale sine wave, outputs unloadedV/µspF10000.1nV-s–100dBDigital feedthrough0.1nV-sOutput noise density (10-kHz offset frequency)70nV/rtHz–85dBTotal harmonic distortionFOUT 1 kHz, FS 1 MSPS, BW 20 kHz1ΩVDD 5 V50mAVDD 3 V20Coming out of power-down mode, VDD 5 V15Coming out of power-down mode, VDD 3 V15DC output impedanceShort-circuit currentPower-up timeµsLOGIC INPUTS (2) 1µA0.3 VDDV3pF5.5V700880µA5508300.220.052Input currentVIN L, Input low voltageVDD 5 VVIN H, Input high voltageVDD 3 V0.7 VDDVPin capacitancePOWER REQUIREMENTSVDD2.7IDD(normal operation)VDD 3.6 V to 5.5 VDAC active and excluding load currentVIH VDD and VIL GNDVDD 2.7 V to 3.6 VIDD (all power-down modes)VDD 3.6 V to 5.5 VVIH VDD and VIL GNDVDD 2.7 V to 3.6 VReference input impedance25µAkΩPOWER EFFICIENCYIOUT/IDD(1)(2)ILOAD 2 mA, VDD 5 V93%Linearity tested using a reduced code range of 48 to 4048; output unloaded.Specified by design and characterization, not production tested.3

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TIMING CHARACTERISTICS (1) (2)VDD 2.7 V to 5.5 V, RL 2 kΩ to GND; all specifications –40 C to 105 C, unless otherwise specifiedPARAMETERTEST CONDITIONSt1 (3)SCLK cycle timet2SCLK HIGH timet3SCLK LOW timet4SYNC falling edge to SCLK falling edge setuptimet5Data setup timet6Data hold timet7SCLK falling edge to SYNC rising edget8Minimum SYNC HIGH time(1)(2)(3)MINVDD 2.7 V to 3.6 V20VDD 3.6 V to 5.5 V20VDD 2.7 V to 3.6 V10VDD 3.6 V to 5.5 V10VDD 2.7 V to 3.6 V10VDD 3.6 V to 5.5 V10VDD 2.7 V to 3.6 V4VDD 3.6 V to 5.5 V4VDD 2.7 V to 3.6 V5VDD 3.6 V to 5.5 V5VDD 2.7 V to 3.6 V4.5VDD 3.6 V to 5.5 V4.5VDD 2.7 V to 3.6 V0VDD 3.6 V to 5.5 V0VDD 2.7 V to 3.6 V20VDD 3.6 V to 5.5 V20All input signals are specified with tR tF 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL VIH)/2.See Serial Write Operation timing diagram Figure 1.Maximum SCLK frequency is 50 MHz at VDD 2.7 V to 5.5 Figure 1. Serial Write Operation4TYPXMAXUNITSnsnsnsnsnsnsnsns

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004PIN DESCRIPTIONDGS Package(Top DDINSCLKTerminal FunctionsTERMINALNO.DESCRIPTIONNAME1VOUTAAnalog output voltage from DAC A2VOUTBAnalog output voltage from DAC B3GNDGround4VOUTCAnalog output voltage from DAC C5VOUTDAnalog output voltage from DAC D6SCLKSerial clock input7DINSerial data input8VDDAnalog voltage supply input9SYNCFrame synchronization input. The falling edge of the FS pulse indicates the start of a serial data frame shifted out tothe DAC755410REFINAnalog input. External reference5

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICSLINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODELINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODE11Channel BVDD 5 VLinearity Error LSBVREF 4.096 V0.50 0.5 0.5 1 10.50 0.25 0.505121024153620482560Digital Input Code307235840.250 0.25 0.504096153620482560Digital Input Code3072LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODELINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODE358440961VREF 4.096 VChannel DVDD 5 VLinearity Error LSBLinearity Error LSB1024Figure 3.Channel C0.50 0.5 1VREF 4.096 VVDD 5 V0.50 0.5 1Differential Linearity Error LSBDifferential Linearity Error LSB512Figure 2.10.50.250 0.250.50.250 0.25 0.50512102415362048Digital Input CodeFigure 4.6VDD 5 V00.50.25VREF 4.096 V0.5Differential Linearity Error LSBDifferential Linearity Error LSBLinearity Error LSBChannel A2560307235844096 0.505121024153620482560Digital Input CodeFigure 5.307235844096

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODELINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODE11VREF 2.5 VVDD 2.7 VLinearity Error LSBLinearity Error LSBChannel A0.50 0.50.50.250 0.25 0.505121024153620482560Digital Input Code307235844096 0.50.50.250 0.25 0.505121024153620482560Digital Input Code30723584LINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODELINEARITY ERROR ANDDIFFERENTIAL LINEARITY ERRORvsDIGITAL INPUT CODE40961Channel CVREF 2.5 VChannel DVDD 2.7 VLinearity Error LSBLinearity Error LSB0Figure 7.0.50 0.5 1VREF 2.5 VVDD 2.7 V0.50 0.5 1Differential Linearity Error LSBDifferential Linearity Error LSBVDD 2.7 VFigure 6.10.50.250 0.25 0.5VREF 2.5 V 1Differential Linearity Error LSBDifferential Linearity Error LSB 1Channel B0.505121024153620482560Digital Input CodeFigure 8.3072358440960.50.250 0.25 0.505121024153620482560307235844096Digital Input CodeFigure 9.7

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)ZERO-SCALE ERRORvsFREE-AIR TEMPERATUREZERO-SCALE ERRORvsFREE-AIR TEMPERATURE1010VDD 5 V,VREF 4.096 VVDD 2.7 V,VREF 2.5 VChannel C5Channel D0Channel BZero Scale Error mVZero Scale Error mVChannel AChannel A5Channel CChannel D0Channel B 5 40 102050 5 4080TA Free-Air Temperature C80Figure 11.FULL-SCALE ERRORvsFREE-AIR TEMPERATUREFULL-SCALE ERRORvsFREE-AIR TEMPERATURE5VDD 2.7 V,VREF 2.5 VChannel AChannel CChannel D0Channel B 5 10205080TA Free-Air Temperature CFigure 12.850Figure 10.VDD 5 V,VREF 4.096 V 10 4020TA Free-Air Temperature CChannel CChannel AFull Scale Error mVFull Scale Error mV5 10Channel D0Channel B 5 10 40 10205080TA Free-Air Temperature CFigure 13.

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)SINK CURRENT AT NEGATIVE RAILSOURCE CURRENT AT POSITIVE RAIL0.25.50Typical for All ChannelsVDD 2.7 V,Vref 2.5 V0.15VO Output Voltage VVO Output Voltage VTypical for All Channels0.1VDD 5.5 V,Vref 4.096 VVDD Vref 5.5 V5.405.300.05DAC Loaded with 000h00510ISINK Sink Current mADAC Loaded with FFFh5.20150510ISOURCE Source Current mAFigure 14.Figure 15.SOURCE CURRENT AT POSITIVE RAILSUPPLY CURRENTvsDIGITAL INPUT CODE157002.7Typical for All ChannelsI DD Supply Current µ AVO Output Voltage V6002.6VDD Vref 2.7 V2.5500VDD 5.5 V,Vref 4.096 VVDD 2.7 V,Vref 2.5 V400300200100All Channels Powered, No LoadDAC Loaded with FFFh2.40510ISOURCE Source Current mAFigure 16.1500512 1024 1536 2048 2560 3072 3584 4096Digital Input CodeFigure 17.9

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)SUPPLY CURRENTvsFREE-AIR TEMPERATURESUPPLY CURRENTvsSUPPLY VOLTAGE800700VDD 5.5 V,Vref 4.096 V600VDD 2.7 V,Vref 2.5 V500All DACs Powered,No Load,Vref 2.5 V650I DD Supply Current µ AI DD Supply Current µ A700400300200600550500450100All Channels Powered, No Load0 40 10205080TA Free-Air Temperature C4002.71103.84.14.54.85.25.5Figure 18.Figure 19.SUPPLY CURRENTvsLOGIC INPUT VOLTAGEHISTOGRAM OF CURRENT CONSUMPTION - 5.5 V2000VDD 5.5 V,Vref 4.096 VTA 25 C,SCL Input (All Other Inputs GND)18001500f Frequency HzI DD Supply Current µ A3.4VDD Supply Voltage V2200VDD 5.5 V,Vref 4.096 V140010001000500600VDD 2.7 V,Vref 2.5 V200001234VLOGIC Logic Input Voltage VFigure 20.103.15282 339 395 452 508 565 621 678 734 791IDD Current Consumption AFigure 21.

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)HISTOGRAM OF CURRENT CONSUMPTION - 2.7 VTOTAL ERROR - 5 V2000VDD 5 V,Vref 4.096 V,TA 25 CChannel B OutputVDD 2.7 V,Vref 2.5 V6Channel C Output4Total Error - mVf Frequency Hz15001000Channel A Output20 2500Channel D Output 40 60280 327 373 420 467 513 560 607 653 700IDD Current Consumption A6TOTAL ERROR - 2.7 VEXITING POWER-DOWN MODE5VDD 5 V,Vref 4.096 V,Power-Up Code 40004Channel C OutputChannel B Output0 2VO Output Voltage VTotal Error - mVFigure 23.Channel A Output21024 1536 2048 2560 3072 3584 4095Digital Input CodeFigure 22.VDD 2.7 V,Vref 2.5 V,TA 25 C4512321 4Channel D Output 605121024 1536 2048 2560 3072 3584 4095Digital Input CodeFigure 24.0t Time 4 s/divFigure 25.11

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)LARGE-SIGNAL SETTLING TIME - 5 VLARGE-SIGNAL SETTLING TIME - 2.7 V53Vref 2.5 VVDD 2.7 V,Output Loaded With 200 pF to GNDCode 41 to 4055VDD 5 V,Vref 4.096 VOutput Loaded With 200 pF to GNDCode 41 to 4055VO Output Voltage VVO Output Voltage V43221100t Time 5 s/divFigure 27.MIDSCALE GLITCHWORST-CASE GLITCHVO -VO -(5 mV/Div)(5 mV/Div)Figure 26.Trigger PulseTrigger PulseTime - (400 nS/Div)Figure 28.12t Time 5 s/divTime - (400 nS/Div)Figure 29.

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004TYPICAL CHARACTERISTICS (continued)CHANNEL-TO-CHANNEL CROSSTALKFOR A FULL-SCALE SWINGVO -VO -(5 mV/Div)(5 mV/Div)DIGITAL FEEDTHROUGH ERRORTrigger PulseTrigger PulseTime - (400 nS/Div)Time - (400 nS/Div)Figure 30.Figure 31.TOTAL HARMONIC DISTORTIONvsOUTPUT FREQUENCYTHD Total Harmonic Distortion dB 40VDD 5 V, Vref 4.096 V 1 dB FSR Digital Input, Fs 1 MspsMeasurement Bandwidth 20 kHz 50 60 70THD 802nd Harmonic 90 1003rd Harmonic012345678Output Frequency (Tone) kHz910Figure 32.13

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 20043-Wire Serial InterfaceThe DAC7554 digital interface is a standard 3-wire SPI/QSPI/Microwire/DSP-compatible interface.Table 1. Serial Interface ProgrammingCONTROL14DATA AC(s)FUNCTIONAInput register updateddataBInput register updateddataCInput register updated1dataDInput register updated00dataADAC register updated, output updated101dataBDAC register updated, output updated110dataCDAC register updated, output updated0111dataDDAC register updated, output updated1000dataAInput register and DAC register updated, output updated1001dataBInput register and DAC register updated, output updated1010dataCInput register and DAC register updated, output updated1011dataDInput register and DAC register updated, output updated1100dataA-DInput register updated1101dataA-DDAC register updated, output updated1110dataA-DInput register and DAC register updated, output updated11data--11Sel1Sel0Power-Down Mode - See Table 200Channel A01Channel B10Channel C11Channel DLD1LD0FUNCTION00Single channel store. The selected input register is updated.01Single channel DAC update. The selected DAC register is updated with input register information.10Single channel update. The selected input and DAC register is updated.11Depends on the Sel1 and Sel0 BitsCHANNEL SELECT

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004POWER-DOWN MODEIn power-down mode, the DAC outputs are programmed to one of three output impedances, 1 kΩ, 100 kΩ, orfloating.Table 2. Power-Down Mode ControlEXTENDED CONTROLDATA 111100000XPWD Hi-Z (selected channel A)111100001XPWD 1 kΩ (selected channel A)111100010XPWD 100 kΩ (selected channel A)111100011XPWD Hi-Z (selected channel A)111100100XPWD Hi-Z (selected channel B)111100101XPWD 1 kΩ (selected channel B)111100110XPWD 100 kΩ (selected channel B)111100111XPWD Hi-Z (selected channel B)111101000XPWD Hi-Z (selected channel C)111101001XPWD 1 kΩ (selected channel C)111101010XPWD 100 kΩ (selected channel C)111101011XPWD Hi-Z (selected channel C)111101100XPWD Hi-Z (selected channel D)111101101XPWD 1 kΩ (selected channel D)111101110XPWD 100 kΩ (selected channel D)111101111XPWD Hi-Z (selected channel D)11111XX00XPWD Hi-Z (all channels)11111XX01XPWD 1 kΩ (all channels)11111XX10XPWD 100 kΩ (all channels)1111XX11XPWD Hi-Z (all channels)1DB11ALL CHANNELS FLAG0See DB7–DB101DB10 and DB9 are Don't CareDB10DB900Channel SelectChannel A01Channel B10Channel C11Channel DDB8DB700Power-down Hi-Z01Power-down 1 kΩ10Power-down 100 kΩ11Power-down Hi-ZPower-Down Mode15

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004THEORY OF OPERATIOND/A SECTIONDAC External Reference InputThe architecture of the DAC7554 consists of a stringDAC followed by an output buffer amplifier. Figure 33shows a generalized block diagram of the DACarchitecture.There is a single reference input pin for the fourDACs. The reference input is unbuffered. The usercan have a reference voltage as low as 0.25 V andas high as VDD because there is no restriction due toheadroom and footroom of any reference amplifier.REFINRef Resistor StringRef DAC RegisterVOUT Power-On ResetGNDFigure 33. Typical DAC ArchitectureThe input coding to the DAC7554 is unsigned binary,which gives the ideal output voltage as:VOUT REFIN D/4096Where D decimal equivalent of the binary code thatis loaded to the DAC register which can range from 0to 4095.To OutputAmplifierREFINRRRIt is recommended to use a buffered reference in theexternal circuit (e.g., REF3140). The input impedanceis typically 25 kΩ.RGNDFigure 34. Typical Resistor StringOn power up, all internal registers are cleared and allchannels are updated with zero-scale voltages. Untilvalid data is written, all DAC outputs remain in thisstate. This is particularly useful in applications whereit is important to know the state of the DAC outputswhile the device is powering up. In order not to turnon ESD protection devices, VDD should be appliedbefore any other pin is brought high.Power DownThe DAC7554 has a flexible power-down capabilityas described in Table 2. Individual channels could bepowered down separately or all channels could bepowered down simultaneously. During a power-downcondition, the user has flexibility to select the outputimpedance of each channel. During power-downoperation, each channel can have either 1-kΩ,100-kΩ, or Hi-Z output impedance to ground.SERIAL INTERFACERESISTOR STRINGThe resistor string section is shown in Figure 34. It issimply a string of resistors, each of value R. Thedigital code loaded to the DAC register determines atwhich node on the string the voltage is tapped off tobe fed into the output amplifier. The voltage is tappedoff by closing one of the switches connecting thestring to the amplifier. Because it is a string ofresistors, it is specified monotonic. The DAC7554architecture uses four separate resistor strings tominimize channel-to-channel crosstalk.OUTPUT BUFFER AMPLIFIERSThe output buffer amplifier is capable of generatingrail-to-rail voltages on its output, which gives anoutput range of 0 V to VDD. It is capable of driving aload of 2 kΩ in parallel with up to 1000 pF to GND.The source and sink capabilities of the output amplifier can be seen in the typical curves. The slew rate is1 V/µs with a half-scale settling time of 3 µs with theoutput unloaded.16The DAC7554 is controlled over a versatile 3-wireserial interface, which operates at clock rates up to50 MHz and is compatible with SPI, QSPI, Microwire,and DSP interface standards.16-Bit Word and Input Shift RegisterThe input shift register is 16 bits wide. DAC data isloaded into the device as a 16-bit word under thecontrol of a serial clock input, SCLK, as shown in theFigure 1 timing diagram. The 16-bit word, illustratedin Table 1, consists of four control bits followed by 12bits of DAC data. The data format is straight binarywith all zeroes corresponding to 0-V output and allones corresponding to full-scale output (VREF – 1LSB). Data is loaded MSB first (Bit 15) where the firsttwo bits (LD1 and LD0) determine if the input register,DAC register, or both are updated with shift registerinput data. Bit 13 and bit 12 (Sel1 and Sel0)determine whether the data is for DAC A, DAC B,DAC C, DAC D, or all DACs. All channels areupdated when bits 15 and 14 (LD1 and LD0) arehigh.

DAC7554www.ti.comThe SYNC input is a level-triggered input that acts asa frame synchronization signal and chip enable. Datacan only be transferred into the device while SYNC islow. To start the serial data transfer, SYNC should betaken low, observing the minimum SYNC to SCLKfalling edge setup time, t4. After SYNC goes low,serial data is shifted into the device's input shiftregister on the falling edges of SCLK for 16 clockpulses. Any data and clock pulses after the sixteenthfalling edge of SCLK are ignored. No further serialdata transfer occurs until SYNC is taken high and lowagain.SYNC may be taken high after the falling edge of thesixteenth SCLK pulse, observing the minimum SCLKfalling edge to SYNC rising edge time, t7.After the end of serial data transfer, data is automatically transferred from the input shift register to theinput register of the selected DAC. If SYNC is takenhigh before the sixteenth falling edge of SCLK, thedata transfer is aborted and the DAC input registersare not updated.INTEGRAL AND DIFFERENTIAL LINEARITYThe DAC7554 uses precision thin-film resistors providing exceptional linearity and monotonicity. Integrallinearity error is typically within ( /-) 0.35 LSBs, anddifferential linearity error is typically within ( /-) 0.08LSBs.GLITCH ENERGYThe DAC7554 uses a proprietary architecture thatminimizes glitch energy. The code-to-code glitchesare so low, they are usually buried within thewide-band noise and cannot be easily detected. TheDAC7554 glitch is typically well under 0.1 nV-s. Suchlow glitch energy provides more than 10X improvement over industry alternatives.CHANNEL-TO-CHANNEL CROSSTALKThe DAC7554 architecture is designed to minimizechannel-to-channel crosstalk. The voltage change inone channel does not affect the voltage output inanother channel. The DC crosstalk is in the order of afew microvolts. AC crosstalk is also less than –100dBs. This provides orders of magnitude improvementover certain competing architectures.SLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004can exceed 1 MSPS if the waveform to be generatedconsists of small voltage steps between consecutiveDAC updates. To obtain a high dynamic range,REF3140 (4.096 V) or REF02 (5.0 V) are recommended for reference voltage generation.Generating 5-V, 10-V, and 12-V Outputs ForPrecision Industrial ControlIndustrial control applications can require multiplefeedback loops consisting of sensors, ADCs, MCUs,DACs, and actuators. Loop accuracy and loop speedare the two important parameters of such controlloops.Loop Accuracy:In a control loop, the ADC has to be accurate. Offset,gain, and the integral linearity errors of the DAC arenot factors in determining the accuracy of the loop.As long as a voltage exists in the transfer curve of amonotonic DAC, the loop can find it and settle to it.On the other hand, DAC resolution and differentiallinearity do determine the loop accuracy, becauseeach DAC step determines the minimum incrementalchange the loop can generate. A DNL error less than–1 LSB (non-monotonicity) can create loop instability.A DNL error greater than 1 LSB implies unnecessarily large voltage steps and missed voltage targets.With high DNL errors, the loop looses its stability,resolution, and accuracy. Offering 12-bit ensuredmonotonicity and 0.08 LSB typical DNL error, 755XDACs are great choices for precision control loops.Loop Speed:Many factors determine control loop speed. Typically,the ADC's conversion time, and the MCU's computation time are the two major factors that dominatethe time constant of the loop. DAC settling time israrely a dominant factor because ADC conversiontimes usually exceed DAC conversion times. DACoffset, gain, and linearity errors can slow the loopdown only during the start-up. Once the loop reachesits steady-state operation, these errors do not affectloop speed any further. Depending on the ringingcharacteristics of the loop's transfer function, DACglitches can also slow the loop down. With its 1MSPS (small-signal) maximum data update rate,DAC7554 can support high-speed control loops.Ultra-low glitch energy of the DAC7554 significantlyimproves loop stability and loop settling time.APPLICATION INFORMATIONGenerating Industrial Voltage Ranges:Waveform GenerationFor control loop applications, DAC gain and offseterrors are not important parameters. This could beexploited to lower trim and calibration costs in ahigh-voltage control circuit design. Using a quadoperational amplifier (OPA4130), and a voltage reference (REF3140), the DAC7554 can generate thewide voltage swings required by the control loop.Due to its exceptional linearity, low glitch, and lowcrosstalk, the DAC7554 is well suited for waveformgeneration (from DC to 10 kHz). The DAC7554large-signal settling time is 5 µs, supporting anupdate rate of 200 KSPS. However, the update rates17

DAC7554www.ti.comSLAS399A – OCTOBER 2004 – REVISED NOVEMBER 2004 VtailDAC7554R1REF3140R2VrefREFINDAC7554Vdac V out V ref R2 1 Din V tail R24096R1R1VOUTOPA4130Figure 35. Low-cost, Wide-swing Voltage Generator for Control Loop ApplicationsThe output voltage of the configuration is given by:(1)Fixed R1 and R2 resistors can be used to coarselyset the gain required in the first term of the equation.Once R2 and R1 set the gain to include someminimal over-range, a DAC7554 channel could beused to set the required offset voltages. Residualerrors are not an issue for loop accuracy becauseoffset and gain errors could be tolerated. OneDAC7554 channel can provide the Vtail voltage, whilethe other three DAC7554 channels can provide Vdacvoltages to help generate three high-voltage outputs.For 5-V operation: R1 10 kΩ, R2 15 kΩ, Vtail 3.33 V, Vref 4.096 VFor 10-V operation: R1 10 kΩ, R2 39 kΩ, Vtail 2.56 V, Vref 4.096 VFor 12-V operation: R1 10 kΩ, R2 49 kΩ, Vtail 2.45 V, Vref 4.096 V18

IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.Following are URLs where you can obtain information on other Texas Instruments products and samplifier.ti.comAudiowww.ti.com/audioData andInterfaceinterface.ti.comDigital ilitarywww.ti.com/militaryPower Mgmtpower.ti.comOptical Telephonywww.ti.com/telephonyVideo & Mailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2004, Texas Instruments Incorporated

VIN_H, Input high voltage VDD 3 V 0.7 VDD V Pin capacitance 3 pF POWER REQUIREMENTS VDD 2.7 5.5 V IDD(normal operation) DAC active and excluding load current VDD 3.6 V to 5.5 V VIH VDD and VIL GND 700 880 µA VDD 2.7 V to 3.6 V 550 830 IDD (all power-downmodes) VDD 3.6 V to 5.5

Related Documents:

2015 suzuki king quad (lt-a400asi) tr 2016 suzuki king quad (lt-a400asi) tr 2017 suzuki king quad (lt-a400fsi) tr 2004 suzuki quad sport (lt-z400) tr 2005 suzuki quad sport (lt-z400) nt 2006 suzuki quad sport (lt-z400) nt 2007 suzuki quad sport (lt-z400) nt 2008 suzuki quad sport (lt-z400) nt 2009 suzuki quad

Windows XP Professional 32-Bit/64-Bit, Windows Vista Business 32-Bit/64-Bit, Red Hat Enterprise Linux WS v4.0 32-bit/64-bit, Red Hat Enterprise Desktop v5.0 32-bit/64-bit (with Workstation Option), SUSE Linux Enterprise (SLE) desktop and server v10.1 32-bit/64-bit Resources Configuration LUTs

8127FS–AVR–02/2013 4. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C Page 12 0x3E SPH Stack Poin

SUZUKI SUZUKI Years Hybrid SYSTEM #105590 SUZUKI 250 2x4 ‘97-01 N/D SUZUKI 280 King Quad ‘98 & Older N/D SUZUKI 300 King Quad ‘99-01 N/D SUZUKI 400 Eiger 2x4, 4x4 ‘02-07 N/D SUZUKI 400 King Quad 4x4/AS/AF/ASi/AFi ‘08-18 Yes SUZUKI 450 King Quad 4x4/AXi ‘07-10 Yes SUZUKI 500 King Quad AXI ‘09-18 Yes SUZ

the quad. William (Bill) Orr, W6SAI (SK) in his book "All About Cubical Quad Antennas" said a group of radio engineers installed a "gigantic" four element quad in Ecuador in 1939 (All About Cubical Quad Antennas, 2nd Ed., Radio Publications, Inc., 1977). Now I see various quad related designs (e.g. "Hexbeam", "Spiderbeam") that

QUAD-DECK TYPICAL DETAIL DRAWINGS QD-100 Series QUAD-DECK PRODUCT DETAILS AND COMMON SPECIFICATIONS INDEX QD-200 Series QUAD-DECK TO QUAD-LOCK WALL DETAILS QD-300 Series QUAD-DECK

Microsoft Windows 7, 32-bit and 64-bit Microsoft Windows 8 & 8.1, 32-bit and 64-bit Microsoft Windows 10, 32-bit and 64-bit Microsoft Windows Server 2008 R2 Microsoft Windows Server 2012, 64-bit only RAM: Minimum 2 GB for the 32-bit versions of Microsoft Windows 7, Windows 8, Windows 8.1, and Windows 10.

Previous editions of this Standard were issued in 2003, 2012, and 2016. The 2019 edition of this Standard was approved by the American National Standards Institute as an American National Standard on December 4, 2019. v This is a preview of "ASME PVHO-2-2019". Click here to purchase the full version from the ANSI store.