Atmel 8-bit AVR Microcontroller With 512/1024 Bytes In .
Atmel 8-bit AVR Microcontroller with 512/1024Bytes In-System Programmable FlashATtiny4 / ATtiny5 / ATtiny9 / ATtiny10SummaryFeatures High Performance, Low Power AVR 8-Bit Microcontroller Advanced RISC Architecture – 54 Powerful Instructions – Most Single Clock Cycle Execution– 16 x 8 General Purpose Working Registers– Fully Static Operation– Up to 12 MIPS Throughput at 12 MHzNon-volatile Program and Data Memories– 512/1024 Bytes of In-System Programmable Flash Program Memory– 32 Bytes Internal SRAM– Flash Write/Erase Cycles: 10,000– Data Retention: 20 Years at 85oC / 100 Years at 25oCPeripheral Features– QTouch Library Support for Capacitive Touch Sensing (1 Channel)– One 16-bit Timer/Counter with Prescaler and Two PWM Channels– Programmable Watchdog Timer with Separate On-chip Oscillator– 4-channel, 8-bit Analog to Digital Converter (ATtiny5/10, only)– On-chip Analog ComparatorSpecial Microcontroller Features– In-System Programmable (at 5V, only)– External and Internal Interrupt Sources– Low Power Idle, ADC Noise Reduction, and Power-down Modes– Enhanced Power-on Reset Circuit– Programmable Supply Voltage Level Monitor with Interrupt and Reset– Internal Calibrated OscillatorI/O and Packages– Four Programmable I/O Lines– 6-pin SOT and 8-pad UDFNOperating Voltage:– 1.8 – 5.5VProgramming Voltage:– 5VSpeed Grade– 0 – 4 MHz @ 1.8 – 5.5V– 0 – 8 MHz @ 2.7 – 5.5V– 0 – 12 MHz @ 4.5 – 5.5VIndustrial and Extended Temperature RangesLow Power Consumption– Active Mode: 200µA at 1MHz and 1.8V– Idle Mode: 25µA at 1MHz and 1.8V– Power-down Mode: 0.1µA at 1.8VRev. 8127FS–AVR–02/20138127FS–AVR–02/2013
1. Pin ConfigurationsFigure 1-1.Pinout of ) PB0GND(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1123654PB3 (RESET/PCINT3/ADC3)VCCPB2 ICP0/OC0B/ADC1/AIN1) PB1NCNCGND12348765PB2 (T0/CLKO/PCINT2/INT0/ADC2)VCCPB3 (RESET/PCINT3/ADC3)PB0 (AIN0/ADC0/OC0A/TPIDATA/PCINT0)1.1Pin Description1.1.1VCCSupply voltage.1.1.2GNDGround.1.1.3Port B (PB3.PB0)This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit. The outputbuffers have symmetrical drive characteristics, with both high sink and source capability. As inputs, the port pinsthat are externally pulled low will source current if pull-up resistors are activated. Port pins are tri-stated when areset condition becomes active, even if the clock is not running.The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on page 36.1.1.4RESETReset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clockis not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 16-4on page 118. Shorter pulses are not guaranteed to generate a reset.The reset pin can also be used as a (weak) I/O pin.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20132
2. OverviewATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny4/5/9/10 achieve throughputsapproaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processingspeed.Figure 2-1.Block POINTERWATCHDOGTIMERTIMING ANDCONTROLINSTRUCTIONREGISTERSRAMRESET FLAGREGISTERINSTRUCTIONDECODERMCU REGISTER8-BIT DATA BUSANALOGCOMPARATORDIRECTIONREG. PORT BDATA REGISTERPORT BADCDRIVERSPORT BPB3:0GNDThe AVR core combines a rich instruction set with 16 general purpose working registers and system registers. Allregisters are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to beaccessed in one single instruction executed in one clock cycle. The resulting architecture is compact and code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable Flash, 32 bytes ofSRAM, four general purpose I/O lines, 16 general purpose working registers, a 16-bit timer/counter with two PWMATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20133
channels, internal and external interrupts, a programmable watchdog timer with internal oscillator, an internal calibrated oscillator, and four software selectable power saving modes. ATtiny5/10 are also equipped with a fourchannel, 8-bit Analog to Digital Converter (ADC).Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), analog comparator, andinterrupt system to continue functioning. ADC Noise Reduction mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep theircontents and all chip functions are disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined with low powerconsumption.The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip, in-systemprogrammable Flash allows program memory to be re-programmed in-system by a conventional, non-volatilememory programmer.The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools, including macroassemblers and evaluation kits.2.1Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10A comparison of the devices is shown in Table 2-1.Table 2-1.Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10DeviceFlashADCSignatureATtiny4512 bytesNo0x1E 0x8F 0x0AATtiny5512 bytesYes0x1E 0x8F 0x09ATtiny91024 bytesNo0x1E 0x90 0x08ATtiny101024 bytesYes0x1E 0x90 0x03ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20134
3. General Information3.1ResourcesA comprehensive set of drivers, application notes, data sheets and descriptions on development tools are availablefor download at http://www.atmel.com/microcontroller/avr.3.2Code ExamplesThis documentation contains simple code examples that briefly show how to use various parts of the device. Thesecode examples assume that the part specific header file is included before compilation. Be aware that not all Ccompiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.Please confirm with the C compiler documentation for more details.3.3Capacitive Touch SensingAtmel QTouch Library provides a simple to use solution for touch sensitive interfaces on Atmel AVR microcontrollers. The QTouch Library includes support for QTouch and QMatrix acquisition methods.Touch sensing is easily added to any application by linking the QTouch Library and using the Application Programming Interface (API) of the library to define the touch channels and sensors. The application then calls the API toretrieve channel information and determine the state of the touch sensor.The QTouch Library is free and can be downloaded from the Atmel website. For more information and details ofimplementation, refer to the QTouch Library User Guide – also available from the Atmel website.3.4Data RetentionReliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20years at 85 C or 100 years at 25 C.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20135
4. Register SummaryAddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Page0x3FSREGITHSVNZCPage 120x3ESPHStack Pointer High BytePage 120x3DSPLStack Pointer Low BytePage 12Note:0x3CCCP0x3BRSTFLR–––CPU Change Protection Byte0x3ASMCR–––0x39OSCCALPage 11–WDRF–EXTRFPORF–SM2SM1SM0SEPage 34Page 25Oscillator Calibration BytePage �–––––CLKMS1CLKMS0Page ge 220x35PRR––––––PRADCPRTIM0Page 260x34VLMCSRVLMFVLMIE–––VLM2VLM1VLM0Page ��–Page 1140x31WDTCSRWDIFWDIEWDP3–WDEWDP2WDP1WDP0Page 320x30Reserved––––––––NVM CommanPage A1COM0A0COM0B1COM0B0––WGM01WGM00Page 78Page e 740x2CTCCR0CFOC0AFOC0B––––––Page 750x2BTIMSK0––ICIE0––OCIE0BOCIE0ATOIE0Page HPage 78Timer/Counter0 – Counter Register High BytePage 760x28TCNT0LTimer/Counter0 – Counter Register Low BytePage 760x27OCR0AHTimer/Counter0 – Compare Register A High BytePage 760x26OCR0ALTimer/Counter0 – Compare Register A Low BytePage 760x25OCR0BHTimer/Counter0 – Compare Register B High BytePage 760x24OCR0BLTimer/Counter0 – Compare Register B Low BytePage 760x23ICR0HTimer/Counter0 - Input Capture Register High BytePage 770x22ICR0LTimer/Counter0 - Input Capture Register Low BytePage DCSRAADENADSCADATEADIFADIEADPS2ADPS1ADPS0Page 920x1CADCSRB–––––ADTS2ADTS1ADTS0Page 930x1BADMUX––––––MUX1MUX0Page 920x1AReserved–––––––––ADC Conversion ResultPage 800x19ADCL0x18Reserved––––––––Page Page 380x13EIMSK–––––––INT0Page 380x12PCICR–––––––PCIE0Page 390x11PCIFR–––––––PCIF0Page e 390x0FReserved––––––––Page 81, Page 94Page ��––PORTB3PORTB2PORTB1PORTB0Page 510x01DDRB––––DDRB3DDRB2DDRB1DDRB0Page 510x00PINB––––PINB3PINB2PINB1PINB0Page 51Page 50Page 501. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addressesATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20136
should never be written.2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In theseregisters, the value of single bits can be checked by using the SBIS and SBIC instructions.3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBIinstructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. TheCBI and SBI instructions work with registers 0x00 to 0x1F only.4. The ADC is available in ATtiny5/10, only.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/20137
5. Instruction Set ClocksARITHMETIC AND LOGIC INSTRUCTIONSADDRd, RrAdd without CarryRd Rd RrZ,C,N,V,S,HADCRd, RrAdd with CarryRd Rd Rr CZ,C,N,V,S,H1SUBRd, RrSubtract without CarryRd Rd - RrZ,C,N,V,S,H11SUBIRd, KSubtract ImmediateRd Rd - KZ,C,N,V,S,H1SBCRd, RrSubtract with CarryRd Rd - Rr - CZ,C,N,V,S,H1SBCIRd, KSubtract Immediate with CarryRd Rd - K - CZ,C,N,V,S,H1ANDRd, RrLogical ANDRd Rd RrZ,N,V,S1ANDIRd, KLogical AND with ImmediateRd Rd KZ,N,V,S1ORRd, RrLogical ORRd Rd v RrZ,N,V,S1ORIRd, KLogical OR with ImmediateRd Rd v KZ,N,V,S1EORRd, RrExclusive ORRd Rd RrZ,N,V,S11COMRdOne’s ComplementRd FF RdZ,C,N,V,SNEGRdTwo’s ComplementRd 00 RdZ,C,N,V,S,H1SBRRd,KSet Bit(s) in RegisterRd Rd v KZ,N,V,S11CBRRd,KClear Bit(s) in RegisterRd Rd ( FFh - K)Z,N,V,SINCRdIncrementRd Rd 1Z,N,V,S1DECRdDecrementRd Rd 1Z,N,V,S1TSTRdTest for Zero or MinusRd Rd RdZ,N,V,S1CLRRdClear RegisterRd Rd RdZ,N,V,S1SERRdSet RegisterRd FFNone1Relative JumpPC PC k 1None2Indirect Jump to (Z)PC(15:0) Z, PC(21:16) 0None2BRANCH INSTRUCTIONSRJMPkIJMPRelative Subroutine CallPC PC k 1None3/4ICALLIndirect Call to (Z)PC(15:0) Z, PC(21:16) 0None3/4RETSubroutine ReturnPC STACKNone4/5RETIInterrupt ReturnPC STACKIif (Rd Rr) PC PC 2 or 3NoneRCALLk4/5CPSERd,RrCompare, Skip if Equal1/2/3CPRd,RrCompareRd RrZ, C,N,V,S,H1CPCRd,RrCompare with CarryRd Rr CZ, C,N,V,S,H1CPIRd,KCompare with ImmediateRd KZ, C,N,V,S,HSBRCRr, bSkip if Bit in Register Clearedif (Rr(b) 0) PC PC 2 or 3None11/2/3SBRSRr, bSkip if Bit in Register is Setif (Rr(b) 1) PC PC 2 or 3None1/2/3SBICA, bSkip if Bit in I/O Register Clearedif (I/O(A,b) 0) PC PC 2 or 3None1/2/3SBISA, bSkip if Bit in I/O Register is Setif (I/O(A,b) 1) PC PC 2 or 3None1/2/3BRBSs, kBranch if Status Flag Setif (SREG(s) 1) then PC PC k 1None1/2BRBCs, kBranch if Status Flag Clearedif (SREG(s) 0) then PC PC k 1None1/2BREQkBranch if Equalif (Z 1) then PC PC k 1None1/2BRNEkBranch if Not Equalif (Z 0) then PC PC k 1None1/2BRCSkBranch if Carry Setif (C 1) then PC PC k 1None1/2BRCCkBranch if Carry Clearedif (C 0) then PC PC k 1None1/2BRSHkBranch if Same or Higherif (C 0) then PC PC k 1None1/2BRLOkBranch if Lowerif (C 1) then PC PC k 1None1/2BRMIkBranch if Minusif (N 1) then PC PC k 1None1/2BRPLkBranch if Plusif (N 0) then PC PC k 1None1/2BRGEkBranch if Greater or Equal, Signedif (N V 0) then PC PC k 1None1/2BRLTkBranch if Less Than Zero, Signedif (N V 1) then PC PC k 1None1/2BRHSkBranch if Half Carry Flag Setif (H 1) then PC PC k 1None1/2BRHCkBranch if Half Carry Flag Clearedif (H 0) then PC PC k 1None1/2BRTSkBranch if T Flag Setif (T 1) then PC PC k 1None1/2BRTCkBranch if T Flag Clearedif (T 0) then PC PC k 1None1/2BRVSkBranch if Overflow Flag is Setif (V 1) then PC PC k 1None1/2BRVCkBranch if Overflow Flag is Clearedif (V 0) then PC PC k 1None1/2BRIEkBranch if Interrupt Enabledif ( I 1) then PC PC k 1None1/2BRIDkBranch if Interrupt Disabledif ( I 0) then PC PC k 1None1/2BIT AND BIT-TEST INSTRUCTIONSLSLRdLogical Shift LeftRd(n 1) Rd(n), Rd(0) 0Z,C,N,V,HLSRRdLogical Shift RightRd(n) Rd(n 1), Rd(7) 0Z,C,N,V1ROLRdRotate Left Through CarryRd(0) C,Rd(n 1) Rd(n),C Rd(7)Z,C,N,V,H1RORRdRotate Right Through CarryRd(7) C,Rd(n) Rd(n 1),C Rd(0)Z,C,N,V1ASRRdArithmetic Shift RightRd(n) Rd(n 1), n 0.6Z,C,N,V1SWAPRdSwap NibblesRd(3.0) Rd(7.4),Rd(7.4) Rd(3.0)None1BSETsFlag SetSREG(s) 1SREG(s)1BCLRsFlag ClearSREG(s) 0SREG(s)1SBIA, bSet Bit in I/O RegisterI/O(A, b) 1None1ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201318
BIA, bClear Bit in I/O RegisterI/O(A, b) 0NoneBSTRr, bBit Store from Register to TT Rr(b)T1BLDRd, bBit load from T to RegisterRd(b) TNone111SECSet CarryC 1CCLCClear CarryC 0C1SENSet Negative FlagN 1N1CLNClear Negative FlagN 0N1SEZSet Zero FlagZ 1Z1CLZClear Zero FlagZ 0Z1SEIGlobal Interrupt EnableI 1I1CLIGlobal Interrupt DisableI 0I11SESSet Signed Test FlagS 1SCLSClear Signed Test FlagS 0S1SEVSet Two’s Complement Overflow.V 1V1CLVClear Two’s Complement OverflowV 0V1SETSet T in SREGT 1T1CLTClear T in SREGT 0T1SEHCLHSet Half Carry Flag in SREGClear Half Carry Flag in SREGH 1H 0HH11DATA TRANSFER INSTRUCTIONSMOVRd, RrCopy RegisterRd RrNone1LDIRd, KLoad ImmediateRd KNone11/2LDRd, XLoad IndirectRd (X)NoneLDRd, X Load Indirect and Post-IncrementRd (X), X X 1None2LDRd, - XLoad Indirect and Pre-DecrementX X - 1, Rd (X)None2/31/2LDRd, YLoad IndirectRd (Y)NoneLDRd, Y Load Indirect and Post-IncrementRd (Y), Y Y 1None2LDRd, - YLoad Indirect and Pre-DecrementY Y - 1, Rd (Y)None2/31/2LDRd, ZLoad IndirectRd (Z)NoneLDRd, Z Load Indirect and Post-IncrementRd (Z), Z Z 1None2LDRd, -ZLoad Indirect and Pre-DecrementZ Z - 1, Rd (Z)None2/3LDSRd, kStore Direct from SRAMRd k)None1STX, RrStore Indirect(X) RrNone1STX , RrStore Indirect and Post-Increment(X) Rr, X X 1None1ST- X, RrStore Indirect and Pre-DecrementX X - 1, (X) RrNone2STY, RrStore Indirect(Y) RrNone1STY , RrStore Indirect and Post-Increment(Y) Rr, Y Y 1None1ST- Y, RrStore Indirect and Pre-DecrementY Y - 1, (Y) RrNone2STZ, RrStore Indirect(Z) RrNone1STZ , RrStore Indirect and Post-Increment.(Z) Rr, Z Z 1None1ST-Z, RrStore Indirect and Pre-DecrementZ Z - 1, (Z) RrNone2STSk, RrStore Direct to SRAM(k) RrNone1INRd, AIn from I/O LocationRd I/O (A)None1OUTA, RrOut to I/O LocationI/O (A) RrNone1PUSHRrPush Register on StackSTACK RrNone2POPRdPop Register from StackRd STACKNone2MCU CONTROL INSTRUCTIONSBREAKBreak(see specific descr. for Break)None1NOPNo OperationNone1SLEEPWDRSleepWatchdog ResetNoneNone1(see specific descr. for Sleep)(see specific descr. for WDR)ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201319
6. Ordering Information6.1ATtiny4Supply VoltageSpeed (1)TemperaturePackage (2)Industrial(-40 C to 85 C) (4)6ST1ATtiny4-TSHR(5)12 MHz8MA4ATtiny4-MAHR (6)6ST1ATtiny4-TS8R (5)1.8 – 5.5V10 MHzNotes:Extended(-40 C to 125 C) (6)Ordering Code (3)1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116.2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.3. Tape and reel.4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5. Top/bottomside markings:– Top: T4x, where x die revision– Bottom: zHzzz or z8zzz, where H (-40 C to 85 C), and 8 (-40 C to 125 C)6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125 C.Package Type6ST16-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8MA48-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201310
6.2ATtiny5Supply VoltageSpeed (1)TemperaturePackage (2)Industrial(-40 C to 85 C) (4)6ST1ATtiny5-TSHR (5)12 MHz8MA4ATtiny5-MAHR (6)6ST1ATtiny5-TS8R (5)1.8 – 5.5V10 MHzNotes:Extended(-40 C to 125 C) (6)Ordering Code (3)1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116.2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.3. Tape and reel.4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5. Top/bottomside markings:– Top: T5x, where x die revision– Bottom: zHzzz or z8zzz, where H (-40 C to 85 C), and 8 (-40 C to 125 C)6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125 C.Package Type6ST16-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8MA48-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201311
6.3ATtiny9Supply VoltageSpeed (1)TemperaturePackage (2)Industrial(-40 C to 85 C) (4)6ST1ATtiny9-TSHR (5)12 MHz8MA4ATtiny9-MAHR (6)6ST1ATtiny9-TS8R (5)1.8 – 5.5V10 MHzNotes:Extended(-40 C to 125 C) (6)Ordering Code (3)1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116.2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.3. Tape and reel.4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5. Top/bottomside markings:– Top: T9x, where x die revision– Bottom: zHzzz or z8zzz, where H (-40 C to 85 C), and 8 (-40 C to 125 C)6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125 C.Package Type6ST16-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8MA48-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201312
6.4ATtiny10Supply VoltageSpeed (1)TemperaturePackage (2)Ordering Code (3)Industrial(-40 C to 85 C) (4)6ST1ATtiny10-TSHR (5)12 MHz8MA4ATtiny10-MAHR (6)6ST1ATtiny10-TS8R (5)1.8 – 5.5V10 MHzNotes:Extended(-40 C to 125 C) (6)1. For speed vs. supply voltage, see section 16.3 “Speed” on page 116.2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS). NiPdAu finish.3. Tape and reel.4. Can also be supplied in wafer form. Contact your local Atmel sales office for ordering information and minimum quantities.5. Top/bottomside markings:– Top: T10x, where x die revision– Bottom: zHzzz or z8zzz, where H (-40 C to 85 C), and 8 (-40 C to 125 C)6. For typical and Electrical characteristics for this device please consult Appendix A, ATtiny4/5/9/10 Specification at 125 C.Package Type6ST16-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)8MA48-pad, 2 x 2 x 0.6 mm Plastic Ultra Thin Dual Flat No Lead (UDFN)ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201313
7. Packaging Information7.16ST1D56EE1A4A2Pin #1 IDA132b0.10 CSEATING PLANEA1ACSide VieweTop ViewA2A0.10 CSEATING PLANEc0.25OCA1CView A-ASEATING PLANESEE VIEW BLView BCOMMON DIMENSIONS(Unit of Measure mm)SYMBOL MINNotes: 1. This package is compliant with JEDEC specification MO-178 Variation AB2. Dimension D does not include mold Flash, protrusions or gate burrs.Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end.3. Dimension b does not include dambar protrusion. Allowable dambarprotrusion shall not cause the lead width to exceed the maximumb dimension by more than 0.08 mm4. Die is facing down after .55eNOTE20.95 BSCb0.30–0.50c0.09–0.20θ0 –8 36/30/08Package Drawing Contact:packagedrawings@atmel.comTITLE6ST1, 6-lead, 2.90 x 1.60 mm Plastic Small OutlinePackage (SOT23)GPCTAQDRAWING NO.REV.6ST1AATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201314
7.28MA48768x50.05 cc0.05 cESIDE VIEWPin 1 ID1234DA1TOP VIEWAD2e85COMMON DIMENSIONS(Unit of Measure 0.241LbBOTTOM �NOTENote: 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES.2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THETERMINALS COPLANARITY SHALL NOT EXCEED 0.05 mm.3. WARPAGE SHALL NOT EXCEED 0.05 mm.4. REFER JEDEC MO-236/MO-252TITLEPackage Drawing Contact:packagedrawings@atmel.com8PAD, 2x2x0.6 mm body, 0.5 mm pitch,0.9x1.5 mm exposed pad, Saw singulatedThermally enhanced plastic ultra thin dual flatno lead package (UDFN/USON)GPCYAG12/17/09DRAWING NO. REV.8MA4ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/2013A15
8. ErrataThe revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10 device.8.1ATtiny48.1.1Rev. E Programming Lock Bits1. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.1.2Rev. D ESD HBM (ESD STM 5.1) level 1000V Programming Lock Bits1. ESD HBM (ESD STM 5.1) level 1000VThe device meets ESD HBM (ESD STM 5.1) level 1000V.Problem Fix / WorkaroundAlways use proper ESD protection measures (Class 1C) when handling integrated circuits before and duringassembly.2. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.1.3Rev. A – CNot sampled.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201316
8.2ATtiny58.2.1Rev. E Programming Lock Bits1. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.2.2Rev. D ESD HBM (ESD STM 5.1) level 1000V Programming Lock Bits1. ESD HBM (ESD STM 5.1) level 1000VThe device meets ESD HBM (ESD STM 5.1) level 1000V.Problem Fix / WorkaroundAlways use proper ESD protection measures (Class 1C) when handling integrated circuits before and duringassembly.2. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.2.3Rev. A – CNot sampled.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201317
8.3ATtiny98.3.1Rev. E Programming Lock Bits1. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.3.2Rev. D ESD HBM (ESD STM 5.1) level 1000V Programming Lock Bits1. ESD HBM (ESD STM 5.1) level 1000VThe device meets ESD HBM (ESD STM 5.1) level 1000V.Problem Fix / WorkaroundAlways use proper ESD protection measures (Class 1C) when handling integrated circuits before and duringassembly.2. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.3.3Rev. A – CNot sampled.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201318
8.4ATtiny108.4.1Rev. E Programming Lock Bits1. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.4.2Rev. C – D ESD HBM (ESD STM 5.1) level 1000V Programming Lock Bits1. ESD HBM (ESD STM 5.1) level 1000VThe device meets ESD HBM (ESD STM 5.1) level 1000V.Problem Fix / WorkaroundAlways use proper ESD protection measures (Class 1C) when handling integrated circuits before and duringassembly.2. Programming Lock BitsProgramming Lock Bits to a lock mode equal or lower than the current causes one word of Flash to be corrupted. The location of the corruption is random.Problem Fix / WorkaroundWhen programming Lock Bits, make sure lock mode is not set to present, or lower levels.8.4.3Rev. A – BNot sampled.ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201319
9. Datasheet Revision History9.1Rev. 8127F – 02/131. Updated:– Ordering information on page 10, page 11, page 12, and page 139.2Rev. 8127E – 11/111. Updated:– Device status from Preliminary to Final– Ordering information on page 10, page 11, page 12, and page 139.3Rev. 8127D – 02/101. Added UDFN package in “Features” on page 1, “Pin Configurations” on page 2, “Ordering Information” onpage 10, and in “Packaging Information” on page 142. Updated Figure 8-2 and Figure 8-3 in Section 8.2.1 “Power-on Reset” on page 273. Updated Section 8.2.3 “External Reset” on page 294. Updated Figures 17-36 and 17-51 in “Typical Characteristics”5. Updated notes in Section 6. “Ordering Information” on pages 10 - 136. Added device Rev. E in Section 8. “Errata” on page 169.4Rev. 8127C – 10/091. Updated values and notes:– Table 16-1 in Section 16.2 “DC Characteristics” on page 115– Table 16-3 in Section 16.4 “Clock Characteristics” on page 117– Table 16-6 in Section 16.5.2 “VCC Level Monitor” on page 118– Table 16-9 in Section 16.8 “Serial Programming Characteristics” on page 1202. Updated Figure 16-1 in Section 16.3 “Speed” on page 1163. Added Typical Characteristics Figure 17-36 in Section 17.8 “Analog Comparator Offset” on page 139.Also, updated some other plots in Typical Characteristics.4. Added topside and bottomside marking notes in Section 6. “Ordering Information” on page 10, up to page135. Added ESD errata, see Section 8. “Errata” on page 166. Added Lock bits re-programming errata, see Section 8. “Errata” on page 169.5Rev. 8127B – 08/091. Updated document template2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny93. Added section:– “Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 44. Updated sections:– “ADC Clock – clkADC” on page 18– “Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20– “ADC Noise Reduction Mode” on page 24– “Analog to Digital Converter” on page 25ATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201320
– “SMCR – Sleep Mode Control Register” on page 25– “PRR – Power Reduction Register” on page 26– “Alternate Functions of Port B” on page 48– “Overview” on page 82– “Physical Layer of Tiny Programming Interface” on page 95– “Overview” on page 106– “ADC Characteristics (ATtiny5/10, only)” on page 119– “Supply Current of I/O Modules” on page 121– “Register Summary” on page 6– “Ordering Information” on page 105. Added figure:– “Using an External Programmer for In-System Programming via TPI” on page 966. Updated figure:– “Data Memory Map (Byte Addressing)” on page 157. Added table:– “Number of Words and Pages in the Flash (ATtiny4/5)” on page 1088. Updated tables:– “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23– “Reset and Interrupt Vectors” on page 35– “Number of Words and Pages in the Flash (ATtiny9/10)” on page 107– “Signature codes” on page 1099.6Rev. 8127A – 04/091. Initial revisionATtiny4/5/9/10 [DATASHEET]8127FS–AVR–02/201321
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8127FS–AVR–02/2013 4. Register Summary Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F SREG I T H S V N Z C Page 12 0x3E SPH Stack Poin
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the Atmel AVR XMEGA AU microcontroller family. The Atmel AVR XMEGA AU is a family of low-power, high-performance, and peripheral-rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. The available Atmel AVR XMEGA AU modules described in this manual are: zAtmel AVR CPU zMemories zDMAC - Direct memory access controller
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