Simple VHDL Example Using VIVADO 2015 With ZYBO FPGA

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Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAimI am FPGA novice and want to try classical FPGA design tutorials. I bought perfectmodern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent butlatest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while Iwant to just pure FPGA design without any linuxes bootloaders etc. So I wrote thistutorial to help people like me :)In this example we make simple scheme: 2 signals IN and 4 OUT.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD1

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardPreconditions: Adding Zybo Board to VivadoVivado 2015.2 under Windows 7 64 bit was used with 16 GB of RAM.Before using Zybo with Vivado you should add Zybo Definitions File to Vivado.1. Good source for Board Definition files is Zynqbook website.DownloadThe Zynq Book Tutorial Sources Aug15.zip2. Copy zybo folder with content from Archive path \sources\zybo\setup\board partinto D:\Xilinx\Vivado\2015.2\data\boards\board files (if D:\Xilinx\Vivado\2015.2 is myPC you probably have C:\Xilinx etc.)3. In board files you should see other boards so now our Zybo known by Vivado.4. Download ZYBO Master.xdc from Digilent website unpack constraints file it on localhard disk.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD2

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardLaunch VivadoI have latest Vivado Design Edition from Xilinx which comes with Digilent Zybo board.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD3

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardCreate new projectSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD4

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardNew ProjectClick NextSet project name.Set project name to gates2,SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD5

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardKeep rest settings unchanged unless you know what you doing.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD6

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardProject TypeKeep default RTL project, Press NextAdd sourcesIn this tutorial we decided to use VHDL language so make sure it set correctly. Simulatorlanguage you can keep unchanged.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD7

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardClick on " " - Select - Create File.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD8

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardCreate Source FileSet Filename to gates2. Keep the rest unchaged. Press OK. Press Next.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD9

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAdd Existing IPClick Next.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD10

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAdd ConstraintsClick " ", Add Files.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD11

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAdd Constraint file we downloaded at Precondition step.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD12

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardMake sure: Copy constraints files into project - Checked.Click - NextDefault PartClick on boards and select Zybo. If you still don't have it follow steps in Preconditions:Adding Zybo board to Vivado.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD13

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardIf you don't see ZYBO goto Preconditions Step.Next.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD14

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardNew Project SummaryFinishNew Project main viewProject files generated and ready for your design.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD15

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardWe will implement 2 input gates and 4 output basic gates and, or, xor and nor.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD16

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardDefine I/O ports as belowOKSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD17

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSelect VHDL DesignClick on Source file in Project Manager Sources Design Sources - Source code onRighthand side should appear.Changes to source code.Modify VHDL file - add lines as highlighted below.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD18

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardz(0) a and b;z(1) a or b;z(2) a xor b;z(3) a nor b;SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD19

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardCreate top fileRightclick on Design Sources and select Add Sources.1. Add or create design souces.2. " " Create FileFile Type :VHDL,File name: top gates2SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD20

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardOKFinishSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD21

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardDefine ModuleAdd sw and led as on image below.Replace default source code.library IEEE;use IEEE.STD LOGIC 1164.ALL;SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD22

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardentity top gates2 isPort (sw : in STD LOGIC VECTOR (1 downto 0);led : out STD LOGIC VECTOR (3 downto 0));end top gates2;architecture top gates2 of top gates2 iscomponent gates2 isPort (a : in STD LOGIC;b : in STD LOGIC;z : out STD LOGIC VECTOR (3 downto 0));end component;begincl : gates2SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD23

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardport map (a sw(0),b sw(1),z(0) led(0),z(1) led(1),z(2) led(2),z(3) led(3));end top gates2;SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD24

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD25

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardTop DesignWe have single top design interface file which use our gates2 design as component.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD26

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardtop designMake sure our top file became parent of gates2 file. Otherwise set it manually with Setas Top.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD27

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAmend Constraints fileSelect xdc file from Sources ConstraintsSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD28

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardChanges in xdc fileUncomment lines of I/O port we need to use.Save file.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD29

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD30

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSynthesisAt Synthesis phase we convert our circuit from register transfer level (RTL) into adesign implementation in terms of logic gates.In Flow Navigator on Lefthand side.:Next steps can be Simulation Run Simulation or RTL Analysis Schematic but weskip them in this tutorial and come directly to Synthesis Run Synthesis.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD31

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD32

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardSynthesis complentionLeave default Run ImplementationOKSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD33

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardGenerate BitstreamSelect Generate BitstreamOKFinalPay attention to jumpers.JP7 - It should set to USB.JP5 can be JTAG or QSPIConnect ZYBO to PC with Micro-USB cable.SIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD34

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardPhoto from mlSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD35

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardProgram ZYBOSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD36

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardNextSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD37

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardNextSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD38

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardMake sure you have similar setting like on picture below.Select xc7z010 1NextSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD39

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardFinishSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD40

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardProgram device xc7z010 1ProgramSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD41

Simple VHDL example using VIVADO2015 with ZYBO FPGA boardAs confirmation of successfull upload Greed Led will setUse switches to confirm and, or, xor and nor operations.Archive of project available.Reference1. Digital Design Using Digilent FPGA Boards VHDL/ Active-HDL edition. Richard E.Haskell, Darrin M. HannaSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD42

Simple VHDL example using VIVADO2015 with ZYBO FPGA board2. Learning By Example Using VHDL. Advanced Digital Design With a NEXYS 2 FPGABoard. Richard E. Haskell, Darrin M. Hanna3. The ZYNQ BOOK - Make sure you download not only book archive but also tutorialsbook with sources.4. HDL Chip Design- A Practical Guide for Designing, Synthesizing and SimulatingASICs and FPGAs Using VHDL or Verilog. By Douglas J. Smith5. ZYBO Reference ManualSIMPLE VHDL EXAMPLE USING VIVADO 2015WITHZYBO FPGA BOARD43

I am FPGA novice and want to try classical FPGA design tutorials. I bought perfect modern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent but latest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while I want to just pure FPGA de

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