CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE

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CS31001 COMPUTERORGANIZATIONANDARCHITECTUREDebdeep Mukhopadhyay,CSE, IIT KharagpurReferences/Text Books Theory: Computer Organization and Design, 4th Ed, D. A.Patterson and J. L. HennessyComputer Architceture and Organization, J. P. HayesComputer Architecture, Berhooz ParhamiMicroprocessor Architecture, Jean Loup BaerLaboratory: Douglas Smith, HDL Chip Design (for Verilog)SPIM Tutorial :pages.cs.wisc.edu/ larus/spim.html1

Pre-Midsem Syllabus Overview: Terms and TaxonomyInstruction Set Architecture: Instruction and AddressingProcedures and DataAssembly Languages Programs: SPIM simulator and DebuggerNumbers and Computers: Number RepresentationsAddersMultipliersFloating Point ArithmeticPre-MidSem Syllabus Design of a Processor: Instruction Execution StepsControl Unit Design: MicroprogrammingPipelined Data Paths PerformanceHazards2

An OverviewVon Neumann Model 1903-1957Contributed to give a verybasic model, often referredto as Von Neumann model3

The von Neumann erINPUTALUOUTPUTMEMORYCPUI/O BUSMEMORY BUSThe Stored Program Concept Programs are sequence of instructions stored in thememory.The CPU consists of: Program Counter (PC) indicates the address of the nextinstruction to be executed.ALU (Arithmetic Logic Unit) performs arithmetic and logical operationsRegisters: High Speed storage of operands.Control Unit: That interprets instructions and causes themto be executed.4

The Stored Program Concept The memory stores the instructions, data andintermediate results. Memory has severalhierarchy: registers being the highest level and the fastestform.Input/ Output: Transmits and receives resultsand messages (information) from and to theoutside world respectively.Instruction Execution Cycle Next instruction is fetched from memory.Control Unit decodes the instruction.Instruction is executed: ALU basedload from a memory location to a registerstore from a register to the memorytesting condition of a potential branchPC is updated (incremented except for a branch)Repeat5

Brief HistoryBlack bars:frequency atintroductionWhite bars:peak frequency Evolution of Intel Microprocessors (from Jean Baer,Microprocessor Architecture, Cambridge University Press)Moore’s law for Intel Microprocessors Evolution of Intel Microprocessors (from Jean Baer,Microprocessor Architecture, Cambridge University Press)6

Some figures 1971: Intel 4004, 1.08 MHz, 2,300 transistors2003: Intel Pentium 4, 3.4 GHz, 1.7 billiontransistors Frequency increases roughly double per 2.5 yearsNumber of transistors roughly double every twoyears (Moore’s Law).How will the trend continue in the future?Power Dissipation in Intel Processors Evolution of Intel Microprocessors (from Jean Baer,Microprocessor Architecture, Cambridge University Press)7

Performance Metrics Raw Speed and number of transistors give a goodindication of the developments made by theprocessors.However we need more precise metrics. to evaluate how fast a program executesBut it depends on several factors: Operating SystemCompilerNetworkNature of ProgramProgram Independent Metrics andBenchmarks Program Independent metrics: Metrics whichare not affected by the types of programs. Benchmarks: A suite of programs, thatindicate the load of the processor.8

Instructions Per Cycle (IPC) Metrics to asses the micro-architecture andthe memory hierarchy, should be independentof the IO subsystem.Define, EXCPU as the time to execute aprogram (a collection of instructions), whenthe code and data both reside in the memory. EXCPU Number of Instructions x Time to executeone instructionCPI vs IPC Now, Time to execute one instruction CyclesPer Instruction (CPI) x Cycle time CPI is a program-independent, clock frequencyindependent metric.IPC (Instructions per cycle) 1/CPIMore intuitive as one tries to increase IPC (ratherthan decreasing CPI).IPC (Number of Instructions x cycle time)/EXCPU 9

Performance Can be defined as the reciprocal of EXCPU.Three important factors: Compiler driven: For a given set of Instructions (called asISA-Instruction Set Architecture), and a given program, itdecides the number of instructions. Micro-architecture design and implementation: Smallerthe CPI or more the IPC, better the performance. Technology: Decides the cycle time.Reduction of Instructions does notnecessarily make the programs faster Consider the example, where a multiplicationprogram can be realized by shift and add.The number of instructions increase.But the overall time required reduces. This is because, not all instructions take the samenumber of cycles.10

Conclusions Von Neumann Model: The Load StoreArchitectureThe Instruction Cycle.The trend in processor designs, Moore’s law.Performance Metrics.11

CS31001 COMPUTER ORGANIZATION AND ARCHITECTURE Debdeep Mukhopadhyay, CSE, IIT Kharagpur References/Text Books Theory: Computer Organization and Design, 4th Ed, D. A. Patterson and J. L. Hennessy Computer Architceture and Organization, J. P. Hayes Computer Architecture, Berhooz Parhami Microprocessor Architecture, Jean Loup Baer

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