Semester: IV Subject: Computer Systems Architecture Code .

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Semester: IV Branch: Computer Science & EngineeringSubject: Computer Systems Architecture Code: 322414 (22)Total Theory Periods: 40 Total Tut Periods: 10Total Marks in End Semester Exam: 80Maximum number of Class Tests to be conducted: 2Unit 1: Processor BasicsCPU Organization, Fundamental and features, Data Representation formats, Fixed andFloatingpoint representation, Instruction Sets, Formats, Types and Programming Considerations.Unit 2: Datapath DesignFixed-Point Arithmetic, Combinational ALU and Sequential ALU, Floating point arithmeticandAdvanced topics, Hardware Algorithm – Multiplication, Division.Unit 3: Control DesignBasic Concepts, Hardwired control, Microprogrammed Control, CPU control unit andMultipliercontrol unit, Pipeline Control.

Unit 4: Memory OrganizationMemory device characteristics, RAM technology and Serial access memoriestechnology,Multilevel memory systems, Address translation and Memory allocation systems,Cachesmemory.Unit 5: System OrganizationProgrammed I/O , DMA, Interrupts and IO Processors, Processor-level Parallelism,Multiprocessor and Fault tolerance system.Name of Text Books1. Computer Architecture and organization – John P Hayes, McGraw Hill Publication2 Computer Organizations and Design- P. Pal Chaudhari, Prentice-Hall of IndiaName of reference Books:1. Computer System Architecture - M. Morris Mano, PHI.2. Computer Organization and Architecture- William Stallings, Prentice-Hall of India3. Architecture of Computer Hardware and System Software: An Information TechnologyApproach,3rd Edition (Illustrated) – Iry Englander, John Wiley & Sons Inc4 Structured Computer Organization Andrew S Tanenbaum, Prentice-Hall of India5 Computer Systems Organization & Architecture – John D Carpinelli, Addison-Wesle

Unit - 02Principles of Computerdesign

Register Organization

Determining The Type of Instruction

Elements of an Instruction Operation code (Op code)– Do this Source Operand reference– To this Result Operand reference– Put the answer here Next Instruction Reference– When you have done that, do this.

Where have all the Operands gone? Main memory (or virtual memory or cache) CPU register I/O device

Instruction RepresentationOPCODEOPERAND1OPERAND2

Instruction Types Data processingData storage (main memory)Data movement (I/O)Program flow control

Number of Addresses (a) 3 addresses– Operand 1, Operand 2, Result– a b c;– May be a forth - next instruction (usually implicit)– Not common– Needs very long words to hold everything

Number of Addresses (b) 2 addresses– One address doubles as operand and result–a a b– Reduces length of instruction– Requires some extra work Temporary storage to hold some results

Number of Addresses (c) 1 address– Implicit second address– Usually a register (accumulator)– Common on early machines

Number of Addresses (d) 0 (zero) addresses– All addresses implicit– Uses a stack– e.g. push a–push b–add–pop c–c a b

How Many Addresses More addresses– More complex (powerful?) instructions– More registers Inter-register operations are quicker– Fewer instructions per program Fewer addresses– Less complex (powerful?) instructions– More instructions per program– Faster fetch/execution of instructions

Design Decisions (1) Operation repertoire– How many ops?– What can they do?– How complex are they? Data types Instruction formats– Length of op code field– Number of addresses

Design Decisions (2) Registers– Number of CPU registers available– Which operations can be performed on whichregisters? Addressing modes (later ) RISC v CISC

Instruction cycle with interrupt136

Interrupts - In Summary An interruption of normal processing Improves processing efficiency Allows the processor to execute otherinstructions while an I/O operation is inprogress A suspension of a process caused by an eventexternal to that process and performed in sucha way that the process can be resumed137

Classes of Interrupts Program– arithmetic overflow– division by zero– execute illegal instruction– reference outside user’s memory space Timer I/O Hardware failure138

Common Functions of Interrupts Interrupts transfer control to the interrupt serviceroutine generally, through the interrupt vector Interrupt architecture must save the address of theinterrupted instruction. interrupts are disabled while another interrupt isbeing processed to prevent a lost interrupt. A trap is a software-generated interrupt causedeither by an error or a user request. An operating system is interrupt driven.139

Interrupt Handling The operating system preserves the state of theCPU by storing registers and the programcounter. Determines which type of interrupt hasoccurred:– polling– vectored interrupt system Separate segments of code determine whataction should be taken for each type ofinterrupt140

Instruction Cycle with InterruptsInterrupt CycleExecute CycleInterrupts DisabledSTARTFetch NextInstructionExecuteInstructionInterrupts EnabledFetch CycleCheck for &Process IntHALT141

Interrupt Cycle Processor checks for interrupts If no interrupts fetch the next instruction forthe current program If an interrupt is pending, suspend executionof the current program, and execute theinterrupt handler142

Interrupt Service Routine (aka handler) A program that determines nature of theinterrupt and performs whatever actionsare needed Control is transferred to this program Generally part of the operating system143

Simple Interrupt ProcessingHardwareSoftwareDevice controller orother system hardwareissues an interruptProcessor finishesexecution of currentinstructionProcessor signalsacknowledgmentof interruptProcessor pushes PSWand PC onto controlstackProcessor loads newPC value based oninterruptSave remainder ofprocess stateinformationProcess interruptRestore process stateinformationRestore old PSWand PC144

What about Multiple Interrupts Simple Approach - disable interrupts Use Priorities to differentiate betweeninterrupt classes145

Multiple Interrupts Sequential Order Disable interrupts so processor cancomplete task Interrupts remain pending until theprocessor enables interrupts After interrupt handler routine completes,the processor checks for additionalinterrupts146

Multiple Interrupts Priorities Higher priority interrupts cause lowerpriority interrupts to wait Causes a lower-priority interrupt handler tobe interrupted Example when input arrives fromcommunication line, it needs to beabsorbed quickly to make room for moreinput147

Unit – 03CPU&Control Unit

Instruction FormatsThe format of an instruction is usually depicted in arectangular box symbolizing the bits of the instruction asthey appear in memory words or in a control register.The bits of the instructions are divided into groups calledfields. The most common fields found in instructionformat are:1. An Operation code field that specifies the operation tobe performed.2. An address field that designates a memory address or aprocessor register.3. A mode field that specifies the way the operand or theeffective address is determined.Computer may have instructions of several differentlength containing varying number of addresses. The no.of address field in the instruction format of a computerdepends on the internal organization of its registers.

Addressing Modes

RISC vs CISCRISCCISC Emphasis on hardware Emphasis on software Includes multi-clock Single-clock,complex instructions Memory-to-memory:reduced instruction only Register to register:"LOAD" and "STORE“"LOAD" and "STORE“incorporated in instructionsare independent instructions Small code sizes,high cycles per second Transistors used for storingcomplex instructions Low cycles per second,large code sizes Spends more transistorson memory registers

CISC Characteristics The instructions in a typical CISC processor provide directmanipulation of operands residing in a memory. The majorcharacteristics of CISC architecture are:1. A large number of instructions – typically from 100 to 250instructions2. Some instruction that perform specialized tasks and are usedinfrequently3. A large variety of addressing modes – typically from 5 to 20different modes4. Variable – length instruction format5. Instruction that manipulate operands in memory6. Instructions are complex7. Example - Pentium processors.

RISC Characteristics The concept of RISC architecture involves an attempt toreduce execution time by simplifying the instructionset of the computer. The major characteristics of aRISC processor are:1. Relatively few instructions2. Relatively few addressing modes3. Memory access limited to load and store instructions4. All operation done within the register of the CPU5. Fixed length, easily decoded instruction format.6. Single cycle instruction execution7. Hardwired rather than Micro programmed control8. Instructions are simple9. Example:- Power PC.

General structure for Microprogrammed control gister

General structure for hardwired control unitStatussignalsSequential logiccircuitInstructionregisterControlsignals

The hardwired approach views the controller as a sequential logic circuit orfinite state machine that generates specific sequences of control signals Advantage: 1. reduces the number of components2. speed is fast Disadvantage : Once the unit is constructed the only way to implementchanges in control unit behaviour is by redesigning the entire unit

What is pipelining?Pipelining is a technique of decomposing asequential process into sub-operations, witheach sub-process being executed in a specialdedicatedsegmentsthatoperatesconcurrently with all other segments. Apipeline can be visualized as a collection ofprocessing segments through which binaryinformation flows. The name pipeline impliesa flow of information analogous to anindustrial assembly line.

Pipelining Example Sub-operation performed in each segment ofthe pipeline are as follows:R1 Ai, R2 BiInput Ai and BiR3 R1 * R2, R4 Ci Multiply and input CiR5 R3 R4Add Ci to product

Pipelining ProcessingAiBiR1CiR2MultiplierR3R4AdderR5

Different Types of Pipelining 1 Arithmetic pipeline2 Instruction pipeline3 RISC pipeline4 Vector processing

Arithmetic Pipeline An arithmetic pipeline divides an arithmeticoperation into sub-operation for execution inthe pipeline segments.Pipeline arithmetic units are usually foundin very high speed computers. They are usedto implement floating-point operations,multiplication of fixed point numbers, andsimilar computations encountered in specificproblems.

Pipeline for floating point Addition and SubtractionSegment 1ExponentMantissaRRCompareexponents bysubtractionRSegment 2ChooseexponentsAlign mantissaa2a1R

a1a2Add or subtractmantissaSegment 3Segment 4RRAdjust exponentNormalizeresultRR

Unit - 04Computer Arithmetic&I/O Techniques

Combinational ALU

Combinational ALU

Combinational ALU

Combinational ALU

Sequential ALU

Sequential ALU Basic Design

Sequential ALU

Sequential ALU

Register File

Register File

Floating Point Arithmatic

Basic Operation

Basic Operation

Basic Operation

Basic Operation

Algorithm for floating point Operation

Pipelined floating point operation

I/O InterfaceInput-Output interface provides a method fortransferring information between internal storageand external I/O devices. The purpose of thecommunication link is to resolve the differencesthat exist between the central computer andeach peripheral. The major differences are :1. Peripherals are electromechanical andelectromagnetic devices and their manner ofoperation of the CPU and memory, which areelectronic devices. Therefore, a conversion ofsignal values may be required.

2. The data transfer rate of peripherals is usuallyslower than the transfer rate of the CPU, andconsequently, a synchronization mechanismmay be needed.3. Data codes and formats in peripherals differfrom the word format in the CPU andmemory.4. The operating modes of peripheral aredifferent from each other and each must becontrolled so as not to disturb the operationof other peripherals connected to the CPU.

To resolve these differences computersystems include special hardware componentsbetween the CPU and peripherals to superviseand synchronize all input and output transfers.These components are called “interface units”because they interface between the processorbus and peripheral device. In addition eachdevice may have its own controller thatsupervises the operation of the particularmechanism in the peripherals.

I/O Bus and Interface ModulesI/O terfaceinterfaceKeyboardand nection of I/O bus to input-output devices.

I/O CommandsThere are four types of commands that aninterface may receive. They are classified as control,status, data output, and data input.1. Control Command:- A control command is issued toactivate peripheral and inform it what to do.For example:- A magnetic tape unit may beinstructed to backspace the tape by one record, torewind the tape, or to start the tape moving in theforward direction.2. Status Command:- A status command is used to testvarious status conditions in the interface and theperipheral.

For example:- the computer may wish tocheck the status of the peripheral before atransfer is initiated. During the transfer, one ormore errors may occur which are detected bythe interface. These errors are designated bysetting bits in a status register that theprocessor can read at certain intervals.3. Output data:- It causes the interface torespond by transferring data from the bus intoone of its register. Consider an example with atape unit. The computer starts the tapemoving by issuing a control command.

The processor then monitor the status of thetape by means of a status command. Whenthe tape is in the correct position theprocessor issues a data output command. Theinterface responds to the address andcommand and transfers the information fromthe data lines in the bus to its buffer register.The interface then communicates with thetape controller and sends the data to bestored on tape.

4. Input data:- The data input command is theopposite of the data output. In this case theinterface receive an item of data from theperipheral and places it in its buffer register.The processor checks if data are available bymeans of a status command and then issues adata input command. The interface places thedata on the data lines, where they areaccepted by the processor.

Example of I/O InterfacePort AregisterBidirectionalI/O dataBus buffersb u sData busCSRS0I/O writeRDWRControlregisterStatusregisterII/O readeRegular selectTimingandcontroln tRS1r n alChip selectPort BregisterTo CPUTo I/P devicesI/O dataControlStatus

Example of I/O Interface unitCSRS1RS0Register selected0**100None: data bus in highimpedancePort A register101Port B register110Control register111Status register

Synchronization The process that communicate, do so through asynchronization mechanism. A process executeswith unpredictable velocity and generates eventsand actions that must be recognized by other cooperating processes. The set of constraints on theordering of these events constitutes the set ofsynchronization required for the operatingprocesses. The synchronization technique is usedto delay execution of a process in order to satisfysuch constraints.

In a multiprocessor system, processes canexecute concurrently until they need tointeract. Planned and controlled interaction isknown as process communication or processsynchronization. Process communication musttake place through shared or global variables.Co-operating process must communicate tosynchronize or limit their concurrency.

Two types of synchronization are generallyneeded while using shared variable.1. Mutual Exclusion :- Mutual exclusion ensuresthat a physical or virtual resource is heldindivisibly.2. Condition Synchronization :- When a shareddata object is in a state that is not appropriatefor executing a given operation, any processwhich attempts such an operation must bedelayed. Such operation must be delayed untilthe state of data objects to the desired value asa result of other process being executed. Thistype of synchronization is called “ Conditionsynchronization”.

Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA)

Three Techniques for Input of a Block of Data

Programmed I/O CPU has direct control over I/O– Sensing status– Read/write commands– Transferring data CPU waits for I/O module to completeoperation Wastes CPU time

Programmed I/O - detail CPU requests I/O operationI/O module performs operationI/O module sets status bitsCPU checks status bits periodicallyI/O module does not inform CPU directlyI/O module does not interrupt CPUCPU may wait or come back later

Programmed I/OProgrammed I/O operations are the result ofI/O instructions written in the computer program.Each data item transfer is initiated by aninstruction in the program. Usually the transfer isto read and from a CPU register and peripheral.Other instructions are needed to transfer thedata to and from CPU and memory. Transferringdata under program control requires constantmonitoring of the peripheral by the CPU. Once adata transfer is initiated, the CPU is required tomonitor the interface to see when a transfer canagain be made.

Example of Programmed I/OIn the programmed I/O method, the I/O devicesdoes not have direct access to memory. Atransfer from an I/O device to memory requiresthe execution of several instruction by the CPU,including an input instruction to transfer the datafrom the device to the CPU and a storeinstruction to transfer the data from the CPU tomemory. Other instruction may be needed toverify that the data are available from the deviceand to count the numbers of words transferred.

An example of data transfer from an I/Odevice through an interface into the CPU isshown in figure:-Data busAddress busCPUInterfaceI/O busData registerData validI/O readI/O writeStatusregisterFDataacceptedI/Odevice

Read data registerCheck flag bit 0Flagno 1OperationcompleteRead status registeryesTransfer data to memoryContinue with programFlowchart for CPU program to input data

I/O Commands CPU issues address– Identifies module (& device if 1 per module) CPU issues command– Control - telling module what to do e.g. spin up disk– Test - check status e.g. power? Error?– Read/Write Module transfers data via buffer from/to device

Addressing I/O Devices Under programmed I/O data transfer is verylike memory access (CPU viewpoint) Each device given unique identifier CPU commands contain identifier (address)

I/O Mapping Memory mapped I/O– Devices and memory share an address space– I/O looks just like memory read/write– No special commands for I/O Large selection of memory access commands available Isolated I/O– Separate address spaces– Need I/O or memory select lines– Special commands for I/O Limited set

Memory Mapped and Isolated I/O

Interrupt MechanismData transfer between the CPU and I/Odevice is initiated by the CPU. However, the CPUcan not start the transfer unless the device isready to communicate with the CPU. Thereadiness of the device can be determined froman interrupt signal. The CPU respond to theInterrupt request by storing the return addressfrom PC into a memory stack and then theprogram branches to service routine thatprocesses the required transfer.

Priority InterruptA priority interrupt is a system that establishes apriority over the various sources to determine whichcondition is to be services first

1. Computer Architecture and organization – John P Hayes, McGraw Hill Publication 2 Computer Organizations and Design- P. Pal Chaudhari, Prentice-Hall of India Name of reference Books: 1. Computer System Architecture - M. Morris Mano, PHI. 2. Computer Organization and Architecture- William Stallings, Prentice-Hall of India 3.

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