A Comparison Of The MC9S12DP256 (mask Set 0K36N) Versus .
EB376/DA comparison of the MC9S12DP256(mask set 0K36N) versus the HC12Engineering BulletinEB376January 8, 2001
List of SectionsList of SectionsList of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Central Processing Unit (CPU) . . . . . . . . . . . . . . . . . . . . 13Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Flash Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Port Integration Module (PIM) . . . . . . . . . . . . . . . . . . . . 27Clocks and Reset Generator (CRG) . . . . . . . . . . . . . . . 29Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . 31Enhanced Capture Timer (ECT) . . . . . . . . . . . . . . . . . . . 37Serial Communications Interface (SCI). . . . . . . . . . . . . 41Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . 45Inter IC Bus (IIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49msCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Motorola, Inc., 2000MOTOROLAEB3763
Analog-to-Digital Converter (ATD) . . . . . . . . . . . . . . . . 55Byte Data Link Controller (BDLC) . . . . . . . . . . . . . . . . . . 67Background Debug Module (BDM) . . . . . . . . . . . . . . . . 73Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77EB3764MOTOROLA
Table of ContentsTable of ContentsList of SectionsTable of ContentsIntroductionContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Conventions Used Throughout This Document . . . . . . . . . . . . . . . . . 10Module Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Central ProcessingUnit (CPU)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13MOVB/MOVW instructions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Instructions with cycle count reduced by 1 . . . . . . . . . . . . . . . . . . . . . 14Instructions with cycle count reduced by 2 . . . . . . . . . . . . . . . . . . . . . 15Instructions with cycle count increased by 1 . . . . . . . . . . . . . . . . . . . 15Instructions with operations re-ordered . . . . . . . . . . . . . . . . . . . . . . . 15HardwareContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 18MC9S12DP256 Power Supply Detail . . . . . . . . . . . . . . . . . . . . . . . . . 20EEPROM MemoryContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23MC9S12DP256 Versus 68HC912DG128 . . . . . . . . . . . . . . . . . . . . . . 24Flash MemoryContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25MC9S12DP256 Versus 68HC912DG128 . . . . . . . . . . . . . . . . . . . . . . 26Port IntegrationModule (PIM)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27I/O port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28EB376MOTOROLA5
Clocks and ResetGenerator (CRG)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Clocks and Reset Generator (CRG) . . . . . . . . . . . . . . . . . . . . . . . . . . 29MC9S12DP256 Versus 68HC912DG128 . . . . . . . . . . . . . . . . . . . . . . 30Pulse WidthModulator (PWM)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 31Comparison of PWM Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Enhanced CaptureTimer (ECT)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 38Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38SerialCommunicationsInterface (SCI)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 42Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42Serial PeripheralInterface (SPI)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 46Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Inter IC Bus (IIC)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Summary of Additional Functions on the MC9S12DP256 . . . . . . . . . 50Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50msCANContents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 52Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Analog-to-DigitalConverter (ATD)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 56Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58EB3766MOTOROLA
Byte Data LinkController (BDLC)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . .Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67676869Background DebugModule (BDM)Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . .Register Block Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Breakpoint registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7373747576Literature UpdatesLiterature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . . . 78EB376MOTOROLA7
EB3768MOTOROLA
IntroductionIntroductionContentsOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Conventions Used Throughout This Document . . . . . . . . . . . . . . . . . 10Module Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11OverviewThis document compares the various modules of the MC9S12DP256(mask 0K36N) with equivalent modules in the HC12 family and is meantto be used as a guide in conjunction with the appropriate device DataBooks.It is structured (where possible) to align with the Chapter structure of theMC9S12DP256 Technical Data Book, MC9S12DP256/D.Generally, the first subsection of each chapter highlights the differencesin features of the two devices. Where appropriate, this is followed by acomparison of the individual registers and bits.The Star12 (MC9S12DP256) design methodology includes a greatlyimproved highly flexible I/O structure. On the HC12, port control ismanaged by register bits in the appropriate peripheral modules. On theMC9S12DP256, the functionality of these bits has been greatlyexpanded and centralized in the Port Integration Module (PIM).1-introMOTOROLAEB3769
Conventions Used Throughout This DocumentIn the register comparisons, the bits highlighted in bold italics indicatethe differences between the corresponding registers of the devicesbeing compared.Registers not identified remain identical.Port I/O control bits are not included in the register comparisons as theirfunctionality has been transferred to the PIM. For detail on the I/Ophilosophy and Port registers refer to the Port Integration Module (PIM)chapter in this document and in the MC9S12DP256 Technical DataBook, MC9S12DP256/D.EB376102-introMOTOROLA
Module Base AddressesThe following table lists the base addresses for each module on theMC9S12DP256 and their equivalent on the 68HC912DG128 (or68HC912B32 in the case of the BDLC module).Table 1 Module Base AddressesBase 6BKPT 20 28CRG(CGM) 34 34ECT 80 40ATD0 60 80PWM 40 A0SCI0 C0 C8SCI1 C8 D0SPI0 D0 D8IIC E0 E0BDLC F8 (on 68HC912B32 not68HC912DG128) E8SPI1— F0SPI2— F8Flash F4 100EEPROM F0 110ATD1 1E0 120MSCAN0 100 140MSCAN1 300 180MSCAN2— 1C0MSCAN3— 200PIM— 240MSCAN4— 280BDM FF00 FF00EB37611
EB376124-introMOTOROLA
Central Processing Unit (CPU)Central Processing Unit (CPU)ContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13MOVB/MOVW instructions: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Instructions with cycle count reduced by 1 . . . . . . . . . . . . . . . . . . . . . 14Instructions with cycle count reduced by 2 . . . . . . . . . . . . . . . . . . . . . 15Instructions with cycle count increased by 1 . . . . . . . . . . . . . . . . . . . . 15Instructions with operations re-ordered . . . . . . . . . . . . . . . . . . . . . . . . 15Introduction Identical programmers model. Pipe increased to 3 stages (from 2 plus latch) giving deterministicbehavior. All instructions implemented using same Mnemonics & Op codes. Further detail can be found in the Star12 CPU Reference Guide.MOVB/MOVW instructions:On the HC12, when using the PC relative addressing mode, an offsetis required to be added to/subtracted from the displacementcomputed from the base address, which is equal to the address of thenext instruction. This is detailed in chapter 3.9.1 of the CPU12Reference Manual (CPU12M/AD). It is handled transparently byassemblers and compilers for the HC12 today.1-cpuMOTOROLAEB37613
On the Star12 this is no longer the case. This base is the same forboth source and destination operands and any assemblers/compilersthat calculate an offset will generate incorrect code.ExamplesMOVBDC.B2,PCR, 10001,2,3,4,5,6,7,8,9STAR12: 1000 is written to 3HC12: 1000 is written to 1The other way roundMOVBTEMP 1000,2,PCRDS.B10STAR12: Value read at 1000 is moved to TEMP 2HC12: Value read at 1000 is moved to TEMP 5It is important to ensure that a compiler or assembler is Star12compliant on this point.Instructions with cycle count reduced by IEB37614EXT, IDX, IDX1, IDX2 (7,7,7,8)[D,IDX], [IDX2]IDX (DES is assembled as LEAS)IDX (ABX is assembled as LEAX)IDX (ABY is assembled as LEAY)[D,IDX], [IDX2][D,IDX], [IDX2][D,IDX], [IDX2][D,IDX], [IDX2][D,IDX], [IDX2][D,IDX], [IDX2]INH (entering)INH (mapped to multiple op codes)INH (entering)2-cpuMOTOROLA
Instructions with cycle count reduced by 2BRCLRIDX2BRSETIDX2MULINHTBLIDXInstructions with cycle count increased by 1NOTE:RTCINHRTIINH (with pending interrupt)STOPINH (exiting)WAIINH (interrupt occurs)The increase in RTC is compensated for by the reduction in the numberof cycles in the CALL instruction. Effective throughput is the samenumber of cycles except CALL IDX2, RTC.Instructions with operations re-orderedIn order to make the cycle by cycle operation the same for similarinstructions, the free cycle "f" has been moved to the last operation(133 cases). [Pf at end of instruction even number of cycles]In order to make the cycle by cycle operation the same for similarinstructions, the optional program word fetch cycle "O" has beenmoved to the last operation (72 cases). [PO at the end of instruction odd number of cycles]In 14 other cases the cycle by cycle sequence has been modified toend in the program word fetch "P" (no "f" or "O" cycles in instructions).A total of 219 cycle order changes have been made in the CPUoperation. These should be transparent for most applications.3-cpuMOTOROLAEB37615
EB376164-cpuMOTOROLA
HardwareHardwareContentsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Summary of Additional Functions on MC9S12DP256 . . . . . . . . . . . . 18MC9S12DP256 Power Supply Detail . . . . . . . . . . . . . . . . . . . . . . . . . 20IntroductionThe MC9S12DP256 has many more (multiplexed) peripheral modulesthan the 68HC912DG128 and a significantly different power supplystructure to cater for it’s low voltage, high performance 0.25µ core logicand 5V compatible, highly flexible I/O ports.This requires a different printed circuit board (PCB) layout.Hybrid layouts, supporting both foot prints, can be achieved using acombination of jumpers, pull-up/down resistors and solderable links butthese are likely to result in significant compromises in performance andEMC.This section compares the PCB requirements of the MC9S12DP256with those of the 68HC912DG128. The first section highlights thedifferences in features, including some considerations on power supplylayout and decoupling.1-hwareMOTOROLAEB37617
Summary of Additional Functions on MC9S12DP256 ATDVRL and VRH voltage reference inputThe MC9S12DP256 requires a single ATD voltage reference inputand reference ground pin shared by both converters as opposedto the separate reference connections for each converter on the68HC912DG128. Pin out changes and Package detailsThe mechanical package is identical (112 pin LQFP, Case 987) tothe 68HC912DG128 but many pins with equivalent functionalityhave changed location. ATD channel conventionOn the MC9S12DP256, the channels for ATD1 are referred to inthe documentation by AN08–AN15 instead of AN10–AN17 as onthe 68HC912DG128. This gives clear and consistent channelnumbering from 00 on up allowing for future implementations ofconverters with greater than 8 input channels.Physically, the channels of ATD1 (AN08–AN15) remain interlacedwith the channels of ATD0 (AN00–AN07) as on the68HC912DG128 but their location relative to pin 1 has moved. EXTAL pinThe oscillator is part of the higher frequency logic, hence EXTALinput is limited to 2.5V signals. XTAL pinThe XTAL output can be buffered with a high-impedance buffer todrive the EXTAL input of another device. On the MC9S12DP256,the maximum output voltage of this pin is VDDPLL (2.5V). Port KThe MC9S12DP256 has 6 pins on Port K to support 64 x 16Kpages of external memory (1 Mbyte).EB376182-hwareMOTOROLA
VSTBY pinThere is no RAM standby function on the MC9S12DP256, so theVSTBY pin has been removed. MODC pinPreviously referred to as SMODN, this is for factory test only. Thepin continues to act as the background debug pin in userapplications. TEST pinThis is a ‘factory-test’ only input and MUST be grounded or pulledto ground with a pull-down resistor in all other applications. ECLK outputECLK control is significantly different. Please refer to the Port Eand PEAR register sections of the MC9S12DP256 Technical DataBook, MC9S12DP256/D for details. Port E7 pinOn the MC9S12DP256, the alternate functionality of this pin haschanged – (CAL function not available, *ECLK not available, *DBEnot available). Pulling PE7 (*XCLKS) low during the reset phasebypasses the internal low current oscillator and an internal buffer(2.5V) driven by EXTAL feeds the internal clocks. Port K7 pin.On the MC9S12DP256, this pin is used as an emulation chipselect signal for the emulation of the internal memory expansionor as general purpose I/O, depending upon the state of the EMKbit in the MODE register.The value on this pin during reset determines the state of theROMON bit during reset into all expanded modes. Flash programming voltageOn the MC9S12DP256, the non-volatile Flash memory is ‘5V only’and does not require an external VFP Pin as on the68HC912DG128; this removes the need for an external chargepump.3-hwareMOTOROLAEB37619
MC9S12DP256 Power Supply DetailThe MC9S12DP256 has an internal 2.5V regulator to supply the highperformance core logic as opposed to the 5V only logic supply of the68HC912DG128. Some key points are highlighted here, but it isessential that the Voltage Regulator (VREG) Chapter of theMC9S12DP256 Technical Data Book be reviewed in detail. VREGEN PinI/P used to define the standby operating mode of the internalvoltage regulator. VDD1 & VDD2 Pins2.5V supply pins for the core logic which require decoupling. VDDPLL PinOn the 68HC912DG128, this pin, when grounded, caused the PLLcircuitry to be bypassed. On the MC9S12DP256, it is a 2.5V(internal) supply pin for the high performance PLL logic and mustNOT be grounded (or connected to 5V). Layout considerationsAvoid current loops in power supply tracks.All ground pins (VSS**) must be connected externally.VDDA/VSSA and VRH/VRL supplies MUST be clean.Connection for external power supply monitor should be close toVDDA. Further Decoupling GuidelinesFor all capacitors in the nF range, it is essential to use a type withlow ESR.All recommendations are load and PC board routing dependent.– VDDXThis is highly dependent on the type of load and switchingfrequency since VDDX supplies only the 5V drivers in Ports J,K, T, P, M & S.EB376204-hwareMOTOROLA
Start with 47–220nF and add 10µF if big loads are switchedand the supply track is long (highly inductive).All fast switching peripherals, PWM, timer, CAN etc. arelocated on this bus.– VDDAHere a good noise decoupling is key; the internal load is almoststatic.Recommended 22nF–100nF.– VDD1,2These are the outputs of the internal voltage regulator.Recommended 47–220nF.– VDDRThis pin supplies the internal regulator as well as the I/O portsA, B, E & H.Two alternatives:a. Expanded busHigh peak current through Port A, B, E mainly.Recommended 100nF 10uF.b. Single chip mode.Here we have a load dependent variant. Since the are nofast switching peripherals on
14 MOTOROLA On the Star12 this is no longer the case. This base is the same for bothsourceand destinationoperands and any assemblers/compilers that calculate an offset will generate incorrect code. Examples MOVB 2,PCR, 1000 DC.B 1,2,3,4,5,6,7,8,9 STAR12: 1000 is written to 3 HC12: 1000 is written to 1 The other way round MOVB 1000,2,PCR TEMP .
May 02, 2018 · D. Program Evaluation ͟The organization has provided a description of the framework for how each program will be evaluated. The framework should include all the elements below: ͟The evaluation methods are cost-effective for the organization ͟Quantitative and qualitative data is being collected (at Basics tier, data collection must have begun)
Silat is a combative art of self-defense and survival rooted from Matay archipelago. It was traced at thé early of Langkasuka Kingdom (2nd century CE) till thé reign of Melaka (Malaysia) Sultanate era (13th century). Silat has now evolved to become part of social culture and tradition with thé appearance of a fine physical and spiritual .
On an exceptional basis, Member States may request UNESCO to provide thé candidates with access to thé platform so they can complète thé form by themselves. Thèse requests must be addressed to esd rize unesco. or by 15 A ril 2021 UNESCO will provide thé nomineewith accessto thé platform via their émail address.
̶The leading indicator of employee engagement is based on the quality of the relationship between employee and supervisor Empower your managers! ̶Help them understand the impact on the organization ̶Share important changes, plan options, tasks, and deadlines ̶Provide key messages and talking points ̶Prepare them to answer employee questions
Dr. Sunita Bharatwal** Dr. Pawan Garga*** Abstract Customer satisfaction is derived from thè functionalities and values, a product or Service can provide. The current study aims to segregate thè dimensions of ordine Service quality and gather insights on its impact on web shopping. The trends of purchases have
Chính Văn.- Còn đức Thế tôn thì tuệ giác cực kỳ trong sạch 8: hiện hành bất nhị 9, đạt đến vô tướng 10, đứng vào chỗ đứng của các đức Thế tôn 11, thể hiện tính bình đẳng của các Ngài, đến chỗ không còn chướng ngại 12, giáo pháp không thể khuynh đảo, tâm thức không bị cản trở, cái được
MOTOROLA A Comparison of the MC9S12DP256 (Mask Set 0K36N) Versus the HC12 5 Introduction Overview This document compares the various modules of the MC9S12DP256 (mask 0K36N) with equivalent modules in the HC12 family and is meant to be used as a guide in conjunction with the appropriate device Data Books.
Le genou de Lucy. Odile Jacob. 1999. Coppens Y. Pré-textes. L’homme préhistorique en morceaux. Eds Odile Jacob. 2011. Costentin J., Delaveau P. Café, thé, chocolat, les bons effets sur le cerveau et pour le corps. Editions Odile Jacob. 2010. Crawford M., Marsh D. The driving force : food in human evolution and the future.
