Techniques For High Speed ADC PCB Layout - Analog Devices

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AN-1142APPLICATION NOTEOne Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.comTechniques for High Speed ADC PCB Layoutby Rob ReederINTRODUCTIONfrom the die to a central point under the part. Note the lack ofground pins in many converters and amplifiers today. TheEPAD is the reason why.In today’s industry, the layout of the system board has becomean integral part of the design itself. Therefore, it is of paramountimportance that the designer has an understanding of themechanisms that affect the performance of a high speed signalchain design.The key is to tie this pin down, that is, soldered well to the PCBto make a robust electrical and thermal connection. When thisconnection is not solid, havoc can occur. In other words, thedesign may not work.There are many options to consider when it comes to layingout a printed circuit board (PCB) in a high speed analog signalchain design. Some options matter more than others, and someare application dependent. In the end, the answer varies but inall cases the designer should try to lean on the error of bestpractice without becoming overly critical regarding every layoutdetail. This application note provides information that may beuseful when starting the next high speed design.Achieving the Best ConnectionThere are three basic steps to take to achieve the best connection, electrically and thermally, with the EPAD. First, ifpossible, replicate the EPAD on each PCB layer. Doing socreates a thick thermal connection to all grounds and groundlayers so that the heat can dissipate and spread out quickly. Thisis pertinent for high power parts and for applications that havehigh channel counts. Electrically, this gives a good equal connection to all the ground layers.EXPOSED PADDLESExposed paddles, or EPADs, are sometimes overlooked; however, they are essential to getting the most performance outof the signal chain as well as getting the most heat out ofthe device.One can even replicate the EPAD on the bottom layer (seeFigure 1). This can serve as a thermal relief ground point fordecoupling and a placeholder to attach a heat sink on thebottom side.The exposed paddle, referred to at Analog Devices, Inc., asPin 0, is the paddle found underneath most parts today. Thisis an important connection because it ties all internal groundsADCEPADLAYER 1 - TOP SIGNALLAYER 2 - GROUND1EPADLAYER 3 - POWER1DIELECTRICLAYERSVIASEPADLAYER 4 - POWER2EPADDECOUPLING CAPDECOUPLING CAPFigure 1. Exposed Pad Layer Layout ExampleRev. 0 Page 1 of 810484-001LAYER 5 - GROUND2LAYER 6 - BOTTOM SIGNAL

AN-1142Application NoteTABLE OF CONTENTSIntroduction . 1Plane Coupling.4Exposed Paddles . 1Splitting Grounds .5Revision History . 2Conclusion.6Decoupling and Plane Capacitance . 3References .6REVISION HISTORY1/12—Revision 0: Initial VersionRev. 0 Page 2 of 8

Application NoteAN-114210484-002NOTICE THE BUBBLES.Figure 2. Poor EPAD Layout Examplethe question remains: how many capacitors are needed?A good deal of the relevant literature states that lowering thepower delivery system (PDS) impedance must be done withmany capacitors and many values; however, that is not entirelytrue. Instead, simply select the right values and the right kindsof capacitors to make the PDS impedance low.25DECOUPLING CAPACITANCEPLANECAPACITANCE2.5IMPEDANCE (Ω)Second, partition the EPAD into equal segments like a checkerboard. Use either a silkscreen crosshatch on the open EPAD orsolder mask. This ensures a robust connection between the partand the PCB. During the reflow assembly process, there is noway to guarantee how the solder paste will flow and ultimatelyconnect the part to the PCB. It is possible that the connectionwould be present, but not evenly distributed. It is possible toget only one connection and that connection could be smallor, worse yet, situated in a corner. Dicing the EPAD into smallerpartitions ensures a connection point in each separate areagiving a more robust and evenly connected EPAD (see Figure 2and Figure 3).0.250.02510µF ONLYHALF 0.1µF HALF 10µFALL CAP VALUES10mΩ REFERENCE0.00250.000025100k1M10M100MFREQUENCY (Hz)1G10G10484-0040.0002510484-003Figure 4. Capacitor ExampleFigure 3. Better EPAD Layout ExampleFinally, make sure that each of those partitions has viaconnections to ground. Usually, the partition is big enoughso that several vias can be placed. Make sure each of thesevias is filled with solder paste or epoxy before assembly.This important step ensures the EPAD solder paste will notbe reflowed into those via voids thus possibly interferingwith proper connection.DECOUPLING AND PLANE CAPACITANCESometimes engineers lose sight of why decoupling is used.Simply spreading many value capacitors across a board givesway to a lower impedance supply connection to ground. YetFor example, consider designing a 10 mΩ reference plane,as shown in Figure 4. As indicated by the red curve, manycapacitor values are employed on a system board, 0.001 µF, 0.01µF, 0.1 µF, and so on. One can certainly lower the impedanceacross a 500 MHz frequency range; however, look at the greencurve. In this case, there are only 0.1 µF and 10 µF capacitorsused in the same design. This proves that if the right capacitorsare used, then not as many capacitors values are needed. Thisalso helps save on placement and BOM costs.Note that not all capacitors are necessarily created equal evenwhen purchased from the same vendor; make, size, and stylematter. If the right capacitors are not used, and this applies tomany capacitors or even just a few different types, then theresult can have the opposite effect on the PDS than intended.The result may be inductance loops. Incorrect placement ofRev. 0 Page 3 of 8

AN-1142Application Notecapacitors, or just using different capacitor makes and modelsthat respond differently over frequency in the system, canresonate against each other (see Figure 5).25LLOOP.SMAPORT2WIDTHCAP2LENGTH0.250.0252 CAPS RESONATING DUETO LOOP 025100k1M10M100MFREQUENCY (Hz)1G10G10484-005GND2Figure 5. Resonating CapacitorsTaking the time to understand the frequency response of thecapacitor types employed in the system is crucial. Do not undoall the hard work it took to design a low impedance PDS systemby using just any capacitor.High Frequency Plane Capacitance of a PDSTo design a good PDS, use a variety of capacitances (seeFigure 4). Typical capacitor values used on the PCB only keepthe impedance low between the frequency range of dc, or neardc, to about 500 MHz. Above 500 MHz frequencies the capacitance is dictated by the internal capacitance developed bythe PCB. Note that stacking the power and ground plane tightlycan help.Design a PCB stack that supports a large plane capacitance. Forexample, a 6-layer stack may consist of a top signal, ground1,power1, power2, ground2, and bottom signal. Specify ground1and power1 to be close in the stack—separating them by 2 milsto 4 mils forms an inherent high frequency plane capacitor.What is best about this capacitor is that it is free; it need only tobe specified in the PCB fabrication notes. If the power planesmust be divided, with multiple VDD rails on the same plane,use as much of the plane as possible. Do not leave voids, but bemindful of sensitive circuitry. This maximizes the capacitancefor that VDD plane.If the design allows for extra layers—from six to eight in theprior example—put those two extra ground planes betweenpower1 and power2. This doubles the inherent capacitancein the stack given the same 2-mil to 3-mil core spacing (seeFigure 6 for an example).SOME EXAMPLES:L 2IN, W 2.5IN, H1 3MIL, CTOTAL 3.2nFL 10IN, W 10IN, H1 3MIL, CTOTAL 64.2nFL 2IN, W 2.5IN, H1 10MIL, CTOTAL 1.0nFL 10IN, W 10IN, H1 10MIL, CTOTAL 5.2nFTHEREFORE, ADDING A SECOND GND PLANE INCREASES (DOUBLES)INNER PLANE CAPACITANCE.Figure 6. High Frequency Plane Capacitance ExamplesOften overlooked, the task of the PDS is critical to minimizethe voltage ripple that occurs in response to supply currentdemand. All circuits require current, some more than othersand some at faster rates than others. A low impedance power orground plane with adequate decoupling and a good PCB stackcan help minimize the voltage ripple that occurs as a result ofthe circuit current demands. For example, if the system designhas 1 A of switching current and the PDS is designed to have a10 mΩ impedance based on the decoupling strategy used, thenthe maximum voltage ripple is 10 mV. It is that simple, V IR.With the perfect PCB stack up, the high frequency range can becovered, while the use of traditional decoupling at both theentry point, where the power plane originates, and around thedevices that run at high power or surge currents can cover thelower frequency range ( 500 MHz). This ensures the lowestPDS impedance across the entire frequency range. It is notnecessary to sprinkle capacitors everywhere, butting them rightup against every IC, thus breaking multiple manufacturingrules. If drastic measures of this sort are required, then this isan indication that something else is going on in the circuit.PLANE COUPLINGIt is inevitable that some layouts have a circuit plane overlapping another (see Figure 8). In some cases, this might be asensitive analog plane (power or ground or signal, for example)where the next layer underneath is a noisy digital plane.Rev. 0 Page 4 of 810484-006IMPEDANCE (Ω)SMAPORT1CAP12.5This can be much easier to design as opposed to adding morediscrete high frequency capacitors to keep the impedance low athigh frequencies.

Application NoteAN-1142ANALOGLAYER 1LAYER 2DIGITALLAYER 210484-007ANALOGLAYER 1DIGITALFigure 7. Cross Coupled Plane ExampleThis is commonly ignored because the noisy plane is on anotherlayer (below) the sensitive analog layer. However, a simple testmay prove otherwise. Take one of the layers and inject a signalon either plane. Next, connect the other layer that cross couplesthat adjacent layer to a spectrum analyzer. The amount of signalcoupling through to the adjacent layer can be seen in Figure 8.Even if they are separated by 40 mil, it is still a capacitor insome sense; therefore, it still couples signals through to theadjacent plane at some frequency.0ISOLATION (dB)Keep this in mind when noisy spurs are seen coupling in thefrequency spectrum of interest. Sometimes layouts dictateunintended signals or planes to be cross coupled to a differentlayer. Again, just keep this in mind when debugging sensitivesystems. The issue may lay one layer below.SPLITTING GROUNDSThe most popular question among analog signal chaindesigners is: should the ground plane be split into a AGND andDGND ground plane when using an ADC? The short answer is:it depends.–20–40The long answer is: not usually. Why not? In most situations,a split ground plane can cause more harm than good becauseblindly splitting the ground plane only serves to increase theinductance for the return current.–60–801M10M100MFREQUENCY (Hz)1G10G10484-008–100–120100kIgnoring this type of cross plane coupling may neither makethe system fail nor cripple the design. Simply note that morecoupling exists between two planes than one may assume.Figure 8. Measured Cross Coupled Plane ResultsFigure 8 shows one such example. Assume, for example, thata noisy digital plane on one layer has a 1 V signal that switchesat a high speed. This means the other layer will see 1 mV ofcoupling ( 60 dB isolation). To a 12-bit ADC with a 2 V p-pfull-scale swing, this is 2 LSBs of coupling. This may be finefor a particular system, but keep in mind that as the system’ssensitivity increases by two bits, from 12 bits to 14 bits, thesensitivity of this coupling only quadruples to 8 LSBs.Consider the equation V L(di/dt). As the inductance isincreased, so is the voltage noise. As the inductance increases,so does the PDS impedance, which the designer worked so hardto keep low. As the request for increasing ADC sampling ratescontinues, there is a minimal amount of effort the designer canmake to decrease the switching current (di/dt). Thus, unlessthere is a reason to split the ground plane, keep those groundsconnected.Rev. 0 Page 5 of 8

AN-1142Application NoteOne tie point on the PCB often ends up being the optimumplace for the return current to pass without reducing performance or forcing return currents to couple to sensitive circuitry.If this tie point is at, near, or under the converter, it is notnecessary to split the grounds.CONCLUSIONPOWERLayout considerations are confusing because there are manydiffering opinions on the best strategy. Techniques and philosophy tend to become part of the design culture of a company.Engineers, who tend to use what worked in their previousdesigns, can be reluctant to change or try new techniques dueto time-to-market pressures. This leaves the designer in theposition of weighing trade-offs with risk until something goeswrong in the system.DIGITALAINCLOCKAt the evaluation board, module, and system level, a simplesingle ground works best. Good circuit partitioning is key. Thisalso extends into plane and adjacent layer layout. Keep in mindthat cross coupling can occur if sensitive planes are just abovethose noisy digital planes. Assembly is important too; use thefabrication notes given to the PCB or assembly house to youradvantage to ensure a solid connection between the IC EPADand the PCB.IDIA 4-009 VDFigure 9. Example of Good Circuit PartitioningGood circuit partitioning is key to not splitting ground planesas shown in Figure 9. Notice that if a layout allows you to keepthe respective circuits in their own areas then there is no needto split the ground. Partitioning this way allows for a starground, which keeps return currents localized to that particularcircuit section.For example, one reason to split ground planes occurs when aform factor restriction prohibits good layout partitioning.This may be because the dirty bus supplies or noisy digitalcircuits must be located in certain areas to conform with alegacy design or form factor. In that case, splitting the groundplane may make the difference in achieving good performance.However, to make the overall design work, a bridge or tie pointis required to connect the grounds together somewhere on theboard. In this case, spread the tie points evenly across theground split planes.Often, poor assembly leads to poor system performance.Decoupling close to both the power plane entry point and theVDD pins of the converter or IC is always good; however, foradded inherent high frequency decoupling, take advantage oftight power and ground plains of 4 mils or less. There is noextra cost for this, only the extra few minutes it takes to updateone’s PCB fabrication notes.It is not easy to cover all the specifics when designing a highspeed, high resolution converter layout. Each application isunique. It is hoped that the key points provided in thisapplication note are useful to the designer to better theirunderstanding for future system designs.REFERENCESGriffin, Gary. 2006. AN-772 Application Note, A Design andManufacturing Guide for the Lead Frame Chip Scale Package(LFCSP).Kester, Walt. 2004. Analog-Digital Conversion: Seminar Series,Analog Devices, ISBN 0-916550-27-3. (Also available asThe Data Conversion Handbook, 2005, Elsevier/Newnes,ISBN 0-7506-7841-0)Rev. 0 Page 6 of 8

Application NoteAN-1142NOTESRev. 0 Page 7 of 8

AN-1142Application NoteNOTES 2012 Analog Devices, Inc. All rights reserved. Trademarks andregistered trademarks are the property of their respective owners.AN10484-0-1/12(0)Rev. 0 Page 8 of 8

AN-1142 APPLICATION NOTE OneTechnologyWay P.O.Box9106 Norwood,MA 02062-9106,U.S.A. Tel:781.329.4700 Fax:781.461.3113 www.analog.com Techniques for High Speed ADC PCB Layout b

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