Intel Quark SoC X1000 Debug Operations - Caxapa
Intel Quark SoC X1000Debug OperationsUser GuideNovember 2013Order Number: 329866-001US
ContentsContents1Introduction .41.11.22JTAG Interface.72.12.22.33TAP Instruction Table . 14Run Control. 155.15.25.35.45.55.62Initial JTAG Discovery . 12Check Core Powergood . 12Add Core TAP to the JTAG Chain . 12Verify Core IDCODE . 13JTAG Interface. 144.15SKU-Based JTAG Debug Capability .7CLTAPC Instruction Table .7CLTAPC Data Register Table .82.3.1CLIDCODE.82.3.2CLBYPASS .82.3.3CLTAPC SELECT .82.3.4CLTAPC CPU VPREQ .92.3.5CLTAPC CPU TAPSTATUS .92.3.6CLTAPC CPU VPRDY . 102.3.7CLTAPC TAPNW STATUS . 10Putting It All Together . 123.13.23.33.44Terminology .5Related Documents.5Introduction to Probe Mode . 15Probe Mode Entry . 15Probe Mode Exit . 16Reset Break . 16TAPSTATUS Register . 16Accessing Architectural Registers . 175.6.1Submitting Instructions to the Core . 175.6.1.1Instruction Faults. 175.6.2EIP Management . 185.6.3DR7 Management . 185.6.3.1EIP and Software Breakpoints . 185.6.4WRITEPIR Register Format . 185.6.5Register Read . 195.6.6Register Write . 195.6.7Special Cases for Register Access . 195.6.7.1PMCR . 195.6.7.2Register Access after HLT Instruction Execution . 195.6.8Checking for HALT State . 205.6.9Pseudo Opcodes for Architectural Register Access . 205.6.10 Probe Mode Control Register . 215.6.11 Accessing Model Specific Registers (MSR) . 22Order Number: 329866-001US
Contents5.75.85.95.105.115.12Reading and Writing Memory . 225.7.1Management of Architectural Registers for Memory Access . 225.7.1.1DS Selector . 225.7.1.2Adjust CPL Prior to Memory Access . 235.7.1.3Disable Interrupts Prior to Memory Access . 235.7.1.4Processor Cache Flush Prior to Memory Access . 235.7.1.5CR0 . 235.7.2Memory Read . 245.7.3Memory Write . 24Reading and Writing I/O Ports . 245.8.1I/O Read . 245.8.2I/O Write . 24Hardware Breakpoints . 24Software Breakpoints . 25Single Step. 25Redirections into Probe Mode . 255.12.1 Shutdown Break. 25FiguresFigure 1.Intel Quark SoC X1000 13.Terminology .5Related Documents .5CLTAPC TAP Instructions .7CLTAPC TAP Data Registers .8CLTAPC SELECT .8CLTAPC CPU VPREQ .9CLTAPC CPU TAPSTATUS .9CLTAPC TAPNW STATUS . 10TAP Instructions . 14TAPSTATUS Data Register . 16Register Access PIR Values . 21PMCR Description . 22DS Selector Values for Memory Access . 23Order Number: 329866-001US3
Introduction1IntroductionThe Intel Quark SoC X1000 processor is the next generation secure, low-powerIntel Architecture (IA) SoC for deeply embedded applications. The SoC integrates theIntel Quark SoC X1000 Core plus all the required hardware components to run offthe-shelf operating systems and to leverage the vast x86 software ecosystem. Fordetails, see the Intel Quark SoC X1000 Datasheet.The Intel Quark SoC X1000 Core (codenamed Lakemont) enables a range of lowcost, high-performance embedded system designs capable of running applicationswritten for the Intel architecture. The Intel Quark SoC X1000 Core integrates a 16Kbyte unified cache and floating-point hardware onchip for improved performance. Forfurther details, including the Intel Quark Core feature list, see the Intel Quark SoCX1000 Core Hardware Reference Manual and Intel Quark SoC X1000 CoreDeveloper’s Manual.This document assumes that the reader has some familiarity with JTAG based debugtools and the use of JTAG for run control of an execution core.This document provides details on JTAG based debug for any product based on theIntel Quark SoC X1000.Figure 1. Intel Quark SoC X10004Order Number: 329866-001US
Introduction 4 Order Number: 329866-001US 1 Introduction The Intel Quark SoC X1000 processor is the next generation secure, low-power Intel Architecture (IA) SoC for deeply embedded applications. The SoC integrates the Intel Quark SoC X1000 Core plus all the required hardware components to run off- the-shelf operating
Intel Quark TM SoC X1000 Intel Quark SoC X1000 Sitara AM3358BZCZ100 ARM Cortex M4F Broadcom BCM2835 SoC based ARM11 76JZF ARM Cortex M3 GPU - - - - PowerVR SGX530 @520 MHz - VideoCore IV Multimedia@ 250 MHz-Operating voltage 5V 5V, 3V 5V 3.3V 3.3V 3.3V 5
Chapter 4 – Quark SoC X1000 Drivers 25 e 4.3.2 Bluetooth* Driver Bluetooth functionality is provided by a mini-PCIe card connected to the mini-PCIe slot on the platform. The following cards have been validated with the AAEON Quark SoC X1000 Softwa
Building Firmware for Quark Processors “Three things cannot be long hidden: the sun, the moon, and the truth.” —The Buddha The Intel Quark SoC X1000 is Intel’s lowest-power SoC, designed to provide performance and reduce development costs
Intel Galileo gen 2 Board The Arduino Intel Galileo board is a microcontroller board based on the Intel Quark SoC X1000, a 32-bit Intel Pentium -class system on a chip (SoC). It is the first board based on Intel architecture designed to be fully pin-compatible with shields desig
Intel Galileo Intel Galileo Front Intel Galileo Back Overview Galileo is a microcontroller board based on the Intel Quark SoC X1000 Application Processor, a 32-bit Intel Pentium-class system on a chip (datasheet). It’s the first board based on Intel architecture designe
SOC/G&WS 200 Intro to LGBTQ Studies SOC 210 Survey of Sociology SOC/C&E SOC 211 The Sociological Enterprise SOC/C&E SOC/G&WS 215 Gender & Work in Rural Am SOC/ASIAN AM 220 Ethnic Movements in the US SOC/C&E SOC 222 Food, Culture, and Society x Any SOC course with a Social Sciences breadth will satisfy this prerequisite.
Send documentation comments to mdsfeedback-doc@cisco.com. Contents x Cisco MDS 9000 Family Command Reference OL-6970-03, Cisco MDS SAN-OS Release 2.x debug klm 6-70 debug license 6-72 debug logfile 6-73 debug mcast 6-75 debug mip 6-77 debug module 6-78 debug ntp 6-79
accounting standards (for domestic filing purposes) and IFRS as issued by the IASB (or other permitted equivalent standards) for the subsidiary, the parent company or the whole group (for the purposes of the EEA listing). We would urge any companies that may be affected by this change to check with the relevant EEA competent authority as soon as possible so that they are clear what .
