Xilinx DS571 LogiCORE IP XPS UART Lite (v1.02.a) Data Sheet

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LogiCORE IP XPS UART Lite(v1.02.a)DS571 June 22, 2011Product SpecificationIntroductionLogiCORE IP Facts TableThe Xilinx XPS Universal Asynchronous ReceiverTransmitter (UART) Lite Interface connects to the PLB(Processor Local Bus) and provides the controllerinterface for asynchronous serial data transfer. This softIP core is designed to interface with the PLBV46.FeaturesCore SpecificsSupportedDevice Family(1)Virtex-5,Virtex-4,Spartan-3E, Automotive Spartan-3E, Spartan-3,Automotive Spartan-3, Spartan-3A,Spartan-3AN, Automotive Spartan-3A,Spartan-3A DSP, Automotive Spartan-3A DSPSupported UserInterfacesPLB v46Resources PLB interface is based on PLB v4.6 specification Supports 8-bit bus interfaces One transmit and one receive channel (full duplex) 16-character Transmit FIFO and 16-characterReceive FIFO Configurable number of data bits in a character(5-8)Slices LUTsFFSBlock RAMsSee Table 9, Table 10 and Table 11Provided with CoreProduct SpecificationDocumentationVHDLDesign FilesExample DesignNot ProvidedNot Provided Configurable parity bit (odd or even)Test Bench Configurable baud rateConstraints FileN/ASimulationModelN/ATested Design ToolsDesign EntryToolsSimulationISE 13.2 softwareMentor Graphics ModelSim (2)XST 13.2Synthesis ToolsSupportProvided by Xilinx @ www.xilinx.com/support1.2.For a complete listing of supported devices, seeIDS Embedded Edition Derivative Device Support for this core.For the supported versions of the tool, see the ISE Design Suite13: Release Notes Guide. Copyright 2009-2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks ofXilinx in the United States and other countries. All other trademarks are the property of their respective owners.DS571 June 22, 2011Product Specificationwww.xilinx.com1

LogiCORE IP XPS UART Lite (v1.02.a)Functional DescriptionThe XPS UART Lite performs parallel-to-serial conversion on characters received through PLB andserial-to-parallel conversion on characters received from a serial peripheral.The XPS UART Lite is capable of transmitting and receiving 8, 7, 6 or 5-bit characters, with 1-stop bit and odd, evenor no parity. The XPS UART Lite can transmit and receive independently.The device can be configured and its status can be monitored via the internal register set. The XPS UART Litegenerates an interrupt when Receive FIFO becomes non-empty or when transmit FIFO becomes empty. Thisinterrupt can be masked by using an interrupt enable/disable signal.The device contains a 16-bit programmable baud rate generator and independent 16-word Transmit and ReceiveFIFOs. The FIFOs can be enabled or disabled through software control.The XPS UART Lite modules are shown in the top-level block diagram in Figure 1.X-Ref Target - Figure 1PLBUART Control ModuleUART LiteRegister ModuleRXModuleRXReceive DataFIFOPLBInterfacePLBInterfaceModuleBRGTransmit DataFIFOStatus Register(STAT REG)Control Register(CTRL igure 1: Block Diagram of XPS UART LiteThe XPS UART Lite modules are described in the next sections:PLB Interface Module: The PLB Interface Module provides the interface to the PLB and implements PLB protocollogic. PLB Interface Module is a bidirectional interface between a user IP core and the PLB bus standard. To simplifythe process of attaching an XPS UART Lite to the PLB, the core makes use of a portable, pre-designed bus interfacecalled PLB Interface Module that takes care of the bus interface signals, bus protocols, and other interfaces.UART Lite Register Module: The Register Module includes all memory-mapped registers (as shown in Figure 1).It interfaces to the PLB through the PLB Interface Module. It consists of an 8-bit status register, an 8-bit controlregister and a pair of 8-bit Transmit/Receive FIFOs. All registers are accessed directly from the PLB using the PLBInterface Module.UART Control Module: The UART Control Module consists of an RX module, a TX module, a parameterized baudrate generator (BRG), and a Control Unit. It incorporates the state machine for initialization and start and stop bitcontrol logic.DS571 June 22, 2011Product Specificationwww.xilinx.com2

LogiCORE IP XPS UART Lite (v1.02.a)InterruptsIf interrupts are enabled, an interrupt is generated when one of these two conditions is true:1. When the Receive FIFO goes from empty to not empty, such as when the first valid character is received in theReceive FIFO2. When the Transmit FIFO goes from not empty to empty, such as when the last character in the Transmit FIFO istransmittedXPS UART Lite I/O SignalsThe XPS UART Lite I/O signals are listed and described in Table 1.Table 1: XPS UART Lite I/O Signal DescriptionPortSignal NameInterfaceInitialStateI/ODescriptionSystem SignalsP1SPLB ClkSystemI-PLB clockP2SPLB RstSystemI-PLB reset, active highPLB Interface SignalsP3PLB ABus[0 : 31]PLBI-PLB address busP4PLB PAValidPLBI-PLB primary address validP5PLB masterID[0 :C SPLB MID WIDTH - 1]PLBI-P6PLB RNWPLBI-P7PLB BE[0 : (C SPLB DWIDTH/8) 1]PLBI-P8PLB size[0 : 3]PLBI-PLB size of requested transferP9PLB type[0 : 2]PLBI-PLB transfer typeP10PLB wrDBus[0 :C SPLB DWIDTH - 1]PLBI-PLB current master identifierPLB read not writePLB byte enablesPLB write data busUnused PLB Interface SignalsP11PLB UABus[0 : 31]PLBI-PLB upper address bitsP12PLB SAValidPLBI-PLB secondary address validP13PLB rdPrimPLBI-PLB secondary to primary readrequest indicatorP14PLB wrPrimPLBI-PLB secondary to primary writerequest indicatorP15PLB abortPLBI-PLB abort bus requestP16PLB busLockPLBI-PLB bus lockP17PLB MSize[0 : 1]PLBI-PLB data bus width indicatorP18PLB lockErrPLBI-PLB lock errorP19PLB wrBurstPLBI-PLB burst write transferP20PLB rdBurstPLBI-PLB burst read transferDS571 June 22, 2011Product Specificationwww.xilinx.com3

LogiCORE IP XPS UART Lite (v1.02.a)Table 1: XPS UART Lite I/O Signal Description (Cont’d)PortSignal NameInterfaceInitialStateI/ODescriptionP21PLB wrPendReqPLBI-PLB pending bus write requestP22PLB rdPendReqPLBI-PLB pending bus read requestP23PLB wrPendPri[0 : 1]PLBI-PLB pending write request priorityP24PLB rdPendPri[0 : 1]PLBI-PLB pending read request priorityP25PLB reqPri[0 : 1]PLBI-PLB current request priorityP26PLB TAttribute[0 : 15]PLBI-PLB transfer attributePLB Slave Interface SignalsP27Sl addrAckPLBO0Slave address acknowledgeP28Sl SSize[0 : 1]PLBO0Slave data bus sizeP29Sl waitPLBO0Slave waitP30Sl rearbitratePLBO0Slave bus rearbitrateP31Sl wrDAckPLBO0Slave write data acknowledgeP32Sl wrCompPLBO0Slave write transfer completeP33Sl rdDBus[0 : C SPLB DWIDTH 1]PLBO0Slave read data busP34Sl rdDAckPLBO0Slave read data acknowledgeP35Sl rdCompPLBO0Slave read transfer completeP36Sl MBusy[0 :C SPLB NUM MASTERS - 1]PLBO0Slave busyP37Sl MWrErr[0 :C SPLB NUM MASTERS - 1]PLBO0Slave write errorP38Sl MRdErr[0 :C SPLB NUM MASTERS - 1]PLBO0Slave read errorUnused PLB Slave Interface SignalsP39Sl wrBTermPLBO0Slave terminate write burst transferP40Sl rdWdAddr[0 : 3]PLBO0Slave read word addressP41Sl rdBTermPLBO0Slave terminate read burst transferP42Sl MIRQ[0 :C SPLB NUM MASTERS - 1]PLBO0Master interrupt requestUART Lite Interface SignalsP43RXUART LiteI-Receive DataP44TXUART LiteO0Transmit DataP45InterruptUART LiteO0UART InterruptDS571 June 22, 2011Product Specificationwww.xilinx.com4

LogiCORE IP XPS UART Lite (v1.02.a)XPS UART Lite Design ParametersTo allow the user to obtain an XPS UART Lite that is uniquely tailored for the system, certain features can beparameterized in the XPS UART Lite design. This allows the user to configure a design that utilizes the resourcesrequired by the system only and that operates with the best possible performance. The features that can beparameterized in the XPS UART Lite design are as shown in Table 2.Table 2: XPS UART Lite Design ParametersGenericFeature/DescriptionParameter NameDefaultValueAllowable ValuesVHDL TypeSystem ParameterG1Target FPGA familyC FAMILYspartan3e, aspartan3e,spartan3,aspartan3,spartan3a, spartan3an,aspartan3a,spartan3adsp,aspartan3adsp, virtex4,qvirtex4, qrvirtex4, virtex5virtex5stringG2System clock frequency (inHz) driving the UART LiteperipheralC SPLB CLKFREQ HZinteger (ex. 100000000)100000000IntegerPLB ParametersG3PLB Base AddressC BASEADDRValid Address(1)None(3)std logicvectorG4PLB High AddressC HIGHADDRValid Address(2)None(3)std logicvectorG5PLB least significant addressbus widthC SPLB AWIDTH3232integerG6PLB data widthC SPLB DWIDTH32, 64, 12832integerG7Selects point-to-point orshared bus topologyC SPLB P2P0 Shared Bus Topology1 Point-to-Point BusTopology(4)0integerG8PLB Master ID Bus WidthC SPLB MIDWIDTHlog2(C SPLB NUMMASTERS) with aminimum value of 11integerG9Number of PLB MastersC SPLB NUMMASTERS1 - 161integerG10Support BurstsC SPLB SUPPORTBURSTS00integerG11Width of the Slave Data BusC SPLB NATIVEDWIDTH3232integer128000 RDIntegerUART Lite ParametersG12Baud rate of the UART Lite inbits per secondC BAUDRATEinteger (ex. 128000)Red [5]G13The number of data bits inthe serial frameDS571 June 22, 2011Product SpecificationC DATA BITSwww.xilinx.com5-88Integer5

LogiCORE IP XPS UART Lite (v1.02.a)Table 2: XPS UART Lite Design Parameters (Cont’d)GenericFeature/DescriptionParameter NameG14Determines whether parity isused or notC USE PARITYG15If parity is used, determines C ODD PARITYwhether parity is odd or evenDefaultValueAllowable ValuesVHDL Type0 Do not use parity1 Use parity1Integer0 Even parity1 Odd parity1IntegerNotes:1.2.3.4.5.The user must set the values. The C BASEADDR must be a multiple of the range, where the range is C HIGHADDR C BASEADDR 1.C HIGHADDR - C BASEADDR must be a power of 2 greater than equal to C BASEADDR 0xF.No default value is specified to ensure that the actual value is set; that is, if the value is not set, a compiler error is generated.Value of ’1’ is not supported in this core.With a baud rate of 115200, the sample clock is 16 * 115200 1.8432 MHz. With the System clock C CLK FREQ running at 10MHz, the integer ratio for driving the sample clock is 5 (rounding of [10/1.8432]). The UART Lite then divides the System clock by5 resulting in 2 MHz for the sample clock. The baud rate error is (1.8432 - 2) /1.8432 -8.5% which is outside the tolerance formost UARTs. The issue is that the higher the baud rate and the lower the C CLK FREQ, the greater the error in the generatedbaud rate of the UART Lite. Specifications for the baud rate error state that within 5% of the requested rate is consideredacceptable.Allowable Parameter CombinationsThe address range specified by C BASEADDR and C HIGHADDR must be a power of 2, and must be at least 0xF.For example, if C BASEADDR 0xE0000000, C HIGHADDR must be at least 0xE000000F.XPS UART Lite Parameter - Port DependenciesThe dependencies between the XPS UART Lite core design parameters and I/O signals are described in Table 3. Inaddition, when certain features are parameterized out of the design, the related logic will no longer be a part of thedesign. The unused input signals and related output signals are set to a specified value.Table 3: XPS UART Lite Parameter-Port DependenciesGenericor PortNameAffectsDependsRelationship DescriptionDesign ParametersG6C SPLB DWIDTHP7, P10, P33-Affects the number of bits in data busG8C SPLB MID WIDTHP5G9This value is calculated as:log2(C SPLB NUM MASTERS) witha minimum value of 1G9C SPLB NUM MASTERSP36, P37, P38,P42-Affects the number of PLB mastersI/O SignalsP5PLB masterID[0 :C SPLB MID WIDTH - 1]-G8Width of the PLB mastedID variesaccording to C SPLB MID WIDTHP7PLB BE[0 : (C SPLB DWIDTH/8) -1]-G6Width of the PLB BE varies accordingto C SPLB DWIDTHP10PLB wrDBus[0 : C SPLB DWIDTH - 1] -G6Width of the PLB wrDBus variesaccording to C SPLB DWIDTHP33Sl rdDBus[0 : C SPLB DWIDTH - 1]G6Width of the Sl rdDBus variesaccording to C SPLB DWIDTHDS571 June 22, 2011Product Specification-www.xilinx.com6

LogiCORE IP XPS UART Lite (v1.02.a)Table 3: XPS UART Lite Parameter-Port Dependencies (Cont’d)Genericor PortNameAffectsDependsRelationship DescriptionP36Sl MBusy[0 :C SPLB NUM MASTERS - 1]-G9Width of the Sl MBusy variesaccording toC SPLB NUM MASTERSP37Sl MWrErr[0 :C SPLB NUM MASTERS - 1]-G9Width of the Sl MWrErr variesaccording toC SPLB NUM MASTERSP38Sl MRdErr[0 :C SPLB NUM MASTERS - 1]-G9Width of the Sl MRdErr variesaccording toC SPLB NUM MASTERSP42Sl MIRQ[0 :C SPLB NUM MASTERS - 1]-G9Width of the Sl MIRQ varies accordingto C SPLB NUM MASTERSXPS UART Lite Register DescriptionsTable 4 shows all the XPS UART Lite registers and their addresses.Table 4: XPS UART Lite RegistersBase Address Offset(hex)Register NameAccessTypeDefaultValue (hex)DescriptionC BASEADDR 0x0Rx FIFO(3)Read(1)0x0Receive Data FIFOC BASEADDR 0x4TxFIFO(3)Write(2)0x0Transmit Data FIFOC BASEADDR 0x8STAT REG(3)Read(1)0x4UART Lite Status RegisterC BASEADDR 0xCCTRL REG(3)Write(2)0x0UART Lite Control Register1.2.3.Writing of a read only register has no effect.Reading of a write only register returns zero.Registers are defined for full 32-bit access only. Any partial word accesses (byte or halfword) have undefined results and returns abus error.Receive Data FIFOThis 16 entry deep FIFO contains data to be received by XPS UART Lite. The FIFO bit definitions are shown inTable 5. Reading of this location will result in reading the current word out from the FIFO. When a read request isissued to an empty FIFO a bus error is generated and the result is undefined. The Receive Data FIFO is a read-onlyregister. Issuing a write request to Receive Data FIFO will do nothing but generate the write acknowledgement.Figure 2 shows the location for data on the PLB when C DATA BITS is set to 8.X-Ref Target - Figure 2Rx Data023 2431ReservedFigure 2: Receive Data FIFO (C DATA BITS 8)DS571 June 22, 2011Product Specificationwww.xilinx.com7

LogiCORE IP XPS UART Lite (v1.02.a)Table 5: Receive Data FIFO Bit on0 - [31-C DATA BITS]ReservedN/A0Reserved[(31-C DATA BITS) 1] - 31Rx DataRead0UART Receive dataTransmit Data FIFOThis 16 entry deep FIFO contains data to be output by XPS UART Lite. The FIFO bit definitions are shown inTable 6. Data to be transmitted is written into this register. This is write only location. Issuing a read request toTransmit Data FIFO generates the read acknowledgement with zero data. Figure 3 shows the location for data onthe PLB when C DATA BITS is set to 8.X-Ref Target - Figure 3Tx Data023 2431ReservedFigure 3: Transmit Data FIFO (C DATA BITS 8).Table 6: Transmit Data FIFO Bit on0 - [31-C DATA BITS]ReservedN/A0Reserved[(31-C DATA BITS) 1] - 31Tx DataWrite0UART transmit dataUART Lite Control Register (CTRL REG)The UART Lite Control Register contains the Enable Interrupt bit and Reset pin for Receive and Transmit DataFIFO. This is write only register. Issuing a read request to Control Register generates the read acknowledgementwith zero data. Figure 4 shows the bit assignment of the CTRL REG. Table 7 describes this bit assignment.X-Ref Target - Figure 4ReservedEnable Intr Rst Tx FIFO026 27 28 29 30 31ReservedRst Rx FIFOFigure 4: UART Lite Control RegisterDS571 June 22, 2011Product Specificationwww.xilinx.com8

LogiCORE IP XPS UART Lite (v1.02.a)Table 7: UART Lite Control Register Bit on0 - 26ReservedN/A0Reserved27Enable IntrWrite’0’Enable Interrupt for the UART Lite’0’ Disable interrupt signal’1’ Enable interrupt signal28 - 29ReservedN/A0Reserved30Rst Rx FIFOWrite’0’Reset/Clear the Receive FIFOWriting a ’1’ to this bit position clears the ReceiveFIFO’0’ Do nothing’1’ Clear the Receive FIFO31Rst Tx FIFOWrite’0’Reset/Clear the Transmit FIFOWriting a ’1’ to this bit position clears the TransmitFIFO’0’ Do nothing’1’ Clear the Transmit FIFOUART Lite Status Register (STAT REG)The UART Lite Status Register contains the status of the Receive and Transmit Data FIFO, if interrupts are enabled,and if there are any errors. This is read only register. If a write request is issued to status register it will do nothingbut generate write acknowledgement. Bit assignment in the STAT REG is shown in Figure 5 and described inTable 8.X-Ref Target - Figure 5Intr EnabledFrame ErrorReserved0Rx FIFOValid DataTx FIFOEmpty23 24 25 26 27 28 29 30 31OverrunRx FIFO FullErrorParity Error Tx FIFO FullFigure 5: UART Lite Status RegisterDS571 June 22, 2011Product Specificationwww.xilinx.com9

LogiCORE IP XPS UART Lite (v1.02.a)Table 8: UART Lite Status Register Bit DefinitionsBit(s)NameCore AccessReset Value0 - 23ReservedN/A0Reserved’0’Indicates that a parity error has occurred after thelast time the status register was read. If the UART isconfigured without any parity handling, this bit isalways ’0’.The received character is written into the ReceiveFIFO.This bit is cleared when the status register is read’0’ No parity error has occurred’1’ A parity error has occurred’0’Indicates that a frame error has occurred after thelast time the status register was read. Frame Error isdefined as detection of a stop bit with the value ’0’.The receive character is ignored and not written tothe Receive FIFO.This bit is cleared when the status register is read’0’ No Frame error has occurred’1’ A frame error has occurred24Parity Error25Frame ErrorReadReadDescription26Overrun ErrorRead’0’Indicates that a overrun error has occurred since thelast time the status register was read. Overrun iswhen a new character has been received but theReceive FIFO is full. The received character isignored and not written into the Receive FIFO. Thisbit is cleared when the status register is read’0’ No interrupt has occurred’1’ Interrupt has occurred27Intr EnabledRead’0’Indicates that interrupts is enabled’0’ Interrupt is disabled’1’ Interrupt is enabled28Tx FIFO FullRead’0’Indicates if the Transmit FIFO is full’0’ Transmit FIFO is not full’1’ Transmit FIFO is full29Tx FIFO EmptyRead’1’Indicates if the Transmit FIFO is empty’0’ Transmit FIFO is not empty’1’ Transmit FIFO is empty30Rx FIFO FullRead’0’Indicates if the Receive FIFO is full’0’ Receive FIFO is not full’1’ Receive FIFO is full31Rx FIFO ValidDataRead’0’Indicates if the receive FIFO has valid data’0’ Receive FIFO is empty’1’ Receive FIFO has valid dataDS571 June 22, 2011Product Specificationwww.xilinx.com10

LogiCORE IP XPS UART Lite (v1.02.a)Design ImplementationTarget TechnologyThe intended target technology is Virtex -4, Virtex-5 and Spartan -3 family FPGAs.Device Utilization and Performance BenchmarksCore PerformanceBecause the XPS UART Lite core will be used with other design modules in the FPGA, the utilization and timingnumbers reported in this section are estimates only. When the XPS UART Lite core is combined with other designsin the system, the utilization of FPGA resources and timing of the XPS UART Lite design will vary from the resultsreported here.The XPS UART Lite resource utilization for various parameter combinations measured with Virtex-4 FPGAs as thetarget device are detailed in Table 9.Table 9: Performance and Resource Utilization Benchmarks on Virtex-4 (xc4vlx25-10-ff668)C BAUDRATEC DATA BITSC USE PARITYC ODD PARITYPerformanceC CLK FREQDevice ResourcesC SPLB AWIDTHParameter Values (other parameters at default value)Slices32100 000 00019 2005FALSEFALSE988312314532100 000 00019 2006FALSEFALSE1008412713232100 000 00019 2007FALSEFALSE1008512916832100 000 00019 2008FALSEFALSE101861311223240 000 00038 4008FALSEFALSE1008513012532100 000 00019 2006TRUEFALSE1049013411732100 000 00019 2007TRUEFALSE10591136149DS571 June 22, 2011Product Specificationwww.xilinx.comSliceFlipFlopsLUTsFMAX (MHz)11

LogiCORE IP XPS UART Lite (v1.02.a)The XPS UART Lite resource utilization for various parameter combinations measured with Virtex-5 FPGAs as thetarget device are detailed in Table 10.Table 10: Performance and Resource Utilization Benchmarks on Virtex-5 (xc5vlx85-1-ff1153)C ODD PARITYfMAX (MHz)C USE PARITYLUTsC DATA BITSSliceFlipFlopsC BAUDRATEPerformanceC CLK FREQDevice ResourcesC SPLB AWIDTHParameter Values (other parameters at default value)Slices32100 000 00019 2005FALSEFALSE979013712632100 000 00019 2006FALSEFALSE928513711932100 000 00019 2007FALSEFALSE918513015832100 000 00019 2008FALSEFALSE96861391153240 000 00038 4008FALSEFALSE928513711932100 000 00019 2006TRUEFALSE979013712632100 000 00019 2007TRUEFALSE9991139116The XPS UART Lite resource utilization for various parameter combinations measured with Spartan-3E FPGAs asthe target device are detailed in Table 11.Table 11: Performance and Resource Utilization Benchmarks on Spartan-3E (xc3s250e-4-ft256)C ODD PARITYfMAX (MHz)C USE PARITYLUTsC DATA BITSSliceFlipFlopsC BAUDRATEPerformanceC CLK FREQDevice ResourcesC SPLB AWIDTHParameter Values (other parameters at default value)Slices32100 000 00019 2005FALSEFALSE978312510832100 000 00019 2006FALSEFALSE988412910232100 000 00019 2007FALSEFALSE978312510832100 000 00019 2008FALSEFALSE98841291023240 000 00038 4008FALSEFALSE1008513111732100 000 00019 2006TRUEFALSE1069013610832100 000 00019 2007TRUEFALSE10085131117DS571 June 22, 2011Product Specificationwww.xilinx.com12

LogiCORE IP XPS UART Lite (v1.02.a)System PerformanceTo measure the system performance (Fmax) of this core, this core was added to a Virtex-4 FPGA system, a Virtex-5FPGA system, and a Spartan-3A FPGA system as the Device Under Test (DUT) as shown in Figure 6, Figure 7, andFigure 8.Because the XPS UART Lite core will be used with other design modules in the FPGA, the utilization and timingnumbers reported in this section are estimates only. When this core is combined with other designs in the system,the utilization of FPGA resources and timing of the design will vary from the results reported here.X-Ref Target - Figure 6PLBV46MPMCPLBV46XPS CDMAXPS CDMADUTIPLB1 DPLB1DPLB0PPC405PLBV46IPLB0XPS BRAMXPS INTCXPS GPIOXPS UARTLitev4 fx sysFigure 6: Virtex-4 FX SystemX-Ref Target - Figure 7XCLMPMCXCLMicroBlazeXPS CDMAXPS CDMADUTPLBV46XPS BRAMXPS INTCXPS GPIOXPS UARTLiteMDMv5 lxt sysFigure 7: Virtex-5 LX SystemDS571 June 22, 2011Product Specificationwww.xilinx.com13

LogiCORE IP XPS UART Lite (v1.02.a)X-Ref Target - Figure 8MPMCMicroBlazeXPS CDMAXPS CDMADUTPLBV46XPS BRAMXPS INTCXPS GPIOXPS UARTLiteMDMsp3 dsp sysFigure 8: Spartan-3A SystemThe target FPGA was then filled with logic to drive the LUT and block RAM utilization to approximately 70% andthe I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the targetFPGA, the resulting target Fmax numbers are shown in Table 12.Table 12: XPS UART Lite System PerformanceTarget FPGATarget fMAX (MHz)S3A700 -490V4FX60 -10100V5LXT50 -1120The target Fmax is influenced by the exact system and is provided for guidance. It is not a guaranteed value acrossall systems.Ordering InformationThis Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite EmbeddedEdition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISEEmbedded Edition software (EDK).Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.For information on pricing and availability of other Xilinx LogiCORE IP modules and software, contact your localXilinx sales representative.Reference DocumentsIBM CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6).DS571 June 22, 2011Product Specificationwww.xilinx.com14

LogiCORE IP XPS UART Lite (v1.02.a)List of AcronymsAcronymSpelled OutBRGBaud Rate GeneratorDSPDigital Signal ProcessingDUTDevice Under TestFFFlip-FlopFIFOFirst In First OutFMAXMaximum FrequencyFPGAField Programmable Gate ArrayI/OInput OutputLUTLookup TableMHzMegaHertzPLBProcessor Local BusRAMRandom Access MemoryRXReceiveTXTransmitUARTUniversal Asynchronous Receiver TransmitterXPSXilinx Platform StudioRevision HistoryDateVersion4/18/071.0Initial Xilinx release.4/20/071.1Added SP-3 support.9/26/071.2Added FMax Margin RD Red System Performance section.11/27/071.3Added SP3A DSP to supported devices listing.1/14/081.4Added Virtex-II Pro support.4/21/081.5Added Automotive Spartan-3E, Automotive Spartan-3A, Automotive Spartan-3,and Automotive Spartan-3A DSP support.7/18/081.6Added QPro Virtex-4 Hi-Rel and QPro Virtex-4 Rad Tolerant FPGA support.9/20/081.7Updated to version v1.01a. Removed Virtex-II Pro support. Modified Interruptsand Register description sections.6/22/111.8Updated to version v1.02a.Updated the interrupts section.DS571 June 22, 2011Product SpecificationRevisionwww.xilinx.com15

LogiCORE IP XPS UART Lite (v1.02.a)Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. Tothe maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx herebyDISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOTLIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULARPURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory ofliability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (includingyour use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including lossof data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if suchdamage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes noobligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to productspecifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed athttp://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued toyou by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safeperformance; you assume sole risk and liability for use of Xilinx products in Critical itapps.DS571 June 22, 2011Product Specificationwww.xilinx.com16

Spartan-3E, Automotive Spartan-3E, Spartan-3, Automotive Spartan-3, Spartan-3A, . It incorporates the state machine for initialization and start and stop bit control logic. X-Ref Target - Figure 1 Figure 1: Block Diagram of XPS . integer (ex. 100000000) 100_ 000_ 000 Integer PLB Para

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These educators volunteered to serve on eleven (11) English Languag e Arts grade level writing teams that met in Columbus, Ohio monthly from January to June 2017 to review the model curriculum and make updates to all current sections based on the need for clarity, detail, and relevance to the recently revised learning standards. Specialists also volunteered for resource teams that met .