ECE 410: VLSI Design Course Lecture Notes

ECE 410: VLSI DesignCourse Lecture Notes(Uyemura textbook)Professor Andrew MasonMichigan State UniversityECE 410, Prof. A. MasonLecture Notes Page 2.1

CMOS Circuit Basics CMOS complementary MOS– uses 2 types of MOSFETsdrainsourcegategateto create logic functions nMOSsourcedrainnMOS pMOSpMOS CMOS Power SupplyVDD– typically single power supply– VDD, with Ground referenceVDD typically uses single power supply VDD varies from 5V to 1V Logic Levels -CMOSlogiccircuit– Logic ‘1’ VDD– Logic ‘0’ ground 0VECE 410, Prof. A. MasonCMOSlogiccircuitVVDD– all voltages between 0V and VDD logic 1voltagesundefinedlogic 0voltagesLecture Notes Page 2.2

Transistor Switching Characteristics nMOS– switching behaviordrain Vout on closed, when Vin VtnVin– Vtn nMOS “threshold voltage”– Vin is referenced to ground, Vin Vgs off open, when Vin Vtngate Vgs-nMOSVgs Vtn onsource pMOS– switching behavior Vsg on closed, when Vin VDD - Vtp – Vtp pMOS “threshold voltage” magnitude Vingate– Vin is referenced to ground, Vin VDD-Vsg off open, when Vin VDD - Vtp nMOSsourcepMOSpMOSVsg Vtp onVsg VDD - VindrainRule to Remember: ‘source’ is at lowest potential for nMOS highest potential for pMOSECE 410, Prof. A. MasonLecture Notes Page 2.3

Transistor Digital Behavior nMOSdrainVin Vout (drain)1Vs 0 device is ON0?device is OFFVin pMOSVin Vout (drain)1?device is OFF0Vs VDD 1 device is ONgate Vgs- VsgVingateVinpMOSVDDVDD- Vtp nMOSnMOSVgs Vtn onsourcepMOSsourcepMOSVsg Vtp onVsg VDD - VinVoutoffononVtndrainVoutoffnMOSNotice:When Vin low, nMOS is off, pMOS is onWhen Vin high, nMOS is on, pMOS is offÆ Only one transistor is on for each digital voltageECE 410, Prof. A. MasonLecture Notes Page 2.4

MOSFET Pass Characteristics Pass characteristics: passing of voltage from drain (or source) tosource (or drain) when device is ON (via gate voltage) Each type of transistor is better than the other at passing (tooutput) one digital voltage– nMOS passes a good low (0) but not a good high (1)– pMOS passes a good high (1) but not a good low (0)VDDVDDnMOSON when gateis ‘high’?0VVDD0VON when gateis ‘low’VDD0V?0VVy VDDPasses a good lowMax high is VDD-VtnVy VDD-VtnVy 0 VpMOS Vgs Vtn?-Vsg Vtp ? Passes a good highMin low is Vtp Vy Vtp Rule to Remember‘source’ is at lowest potential for nMOS and at highest potential for pMOSECE 410, Prof. A. MasonLecture Notes Page 2.5

MOSFET Terminal Voltages How do you find one terminal voltage if the other 2 are known?– nMOS case 1) if Vg Vi Vtn, then Vo ViVo– here Vi is the “source” so the nMOS will pass Vi to Vo case 2) if Vg Vi Vtn, then Vo Vg-VtnVgVi(Vg-Vi Vtn)– here Vo is the “source” so the nMOS output is limitedFor nMOS, max(Vo) Vg-Vtn– pMOS case 1) if Vg Vi - Vtp , then Vo ViVi(Vg-Vi Vtn)(Vi-Vg Vtp )– here Vi is the “source” so the pMOS will pass Vi to Vo case 2) if Vg Vi - Vtp , then Vo Vg Vtp (Vi-Vg Vtp )VgVo– here Vo is the “source” so the pMOS output is limitedFor pMOS, min(Vo) Vg Vtp IMPORTANT:Rules only apply if the devices is ON (e.g., Vg Vtn for nMOS)ECE 410, Prof. A. MasonLecture Notes Page 2.6

MOSFET Terminal Voltages: Examples– nMOS rules max(Vo) Vg-Vtn case 1) if Vg Vi Vtn, then Vo Vi case 2) if Vg Vi Vtn, then Vo Vg-Vtn nMOS examples (Vtn 0.5V)1.5 VoVo 2– 1: Vg 5V, Vi 2V Vg 5 Vi Vtn 2.5 Vo 2V(Vg-Vi Vtn)(Vg-Vi Vtn)Vg5acts asthe sourceVg2– 2: Vg 2V, Vi 2V2Vi source Vg 2 Vi Vtn 2.5 Vo 1.5V– pMOS rules2Vimin(Vo) Vg Vtp case 1) if Vg Vi - Vtp , then Vo Vi(Vi-Vg Vtp ) case 2) if Vg Vi - Vtp , then Vo Vg Vtp (Vi-Vg Vtp ) pMOS examples (Vtp -0.5V)5Vi source– 1: Vg 2V, Vi 5V Vg 2 Vi- Vtp 4.5 Vo 5V– 2: Vg 2V, Vi 2V Vg2Vg 2 Vi- Vtp 1.5 Vo 2.5VECE 410, Prof. A. Mason2ViVg2Vo 52.5 Voacts asthe sourceLecture Notes Page 2.7

Switch-Level Boolean Logic Logic gate are created by using sets of controlled switchesCharacteristics of an assert-high switchnMOS acts like anassert-high switch– y x A, i.e. y x if A 1AND, or multiply functionSeries switches AND functionParallel switches OR functiona AND bECE 410, Prof. A. Masona OR bLecture Notes Page 2.8

Switch-Level Boolean Logic Characteristics of an assert-low switchy xy ?– y x A, i.e. y x if A 0Series assert-low switches ?abpMOS acts like anassert-low switcherror in figure 2.5NOT function, combining asserthigh and assert-low switchesNOT (a OR b)NORRemember This?a b a b,DeMorgan relationsa 1 SW1 closed, SW2 open y 0 aa b a ba 0 SW1 open, SW2 closed y 1 aECE 410, Prof. A. MasonLecture Notes Page 2.9

CMOS “Push-Pull” Logic CMOS Push-Pull Networks– pMOS “on” when input is low pushes output high– nMOSinputs “on” when input is high pulls output lowassert-low pMOSlogicoutputassert-highnMOSlogic Operation: for a given logic function– one logic network (p or n) produces the logic functionand pushes or pulls the output– the other network acts as a “load” to complete thecircuit, but is turned off by the logic inputs– since only one network it active, there is no staticcurrent (between VDD and ground) zero static power dissipationECE 410, Prof. A. MasonLecture Notes Page 2.10

Creating Logic Gates in CMOS All standard Boolean logic functions (INV, NAND, OR, etc.) can beproduced in CMOS push-pull circuits. Rules for constructing logic gates using CMOS––––use a complementary nMOS/pMOS pair for each inputconnect the output to VDD through pMOS txsconnect the output to ground through nMOS txsinsure the output is always either high or lowinputs CMOS produces “inverting” logic– CMOS gates are based on the inverter– outputs are always inverted logic functionsassert-low pMOSlogicoutputassert-highnMOSlogice.g., NOR, NAND rather than OR, AND Logic PropertiesDeMorgan’s Rules(a b)’ a’ b’(a b)’ a’ b’Useful Logic Properties1 x 1 0 x x1 x x 0 x 0x x’ 1 x x’ 0a a a a a aab ac a (b c)ECE 410, Prof. A. MasonProperties which can be proven(a b)(a c) a bca a'b a bLecture Notes Page 2.11

Review: Basic Transistor OperationCMOS Circuit Basicsinputsassert-low pMOSlogicoutputassert-highnMOSlogic VsgVinsourcepMOSVsg Vtp onVsg VDD - VingatedrainVg Vin Vout0 1 on closed1 ? off opendrainVingatenMOSVgs Vtn on Vgs-sourceVg Vin Vout0 ? off open1 0 on closedVinpMOSVDDVDD- Vtp offononVtnoffnMOSCMOS Pass Characteristics‘source’ is at lowest potential (nMOS) and highest potential (pMOS)VDDVDDnMOSVDD0V0V0VVDD0VVy VDD Vsg Vtp Vy Vtp ECE 410, Prof. A. MasonnMOS–––Vy VDD-VtnVy 0 VpMOS Vgs Vtn- 0 in Æ 0 outVDD in Æ VDD-Vtn outstrong ‘0’, weak ‘1’pMOS–––VDD in Æ VDD out0 in Æ Vtp outstrong ‘1’, weak ‘0’Lecture Notes Page 2.12

Review: Switch-Level Boolean Logic assert-high switch– y x A, i.e. y x if A 1a AND b– series AND– parallel OR a OR bassert-low switch x– y x A, i.e. y x if A 0– series NORabNOT (a OR b)– parallel NANDECE 410, Prof. A. MasonLecture Notes Page 2.13

CMOS Inverter Inverter Function Inverter Symbol toggle binary logic of a signalxyTable Inverter Switch Operation Inverterx Truthy x VDD01Vin VDD10 CMOS Inverter Schematicinput low Æ output highnMOS off/openpMOS on/closedpMOS “on”Æ output high (1)input high Æ output lownMOS on/closedpMOS off/opennMOS “on”Æ output low (0)ECE 410, Prof. A. Mason VsgVinpMOSVout Vin Vgs-nMOSLecture Notes Page 2.14

nMOS Logic Gates We will look at nMOS logic first, more simple than CMOS nMOS Logic (no pMOS transistors)– assume a resistive load to VDD– nMOS switches pull output low based on inputsVDDnMOS InverterVDD VDD(b) nMOS is onÆ output is low (0)VDDnMOS NORnMOS NANDc abc a b (a) nMOS is offÆ output is high (1)parallel switches OR functionnMOS pulls low (NOTs the output) series switches AND functionnMOS pulls low (NOTs the output)ECE 410, Prof. A. MasonLecture Notes Page 2.15

CMOS NOR Gate NOR Truth Table NOR Symbolx yx0011x yy Karnaugh map“true” termsy 01010100x0101x y1000“false” termsg(x,y) x y 1 x 0 y 0 construct Sum of Products equation with all termseach term represents a MOSFET path to theoutput‘1’ terms are connected to VDD via pMOS‘0’ terms are connected to ground via nMOSECE 410, Prof. A. MasonLecture Notes Page 2.16

CMOS NOR Gate CMOS NOR Schematicg(x,y) x y 1 x 0 y 0x yg(x,y) x yx output is LOW if x OR y is true parallel nMOSoutput is HIGH when x AND y are false series pMOS Notice: series-parallel arrangement– when nMOS in series, pMOS in parallel, and visa versa– true for all static CMOS logic gates– allows us to construct more complex logic functionsECE 410, Prof. A. MasonLecture Notes Page 2.17

CMOS NAND Gate Truth Table NAND Symbolx yx yx0011x yy CMOS Schematic0101 K-map1110y 01011110xg(x,y) (y 1) (x 1) (x y 0)x g(x,y) x yyx output is LOW if x AND y are true series nMOSoutput is HIGH when x OR y is false parallel pMOSECE 410, Prof. A. MasonLecture Notes Page 2.18

3-Input Gates Alternate Schematic NOR3 what function?xx y zxyzyzg(x,y) x y z NAND3xxyyxg(x,y) x y zyxyzz note shared gate inputszxyxyz is input order important?in series, parallel, both? this schematic resembles how thecircuit will look in physical layoutECE 410, Prof. A. MasonLecture Notes Page 2.19

Complex Combinational Logic General logic functions– for examplef a (b c),f (d e) a (b c) How do we construct the CMOS gate?– use DeMorgan principles to modify expression construct nMOS and pMOS networksa b a ba b a b– use Structured Logic (covered only briefly in ECE410) AOI (AND OR INV) OAI (OR AND INV)ECE 410, Prof. A. MasonLecture Notes Page 2.20

Using DeMorgan DeMorgan Relations– NAND-OR rule pMOS and bubble pushing– Parallel-connected pMOSa b a b bubble pushing illustrationxxyyxequivalenttox yx yyg(x,y) x y x y assert-low OR creates NAND function bubbles inversions– NOR-AND rulexy– Series-connected pMOSa b a bx yyxxxequivalenttox yxyx yx yyyg(x,y) x y x yto implement pMOS this way, must push all bubblesto the inputs and remove all NAND/NOR output bubblesECE 410, Prof. A. Mason assert-low AND creates NOR functionLecture Notes Page 2.21

Review: CMOS NAND/NOR Gates NOR Schematic NAND Schematicxxyg(x,y) x yg(x,y) x yyxx output is LOW if x OR y is true parallel nMOSoutput is HIGH when x AND y are false series pMOS output is LOW if x AND y are true series nMOSoutput is HIGH when x OR y is false parallel pMOSECE 410, Prof. A. MasonLecture Notes Page 2.22

Rules for Constructing CMOS GatesThe Mathematical Method Given a logic functionF f(a, b, c) Reduce (using DeMorgan) to eliminate inverted operations– inverted variables are OK, but not operations (NAND, NOR) Form pMOS network by complementing the inputsFp f(a, b, c) Form the nMOS network by complementing the outputFn f(a, b, c) F Construct Fn and Fp using AND/OR series/parallelMOSFET structuresx– series AND, parallel OREXAMPLE:g(x,y) x yF ab yxFp a b a b;OR/parallelFn ab ab;AND/seriesECE 410, Prof. A. MasonLecture Notes Page 2.23

CMOS Combinational Logic Example Construct a CMOS logic gate to implement the function:F a (b c)aFb14 transistors (cascaded gates)c pMOS nMOS– Apply DeMorgan expansionsF a (b c)F a (b c)– Invert inputs for pMOSFp a (b c)– Invert output for nMOS6 transistors(CMOS)Fn a (b c)– Apply DeMorgannone neededab– Resulting Schematic– Resulting SchematiccF a(b c)aF a(b c)bcaabcbcF a(b c)ECE 410, Prof. A. MasonLecture Notes Page 2.24

Structured Logic Recall CMOS is inherently Inverting logic Can used structured circuits to implement general logicfunctions AOI: implements logic function in the orderAND, OR, NOT (Invert)– Example: F a b c d operation order: i) a AND b, c AND d, ii) (ab) OR (cd), iii) NOT– Inverted Sum-of-Products (SOP) form OAI: implements logic function in the orderOR, AND, NOT (Invert)– Example: G (x y) (z w) operation order: i) x OR y, z OR w, ii) (x y) AND (z w), iii) NOT– Inverted Product-of-Sums (POS) form Use a structured CMOS array to realize such functionsECE 410, Prof. A. MasonLecture Notes Page 2.25